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Power management fix for 6.6-rc1
Fix an Intel RAPL power capping driver regression introduced during the 6.5 development cycle (Srinivas Pandruvada). -----BEGIN PGP SIGNATURE----- iQJGBAABCAAwFiEE4fcc61cGeeHD/fCwgsRv/nhiVHEFAmT7cZ4SHHJqd0Byand5 c29ja2kubmV0AAoJEILEb/54YlRxnGMP/2z7SYBn8wBSmweORYVmi7PeWcOv4kuI 4TALaieUTNQHhMFMk4tvjkp8wy1zXSjfxobLbnw1Ak0d3QOggxb/AMHF0RHKCE44 /gUKlPpN4hlajjMTDARwBfrQXDY3W+rg/9x3MZlUMXZpLLTo3EO0XWlQzqgqT+h7 nbEXtZa0zFaZVjOb/lKoNUk5xVcgLg3wuKn5hZiKg/wCMDW+MYvNAFQfGP6i2jaI NJsnswWEZARvTWvrduvE4BfxwH0h4t+82rpp31ARWGGir1xA02ysk1iKjoli3Tf4 ESW80VMIRGaSl4gxuAqonhlx45/daK7ySJABQR3DFSb7ol+ytoITDP3FP4lp4r/0 AjgwfguTdOeg8mzn5NC0LyQJu2JHP8hHOLBzN0Y1S1MLN17nyX7HvakOgFuRuZud NAlJ6kn+8ofxMMo/Dt6vsZ4059cVZ4h7j6rXqoeSKplsLphwBjDGE2s/osug9kXU g7AKy1E9f+iCrc3OwOE7CGzWXZcoRpqE45oqSiMokoZLdP8u80sY2u+912w7yaXd /+TjpURs4l3DwzQH0uoIJhWz+OeL6Nwd1hOdrbP1YnOlgPMdvqGIgh2RIDtRJOZP EpAdOt0OR6qUyyggkkVDkAW7PLRfxwSxYS0G+9aK3j5qGgRC0GSKwoHqPDcCtC8x P3AGg6Gfjdy7 =XadJ -----END PGP SIGNATURE----- Merge tag 'pm-6.6-rc1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull power management fix from Rafael Wysocki: "Fix an Intel RAPL power capping driver regression introduced during the 6.5 development cycle (Srinivas Pandruvada)" * tag 'pm-6.6-rc1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: powercap: intel_rapl: Fix invalid setting of Power Limit 4
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commit
fd88c59e79
@ -658,8 +658,6 @@ static struct rapl_primitive_info rpi_msr[NR_RAPL_PRIMITIVES] = {
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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[PL2_CLAMP] = PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48,
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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[PL4_ENABLE] = PRIMITIVE_INFO_INIT(PL4_ENABLE, POWER_LIMIT4_MASK, 0,
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RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0),
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[TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17,
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RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
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[TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49,
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@ -1458,7 +1456,7 @@ static void rapl_detect_powerlimit(struct rapl_domain *rd)
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}
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}
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if (rapl_read_pl_data(rd, i, PL_ENABLE, false, &val64))
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if (rapl_read_pl_data(rd, i, PL_LIMIT, false, &val64))
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rd->rpl[i].name = NULL;
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}
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}
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