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dt-bindings: clock: mediatek: add support for MT7623
This patch adds bindings for apmixedsys, audsys, bpsys, ethsys, hifsys, imgsys, infracfg, mmsys, pericfg, topckgen and vdecsys for MT6723. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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@ -10,6 +10,7 @@ Required Properties:
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- "mediatek,mt2712-apmixedsys", "syscon"
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- "mediatek,mt6797-apmixedsys"
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- "mediatek,mt7622-apmixedsys"
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- "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
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- "mediatek,mt8135-apmixedsys"
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- "mediatek,mt8173-apmixedsys"
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- #clock-cells: Must be 1
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@ -8,6 +8,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-audsys", "syscon"
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- "mediatek,mt7622-audsys", "syscon"
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- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
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- #clock-cells: Must be 1
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The AUDSYS controller uses the common clk binding from
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@ -8,6 +8,7 @@ Required Properties:
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- compatible: Should be:
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- "mediatek,mt2701-bdpsys", "syscon"
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- "mediatek,mt2712-bdpsys", "syscon"
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- "mediatek,mt7623-bdpsys", "mediatek,mt2701-bdpsys", "syscon"
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- #clock-cells: Must be 1
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The bdpsys controller uses the common clk binding from
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@ -8,6 +8,7 @@ Required Properties:
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- compatible: Should be:
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- "mediatek,mt2701-ethsys", "syscon"
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- "mediatek,mt7622-ethsys", "syscon"
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- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
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- #clock-cells: Must be 1
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- #reset-cells: Must be 1
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@ -9,6 +9,7 @@ Required Properties:
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- compatible: Should be:
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- "mediatek,mt2701-hifsys", "syscon"
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- "mediatek,mt7622-hifsys", "syscon"
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- "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", "syscon"
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- #clock-cells: Must be 1
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The hifsys controller uses the common clk binding from
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@ -9,6 +9,7 @@ Required Properties:
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- "mediatek,mt2701-imgsys", "syscon"
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- "mediatek,mt2712-imgsys", "syscon"
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- "mediatek,mt6797-imgsys", "syscon"
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- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
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- "mediatek,mt8173-imgsys", "syscon"
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- #clock-cells: Must be 1
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@ -11,6 +11,7 @@ Required Properties:
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- "mediatek,mt2712-infracfg", "syscon"
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- "mediatek,mt6797-infracfg", "syscon"
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- "mediatek,mt7622-infracfg", "syscon"
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- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
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- "mediatek,mt8135-infracfg", "syscon"
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- "mediatek,mt8173-infracfg", "syscon"
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- #clock-cells: Must be 1
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@ -9,6 +9,7 @@ Required Properties:
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- "mediatek,mt2701-mmsys", "syscon"
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- "mediatek,mt2712-mmsys", "syscon"
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- "mediatek,mt6797-mmsys", "syscon"
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- "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
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- "mediatek,mt8173-mmsys", "syscon"
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- #clock-cells: Must be 1
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@ -10,6 +10,7 @@ Required Properties:
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- "mediatek,mt2701-pericfg", "syscon"
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- "mediatek,mt2712-pericfg", "syscon"
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- "mediatek,mt7622-pericfg", "syscon"
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- "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon"
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- "mediatek,mt8135-pericfg", "syscon"
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- "mediatek,mt8173-pericfg", "syscon"
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- #clock-cells: Must be 1
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@ -10,6 +10,7 @@ Required Properties:
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- "mediatek,mt2712-topckgen", "syscon"
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- "mediatek,mt6797-topckgen"
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- "mediatek,mt7622-topckgen"
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- "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
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- "mediatek,mt8135-topckgen"
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- "mediatek,mt8173-topckgen"
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- #clock-cells: Must be 1
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@ -9,6 +9,7 @@ Required Properties:
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- "mediatek,mt2701-vdecsys", "syscon"
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- "mediatek,mt2712-vdecsys", "syscon"
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- "mediatek,mt6797-vdecsys", "syscon"
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- "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
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- "mediatek,mt8173-vdecsys", "syscon"
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- #clock-cells: Must be 1
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