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clk: berlin: drop direct of_iomap of nodes reg property
The Berlin clock driver was sharing a DT node with the pin controller and the reset driver. All these devices are now sub-nodes of the chip controller. This patch rework the Berlin clock driver to allow moving the Berlin clock DT bindings into their own sub-node of the chip controller node. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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@ -508,10 +508,7 @@ static void __init berlin2_clock_setup(struct device_node *np)
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u8 avpll_flags = 0;
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int n;
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if (of_device_is_compatible(parent_np, "syscon"))
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np = parent_np;
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gbase = of_iomap(np, 0);
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gbase = of_iomap(parent_np, 0);
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if (!gbase)
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return;
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@ -689,9 +686,5 @@ static void __init berlin2_clock_setup(struct device_node *np)
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bg2_fail:
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iounmap(gbase);
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}
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CLK_OF_DECLARE(berlin2_clock, "marvell,berlin2-chip-ctrl",
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berlin2_clock_setup);
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CLK_OF_DECLARE(berlin2cd_clock, "marvell,berlin2cd-chip-ctrl",
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berlin2_clock_setup);
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CLK_OF_DECLARE(berlin2_clk, "marvell,berlin2-clk",
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berlin2_clock_setup);
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@ -295,17 +295,14 @@ static void __init berlin2q_clock_setup(struct device_node *np)
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struct clk *clk;
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int n;
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if (of_device_is_compatible(parent_np, "syscon"))
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np = parent_np;
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gbase = of_iomap(np, 0);
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gbase = of_iomap(parent_np, 0);
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if (!gbase) {
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pr_err("%s: Unable to map global base\n", np->full_name);
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return;
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}
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/* BG2Q CPU PLL is not part of global registers */
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cpupll_base = of_iomap(np, 1);
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cpupll_base = of_iomap(parent_np, 1);
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if (!cpupll_base) {
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pr_err("%s: Unable to map cpupll base\n", np->full_name);
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iounmap(gbase);
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@ -388,7 +385,5 @@ bg2q_fail:
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iounmap(cpupll_base);
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iounmap(gbase);
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}
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CLK_OF_DECLARE(berlin2q_clock, "marvell,berlin2q-chip-ctrl",
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berlin2q_clock_setup);
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CLK_OF_DECLARE(berlin2q_clk, "marvell,berlin2q-clk",
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berlin2q_clock_setup);
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