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gpio: omap: convert driver to use gpiolib irqchip
Converts the GPIO OMAP driver to register its chained irq handler and irqchip using the helpers in the gpiolib core. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Javier Martinez Canillas
Linus Walleij
parent
cd0a3748f3
commit
fb655f57ce
@ -247,6 +247,7 @@ config GPIO_OMAP
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bool "TI OMAP GPIO support"
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default y if ARCH_OMAP
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depends on ARM && ARCH_OMAP
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select GPIOLIB_IRQCHIP
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help
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Say yes here to enable GPIO support for TI OMAP SoCs.
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@ -24,7 +24,6 @@
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#include <linux/pm.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/gpio.h>
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#include <linux/platform_data/gpio-omap.h>
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@ -52,7 +51,6 @@ struct gpio_bank {
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struct list_head node;
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void __iomem *base;
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u16 irq;
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struct irq_domain *domain;
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u32 non_wakeup_gpios;
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u32 enabled_non_wakeup_gpios;
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struct gpio_regs context;
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@ -95,11 +93,10 @@ static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
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return bank->chip.base + gpio_irq;
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}
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static int omap_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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static inline struct gpio_bank *_irq_data_get_bank(struct irq_data *d)
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{
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struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
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return irq_find_mapping(bank->domain, offset);
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struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
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return container_of(chip, struct gpio_bank, chip);
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}
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static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
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@ -479,7 +476,7 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
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static int gpio_irq_type(struct irq_data *d, unsigned type)
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{
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struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
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struct gpio_bank *bank = _irq_data_get_bank(d);
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unsigned gpio = 0;
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int retval;
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unsigned long flags;
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@ -514,14 +511,6 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
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return -EINVAL;
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}
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retval = gpio_lock_as_irq(&bank->chip, offset);
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if (retval) {
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dev_err(bank->dev, "unable to lock offset %d for IRQ\n",
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offset);
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spin_unlock_irqrestore(&bank->lock, flags);
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return retval;
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}
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bank->irq_usage |= 1 << GPIO_INDEX(bank, gpio);
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spin_unlock_irqrestore(&bank->lock, flags);
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@ -664,7 +653,7 @@ static void _reset_gpio(struct gpio_bank *bank, int gpio)
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/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
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static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
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{
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struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
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struct gpio_bank *bank = _irq_data_get_bank(d);
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unsigned int gpio = irq_to_gpio(bank, d->hwirq);
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return _set_gpio_wakeup(bank, gpio, enable);
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@ -732,11 +721,12 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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unsigned int bit;
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struct gpio_bank *bank;
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int unmasked = 0;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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struct gpio_chip *chip = irq_get_handler_data(irq);
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chained_irq_enter(chip, desc);
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chained_irq_enter(irqchip, desc);
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bank = irq_get_handler_data(irq);
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bank = container_of(chip, struct gpio_bank, chip);
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isr_reg = bank->base + bank->regs->irqstatus;
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pm_runtime_get_sync(bank->dev);
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@ -764,7 +754,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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configured, we could unmask GPIO bank interrupt immediately */
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if (!level_mask && !unmasked) {
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unmasked = 1;
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chained_irq_exit(chip, desc);
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chained_irq_exit(irqchip, desc);
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}
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if (!isr)
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@ -784,7 +774,8 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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if (bank->toggle_mask & (1 << bit))
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_toggle_gpio_edge_triggering(bank, bit);
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generic_handle_irq(irq_find_mapping(bank->domain, bit));
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generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
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bit));
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}
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}
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/* if bank has any level sensitive GPIO pin interrupt
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@ -793,13 +784,13 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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interrupt */
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exit:
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if (!unmasked)
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chained_irq_exit(chip, desc);
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chained_irq_exit(irqchip, desc);
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pm_runtime_put(bank->dev);
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}
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static void gpio_irq_shutdown(struct irq_data *d)
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{
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struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
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struct gpio_bank *bank = _irq_data_get_bank(d);
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unsigned int gpio = irq_to_gpio(bank, d->hwirq);
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unsigned long flags;
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unsigned offset = GPIO_INDEX(bank, gpio);
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@ -821,7 +812,7 @@ static void gpio_irq_shutdown(struct irq_data *d)
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static void gpio_ack_irq(struct irq_data *d)
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{
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struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
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struct gpio_bank *bank = _irq_data_get_bank(d);
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unsigned int gpio = irq_to_gpio(bank, d->hwirq);
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_clear_gpio_irqstatus(bank, gpio);
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@ -829,7 +820,7 @@ static void gpio_ack_irq(struct irq_data *d)
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static void gpio_mask_irq(struct irq_data *d)
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{
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struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
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struct gpio_bank *bank = _irq_data_get_bank(d);
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unsigned int gpio = irq_to_gpio(bank, d->hwirq);
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unsigned long flags;
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@ -841,7 +832,7 @@ static void gpio_mask_irq(struct irq_data *d)
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static void gpio_unmask_irq(struct irq_data *d)
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{
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struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
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struct gpio_bank *bank = _irq_data_get_bank(d);
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unsigned int gpio = irq_to_gpio(bank, d->hwirq);
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unsigned int irq_mask = GPIO_BIT(bank, gpio);
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u32 trigger = irqd_get_trigger_type(d);
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@ -1085,6 +1076,7 @@ static int omap_gpio_chip_init(struct gpio_bank *bank)
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{
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int j;
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static int gpio;
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int irq_base = 0;
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int ret;
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/*
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@ -1098,7 +1090,6 @@ static int omap_gpio_chip_init(struct gpio_bank *bank)
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bank->chip.direction_output = gpio_output;
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bank->chip.set_debounce = gpio_debounce;
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bank->chip.set = gpio_set;
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bank->chip.to_irq = omap_gpio_to_irq;
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if (bank->is_mpuio) {
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bank->chip.label = "mpuio";
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if (bank->regs->wkup_en)
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@ -1113,24 +1104,46 @@ static int omap_gpio_chip_init(struct gpio_bank *bank)
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ret = gpiochip_add(&bank->chip);
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if (ret) {
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dev_err(bank->dev, "Could not register gpio chip\n", ret);
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dev_err(bank->dev, "Could not register gpio chip %d\n", ret);
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return ret;
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}
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#ifdef CONFIG_ARCH_OMAP1
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/*
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* REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
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* irq_alloc_descs() since a base IRQ offset will no longer be needed.
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*/
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irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
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if (irq_base < 0) {
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dev_err(bank->dev, "Couldn't allocate IRQ numbers\n");
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return -ENODEV;
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}
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#endif
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ret = gpiochip_irqchip_add(&bank->chip, &gpio_irq_chip,
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irq_base, gpio_irq_handler,
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IRQ_TYPE_NONE);
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if (ret) {
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dev_err(bank->dev, "Couldn't add irqchip to gpiochip %d\n", ret);
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ret = gpiochip_remove(&bank->chip);
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return -ENODEV;
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}
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gpiochip_set_chained_irqchip(&bank->chip, &gpio_irq_chip,
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bank->irq, gpio_irq_handler);
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for (j = 0; j < bank->width; j++) {
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int irq = irq_create_mapping(bank->domain, j);
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int irq = irq_find_mapping(bank->chip.irqdomain, j);
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irq_set_lockdep_class(irq, &gpio_lock_class);
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irq_set_chip_data(irq, bank);
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if (bank->is_mpuio) {
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omap_mpuio_alloc_gc(bank, irq, bank->width);
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} else {
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irq_set_chip_and_handler(irq, &gpio_irq_chip,
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handle_simple_irq);
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set_irq_flags(irq, IRQF_VALID);
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irq_set_chip_and_handler(irq, NULL, NULL);
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set_irq_flags(irq, 0);
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}
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}
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irq_set_chained_handler(bank->irq, gpio_irq_handler);
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irq_set_handler_data(bank->irq, bank);
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return 0;
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}
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static const struct of_device_id omap_gpio_match[];
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@ -1143,7 +1156,6 @@ static int omap_gpio_probe(struct platform_device *pdev)
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const struct omap_gpio_platform_data *pdata;
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struct resource *res;
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struct gpio_bank *bank;
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int irq_base = 0;
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int ret;
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match = of_match_device(of_match_ptr(omap_gpio_match), dev);
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@ -1166,6 +1178,7 @@ static int omap_gpio_probe(struct platform_device *pdev)
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bank->irq = res->start;
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bank->dev = dev;
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bank->chip.dev = dev;
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bank->dbck_flag = pdata->dbck_flag;
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bank->stride = pdata->bank_stride;
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bank->width = pdata->bank_width;
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@ -1186,24 +1199,6 @@ static int omap_gpio_probe(struct platform_device *pdev)
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pdata->get_context_loss_count;
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}
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#ifdef CONFIG_ARCH_OMAP1
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/*
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* REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
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* irq_alloc_descs() since a base IRQ offset will no longer be needed.
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*/
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irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
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if (irq_base < 0) {
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dev_err(dev, "Couldn't allocate IRQ numbers\n");
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return -ENODEV;
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}
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#endif
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bank->domain = irq_domain_add_simple(node, bank->width, irq_base,
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&irq_domain_simple_ops, NULL);
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if (!bank->domain) {
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dev_err(dev, "Couldn't register an IRQ domain\n");
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return -ENODEV;
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}
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if (bank->regs->set_dataout && bank->regs->clr_dataout)
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bank->set_dataout = _set_gpio_dataout_reg;
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else
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@ -1215,7 +1210,7 @@ static int omap_gpio_probe(struct platform_device *pdev)
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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bank->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(bank->base)) {
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irq_domain_remove(bank->domain);
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irq_domain_remove(bank->chip.irqdomain);
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return PTR_ERR(bank->base);
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}
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