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qed: Remove e4_ and _e4 from FW HSI

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The existing qed/qede/qedr/qedi/qedf code uses chip-specific naming in
structures,  functions, variables and defines in FW HSI (Hardware
Software Interface).

The new FW version introduced a generic naming convention in HSI
in-which the same code will be used across different versions
for simpler maintainability. It also eases in providing support for
new features.

With this patch every "_e4" or "e4_" prefix or suffix is not needed
anymore and it will be removed.

Reviewed-by: Manish Rangankar <mrangankar@marvell.com>
Reviewed-by: Javed Hasan <jhasan@marvell.com>
Signed-off-by: Ariel Elior <aelior@marvell.com>
Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com>
Signed-off-by: Shai Malin <smalin@marvell.com>
Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Shai Malin 2021-10-04 09:58:40 +03:00 committed by David S. Miller
parent 19198e4ec9
commit fb09a1ed5c
32 changed files with 3888 additions and 3896 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/infiniband/hw/qedr/main.c
View File

@ -272,7 +272,7 @@ static int qedr_register_device(struct qedr_dev *dev)
static int qedr_alloc_mem_sb(struct qedr_dev *dev,
struct qed_sb_info *sb_info, u16 sb_id)
{
struct status_block_e4 *sb_virt;
struct status_block *sb_virt;
dma_addr_t sb_phys;
int rc;

4
drivers/net/ethernet/qlogic/qed/qed.h
View File

@ -703,8 +703,6 @@ struct qed_dev {
#define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && CHIP_REV_IS_B0(dev))
#define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH)
#define QED_IS_K2(dev) QED_IS_AH(dev)
#define QED_IS_E4(dev) (QED_IS_BB(dev) || QED_IS_AH(dev))
#define QED_IS_E5(dev) ((dev)->type == QED_DEV_TYPE_E5)
u16 vendor_id;
@ -903,7 +901,7 @@ static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
}
#define PKT_LB_TC 9
#define MAX_NUM_VOQS_E4 20
#define MAX_NUM_VOQS 20
int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,

16
drivers/net/ethernet/qlogic/qed/qed_cxt.c
View File

@ -54,22 +54,22 @@
/* connection context union */
union conn_context {
struct e4_core_conn_context core_ctx;
struct e4_eth_conn_context eth_ctx;
struct e4_iscsi_conn_context iscsi_ctx;
struct e4_fcoe_conn_context fcoe_ctx;
struct e4_roce_conn_context roce_ctx;
struct core_conn_context core_ctx;
struct eth_conn_context eth_ctx;
struct iscsi_conn_context iscsi_ctx;
struct fcoe_conn_context fcoe_ctx;
struct roce_conn_context roce_ctx;
};
/* TYPE-0 task context - iSCSI, FCOE */
union type0_task_context {
struct e4_iscsi_task_context iscsi_ctx;
struct e4_fcoe_task_context fcoe_ctx;
struct iscsi_task_context iscsi_ctx;
struct fcoe_task_context fcoe_ctx;
};
/* TYPE-1 task context - ROCE */
union type1_task_context {
struct e4_rdma_task_context roce_ctx;
struct rdma_task_context roce_ctx;
};
struct src_ent {

8
drivers/net/ethernet/qlogic/qed/qed_debug.c
View File

@ -4744,9 +4744,9 @@ static u32 qed_ilt_dump(struct qed_hwfn *p_hwfn,
offset += qed_dump_section_hdr(dump_buf + offset,
dump, "num_pf_cids_per_conn_type", 1);
offset += qed_dump_num_param(dump_buf + offset,
dump, "size", NUM_OF_CONNECTION_TYPES_E4);
dump, "size", NUM_OF_CONNECTION_TYPES);
for (conn_type = 0, valid_conn_pf_cids = 0;
conn_type < NUM_OF_CONNECTION_TYPES_E4; conn_type++, offset++) {
conn_type < NUM_OF_CONNECTION_TYPES; conn_type++, offset++) {
u32 num_pf_cids =
p_hwfn->p_cxt_mngr->conn_cfg[conn_type].cid_count;
@ -4759,9 +4759,9 @@ static u32 qed_ilt_dump(struct qed_hwfn *p_hwfn,
offset += qed_dump_section_hdr(dump_buf + offset,
dump, "num_vf_cids_per_conn_type", 1);
offset += qed_dump_num_param(dump_buf + offset,
dump, "size", NUM_OF_CONNECTION_TYPES_E4);
dump, "size", NUM_OF_CONNECTION_TYPES);
for (conn_type = 0, valid_conn_vf_cids = 0;
conn_type < NUM_OF_CONNECTION_TYPES_E4; conn_type++, offset++) {
conn_type < NUM_OF_CONNECTION_TYPES; conn_type++, offset++) {
u32 num_vf_cids =
p_hwfn->p_cxt_mngr->conn_cfg[conn_type].cids_per_vf;

10
drivers/net/ethernet/qlogic/qed/qed_fcoe.c
View File

@ -89,7 +89,7 @@ qed_sp_fcoe_func_start(struct qed_hwfn *p_hwfn,
struct qed_fcoe_pf_params *fcoe_pf_params = NULL;
struct fcoe_init_ramrod_params *p_ramrod = NULL;
struct fcoe_init_func_ramrod_data *p_data;
struct e4_fcoe_conn_context *p_cxt = NULL;
struct fcoe_conn_context *p_cxt = NULL;
struct qed_spq_entry *p_ent = NULL;
struct qed_sp_init_data init_data;
struct qed_cxt_info cxt_info;
@ -144,7 +144,7 @@ qed_sp_fcoe_func_start(struct qed_hwfn *p_hwfn,
memset(p_cxt, 0, sizeof(*p_cxt));
SET_FIELD(p_cxt->tstorm_ag_context.flags3,
E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN, 1);
TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN, 1);
fcoe_pf_params->dummy_icid = (u16)dummy_cid;
@ -549,7 +549,7 @@ int qed_fcoe_alloc(struct qed_hwfn *p_hwfn)
void qed_fcoe_setup(struct qed_hwfn *p_hwfn)
{
struct e4_fcoe_task_context *p_task_ctx = NULL;
struct fcoe_task_context *p_task_ctx = NULL;
u32 i, lc;
int rc;
@ -561,7 +561,7 @@ void qed_fcoe_setup(struct qed_hwfn *p_hwfn)
if (rc)
continue;
memset(p_task_ctx, 0, sizeof(struct e4_fcoe_task_context));
memset(p_task_ctx, 0, sizeof(struct fcoe_task_context));
lc = 0;
SET_FIELD(lc, TIMERS_CONTEXT_VALIDLC0, 1);
@ -572,7 +572,7 @@ void qed_fcoe_setup(struct qed_hwfn *p_hwfn)
p_task_ctx->timer_context.logical_client_1 = cpu_to_le32(lc);
SET_FIELD(p_task_ctx->tstorm_ag_context.flags0,
E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE, 1);
TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE, 1);
}
}

6794
drivers/net/ethernet/qlogic/qed/qed_hsi.h
View File

File diff suppressed because it is too large Load Diff

29
drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c
View File

@ -17,13 +17,13 @@
#define CDU_VALIDATION_DEFAULT_CFG 61
static u16 con_region_offsets[3][NUM_OF_CONNECTION_TYPES_E4] = {
static u16 con_region_offsets[3][NUM_OF_CONNECTION_TYPES] = {
{400, 336, 352, 368, 304, 384, 416, 352}, /* region 3 offsets */
{528, 496, 416, 512, 448, 512, 544, 480}, /* region 4 offsets */
{608, 544, 496, 576, 576, 592, 624, 560} /* region 5 offsets */
};
static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES_E4] = {
static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES] = {
{240, 240, 112, 0, 0, 0, 0, 96} /* region 1 offsets */
};
@ -54,7 +54,7 @@ static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES_E4] = {
#define QM_WFQ_VP_PQ_VOQ_SHIFT 0
/* Bit of PF in WFQ VP PQ map */
#define QM_WFQ_VP_PQ_PF_E4_SHIFT 5
#define QM_WFQ_VP_PQ_PF_SHIFT 5
/* 0x9000 = 4*9*1024 */
#define QM_WFQ_INC_VAL(weight) ((weight) * 0x9000)
@ -156,20 +156,20 @@ static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES_E4] = {
cmd ## _ ## field, \
value)
#define QM_INIT_TX_PQ_MAP(p_hwfn, map, chip, pq_id, vp_pq_id, rl_valid, \
#define QM_INIT_TX_PQ_MAP(p_hwfn, map, pq_id, vp_pq_id, rl_valid, \
rl_id, ext_voq, wrr) \
do { \
u32 __reg = 0; \
\
BUILD_BUG_ON(sizeof((map).reg) != sizeof(__reg)); \
\
SET_FIELD(__reg, QM_RF_PQ_MAP_##chip##_PQ_VALID, 1); \
SET_FIELD(__reg, QM_RF_PQ_MAP_##chip##_RL_VALID, \
SET_FIELD(__reg, QM_RF_PQ_MAP_PQ_VALID, 1); \
SET_FIELD(__reg, QM_RF_PQ_MAP_RL_VALID, \
!!(rl_valid)); \
SET_FIELD(__reg, QM_RF_PQ_MAP_##chip##_VP_PQ_ID, (vp_pq_id)); \
SET_FIELD(__reg, QM_RF_PQ_MAP_##chip##_RL_ID, (rl_id)); \
SET_FIELD(__reg, QM_RF_PQ_MAP_##chip##_VOQ, (ext_voq)); \
SET_FIELD(__reg, QM_RF_PQ_MAP_##chip##_WRR_WEIGHT_GROUP, \
SET_FIELD(__reg, QM_RF_PQ_MAP_VP_PQ_ID, (vp_pq_id)); \
SET_FIELD(__reg, QM_RF_PQ_MAP_RL_ID, (rl_id)); \
SET_FIELD(__reg, QM_RF_PQ_MAP_VOQ, (ext_voq)); \
SET_FIELD(__reg, QM_RF_PQ_MAP_WRR_WEIGHT_GROUP, \
(wrr)); \
\
STORE_RT_REG((p_hwfn), QM_REG_TXPQMAP_RT_OFFSET + (pq_id), \
@ -204,7 +204,7 @@ static void qed_enable_pf_rl(struct qed_hwfn *p_hwfn, bool pf_rl_en)
{
STORE_RT_REG(p_hwfn, QM_REG_RLPFENABLE_RT_OFFSET, pf_rl_en ? 1 : 0);
if (pf_rl_en) {
u8 num_ext_voqs = MAX_NUM_VOQS_E4;
u8 num_ext_voqs = MAX_NUM_VOQS;
u64 voq_bit_mask = ((u64)1 << num_ext_voqs) - 1;
/* Enable RLs for all VOQs */
@ -298,7 +298,7 @@ static void qed_cmdq_lines_rt_init(
struct init_qm_port_params port_params[MAX_NUM_PORTS])
{
u8 tc, ext_voq, port_id, num_tcs_in_port;
u8 num_ext_voqs = MAX_NUM_VOQS_E4;
u8 num_ext_voqs = MAX_NUM_VOQS;
/* Clear PBF lines of all VOQs */
for (ext_voq = 0; ext_voq < num_ext_voqs; ext_voq++)
@ -487,7 +487,7 @@ static void qed_tx_pq_map_rt_init(struct qed_hwfn *p_hwfn,
/* Go over all Tx PQs */
for (i = 0, pq_id = p_params->start_pq; i < num_pqs; i++, pq_id++) {
u16 *p_first_tx_pq_id, vport_id_in_pf;
struct qm_rf_pq_map_e4 tx_pq_map;
struct qm_rf_pq_map tx_pq_map;
u8 tc_id = pq_params[i].tc_id;
bool is_vf_pq;
u8 ext_voq;
@ -505,7 +505,7 @@ static void qed_tx_pq_map_rt_init(struct qed_hwfn *p_hwfn,
if (*p_first_tx_pq_id == QM_INVALID_PQ_ID) {
u32 map_val =
(ext_voq << QM_WFQ_VP_PQ_VOQ_SHIFT) |
(p_params->pf_id << QM_WFQ_VP_PQ_PF_E4_SHIFT);
(p_params->pf_id << QM_WFQ_VP_PQ_PF_SHIFT);
/* Create new VP PQ */
*p_first_tx_pq_id = pq_id;
@ -520,7 +520,6 @@ static void qed_tx_pq_map_rt_init(struct qed_hwfn *p_hwfn,
/* Prepare PQ map entry */
QM_INIT_TX_PQ_MAP(p_hwfn,
tx_pq_map,
E4,
pq_id,
*p_first_tx_pq_id,
pq_params[i].rl_valid,

4
drivers/net/ethernet/qlogic/qed/qed_int.c
View File

@ -36,7 +36,7 @@ struct qed_sb_sp_info {
struct qed_sb_info sb_info;
/* per protocol index data */
struct qed_pi_info pi_info_arr[PIS_PER_SB_E4];
struct qed_pi_info pi_info_arr[PIS_PER_SB];
};
enum qed_attention_type {
@ -1507,7 +1507,7 @@ static void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
else
SET_FIELD(prod, CAU_PI_ENTRY_FSM_SEL, 1);
sb_offset = igu_sb_id * PIS_PER_SB_E4;
sb_offset = igu_sb_id * PIS_PER_SB;
pi_offset = sb_offset + pi_index;
if (p_hwfn->hw_init_done)

2
drivers/net/ethernet/qlogic/qed/qed_int.h
View File

@ -204,7 +204,7 @@ int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
#define QED_SB_EVENT_MASK 0x0003
#define SB_ALIGNED_SIZE(p_hwfn) \
ALIGNED_TYPE_SIZE(struct status_block_e4, p_hwfn)
ALIGNED_TYPE_SIZE(struct status_block, p_hwfn)
#define QED_SB_INVALID_IDX 0xffff

2
drivers/net/ethernet/qlogic/qed/qed_ll2.c
View File

@ -1533,7 +1533,7 @@ static inline u8 qed_ll2_handle_to_queue_id(struct qed_hwfn *p_hwfn,
int qed_ll2_establish_connection(void *cxt, u8 connection_handle)
{
struct e4_core_conn_context *p_cxt;
struct core_conn_context *p_cxt;
struct qed_ll2_tx_packet *p_pkt;
struct qed_ll2_info *p_ll2_conn;
struct qed_hwfn *p_hwfn = cxt;

4
drivers/net/ethernet/qlogic/qed/qed_mcp.c
View File

@ -3905,10 +3905,6 @@ int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK |
DRV_MB_PARAM_FEATURE_SUPPORT_PORT_FEC_CONTROL;
if (QED_IS_E5(p_hwfn->cdev))
features |=
DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EXT_SPEED_FEC_CONTROL;
return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
features, &mcp_resp, &mcp_param);
}

2
drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
View File

@ -1531,7 +1531,7 @@
0x1940000UL
#define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE \
0x000748UL
#define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE \
#define SEM_FAST_REG_DBG_MODSRC_DISABLE \
0x00074cUL
#define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE \
0x000750UL

8
drivers/net/ethernet/qlogic/qed/qed_spq.c
View File

@ -189,7 +189,7 @@ static int qed_spq_fill_entry(struct qed_hwfn *p_hwfn,
static void qed_spq_hw_initialize(struct qed_hwfn *p_hwfn,
struct qed_spq *p_spq)
{
struct e4_core_conn_context *p_cxt;
struct core_conn_context *p_cxt;
struct qed_cxt_info cxt_info;
u16 physical_q;
int rc;
@ -207,11 +207,11 @@ static void qed_spq_hw_initialize(struct qed_hwfn *p_hwfn,
p_cxt = cxt_info.p_cxt;
SET_FIELD(p_cxt->xstorm_ag_context.flags10,
E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN, 1);
XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN, 1);
SET_FIELD(p_cxt->xstorm_ag_context.flags1,
E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE, 1);
XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE, 1);
SET_FIELD(p_cxt->xstorm_ag_context.flags9,
E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN, 1);
XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN, 1);
/* QM physical queue */
physical_q = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB);

10
drivers/net/ethernet/qlogic/qed/qed_sriov.c
View File

@ -1603,7 +1603,7 @@ static void qed_iov_vf_mbx_acquire(struct qed_hwfn *p_hwfn,
/* fill in pfdev info */
pfdev_info->chip_num = p_hwfn->cdev->chip_num;
pfdev_info->db_size = 0;
pfdev_info->indices_per_sb = PIS_PER_SB_E4;
pfdev_info->indices_per_sb = PIS_PER_SB;
pfdev_info->capabilities = PFVF_ACQUIRE_CAP_DEFAULT_UNTAGGED |
PFVF_ACQUIRE_CAP_POST_FW_OVERRIDE;
@ -3581,11 +3581,11 @@ static int
qed_iov_vf_flr_poll_pbf(struct qed_hwfn *p_hwfn,
struct qed_vf_info *p_vf, struct qed_ptt *p_ptt)
{
u32 cons[MAX_NUM_VOQS_E4], distance[MAX_NUM_VOQS_E4];
u32 cons[MAX_NUM_VOQS], distance[MAX_NUM_VOQS];
int i, cnt;
/* Read initial consumers & producers */
for (i = 0; i < MAX_NUM_VOQS_E4; i++) {
for (i = 0; i < MAX_NUM_VOQS; i++) {
u32 prod;
cons[i] = qed_rd(p_hwfn, p_ptt,
@ -3600,7 +3600,7 @@ qed_iov_vf_flr_poll_pbf(struct qed_hwfn *p_hwfn,
/* Wait for consumers to pass the producers */
i = 0;
for (cnt = 0; cnt < 50; cnt++) {
for (; i < MAX_NUM_VOQS_E4; i++) {
for (; i < MAX_NUM_VOQS; i++) {
u32 tmp;
tmp = qed_rd(p_hwfn, p_ptt,
@ -3610,7 +3610,7 @@ qed_iov_vf_flr_poll_pbf(struct qed_hwfn *p_hwfn,
break;
}
if (i == MAX_NUM_VOQS_E4)
if (i == MAX_NUM_VOQS)
break;
msleep(20);

2
drivers/net/ethernet/qlogic/qede/qede_main.c
View File

@ -1395,7 +1395,7 @@ static void qede_free_mem_sb(struct qede_dev *edev, struct qed_sb_info *sb_info,
static int qede_alloc_mem_sb(struct qede_dev *edev,
struct qed_sb_info *sb_info, u16 sb_id)
{
struct status_block_e4 *sb_virt;
struct status_block *sb_virt;
dma_addr_t sb_phys;
int rc;

8
drivers/scsi/qedf/drv_fcoe_fw_funcs.c
View File

@ -22,9 +22,9 @@ int init_initiator_rw_fcoe_task(struct fcoe_task_params *task_params,
u32 task_retry_id,
u8 fcp_cmd_payload[32])
{
struct e4_fcoe_task_context *ctx = task_params->context;
struct fcoe_task_context *ctx = task_params->context;
const u8 val_byte = ctx->ystorm_ag_context.byte0;
struct e4_ustorm_fcoe_task_ag_ctx *u_ag_ctx;
struct ustorm_fcoe_task_ag_ctx *u_ag_ctx;
struct ystorm_fcoe_task_st_ctx *y_st_ctx;
struct tstorm_fcoe_task_st_ctx *t_st_ctx;
struct mstorm_fcoe_task_st_ctx *m_st_ctx;
@ -115,9 +115,9 @@ int init_initiator_midpath_unsolicited_fcoe_task(
struct scsi_sgl_task_params *rx_sgl_task_params,
u8 fw_to_place_fc_header)
{
struct e4_fcoe_task_context *ctx = task_params->context;
struct fcoe_task_context *ctx = task_params->context;
const u8 val_byte = ctx->ystorm_ag_context.byte0;
struct e4_ustorm_fcoe_task_ag_ctx *u_ag_ctx;
struct ustorm_fcoe_task_ag_ctx *u_ag_ctx;
struct ystorm_fcoe_task_st_ctx *y_st_ctx;
struct tstorm_fcoe_task_st_ctx *t_st_ctx;
struct mstorm_fcoe_task_st_ctx *m_st_ctx;

2
drivers/scsi/qedf/drv_fcoe_fw_funcs.h
View File

@ -10,7 +10,7 @@
struct fcoe_task_params {
/* Output parameter [set/filled by the HSI function] */
struct e4_fcoe_task_context *context;
struct fcoe_task_context *context;
/* Output parameter [set/filled by the HSI function] */
struct fcoe_wqe *sqe;

4
drivers/scsi/qedf/qedf.h
View File

@ -141,7 +141,7 @@ struct qedf_ioreq {
struct completion tm_done;
struct completion abts_done;
struct completion cleanup_done;
struct e4_fcoe_task_context *task;
struct fcoe_task_context *task;
struct fcoe_task_params *task_params;
struct scsi_sgl_task_params *sgl_task_params;
int idx;
@ -503,7 +503,7 @@ extern void qedf_cmd_timer_set(struct qedf_ctx *qedf, struct qedf_ioreq *io_req,
unsigned int timer_msec);
extern int qedf_init_mp_req(struct qedf_ioreq *io_req);
extern void qedf_init_mp_task(struct qedf_ioreq *io_req,
struct e4_fcoe_task_context *task_ctx, struct fcoe_wqe *sqe);
struct fcoe_task_context *task_ctx, struct fcoe_wqe *sqe);
extern u16 qedf_get_sqe_idx(struct qedf_rport *fcport);
extern void qedf_ring_doorbell(struct qedf_rport *fcport);
extern void qedf_process_els_compl(struct qedf_ctx *qedf, struct fcoe_cqe *cqe,

2
drivers/scsi/qedf/qedf_els.c
View File

@ -16,7 +16,7 @@ static int qedf_initiate_els(struct qedf_rport *fcport, unsigned int op,
struct qedf_ioreq *els_req;
struct qedf_mp_req *mp_req;
struct fc_frame_header *fc_hdr;
struct e4_fcoe_task_context *task;
struct fcoe_task_context *task;
int rc = 0;
uint32_t did, sid;
uint16_t xid;

12
drivers/scsi/qedf/qedf_io.c
View File

@ -584,7 +584,7 @@ static void qedf_build_fcp_cmnd(struct qedf_ioreq *io_req,
}
static void qedf_init_task(struct qedf_rport *fcport, struct fc_lport *lport,
struct qedf_ioreq *io_req, struct e4_fcoe_task_context *task_ctx,
struct qedf_ioreq *io_req, struct fcoe_task_context *task_ctx,
struct fcoe_wqe *sqe)
{
enum fcoe_task_type task_type;
@ -602,7 +602,7 @@ static void qedf_init_task(struct qedf_rport *fcport, struct fc_lport *lport,
/* Note init_initiator_rw_fcoe_task memsets the task context */
io_req->task = task_ctx;
memset(task_ctx, 0, sizeof(struct e4_fcoe_task_context));
memset(task_ctx, 0, sizeof(struct fcoe_task_context));
memset(io_req->task_params, 0, sizeof(struct fcoe_task_params));
memset(io_req->sgl_task_params, 0, sizeof(struct scsi_sgl_task_params));
@ -674,7 +674,7 @@ static void qedf_init_task(struct qedf_rport *fcport, struct fc_lport *lport,
}
void qedf_init_mp_task(struct qedf_ioreq *io_req,
struct e4_fcoe_task_context *task_ctx, struct fcoe_wqe *sqe)
struct fcoe_task_context *task_ctx, struct fcoe_wqe *sqe)
{
struct qedf_mp_req *mp_req = &(io_req->mp_req);
struct qedf_rport *fcport = io_req->fcport;
@ -692,7 +692,7 @@ void qedf_init_mp_task(struct qedf_ioreq *io_req,
memset(&tx_sgl_task_params, 0, sizeof(struct scsi_sgl_task_params));
memset(&rx_sgl_task_params, 0, sizeof(struct scsi_sgl_task_params));
memset(task_ctx, 0, sizeof(struct e4_fcoe_task_context));
memset(task_ctx, 0, sizeof(struct fcoe_task_context));
memset(&task_fc_hdr, 0, sizeof(struct fcoe_tx_mid_path_params));
/* Setup the task from io_req for easy reference */
@ -850,7 +850,7 @@ int qedf_post_io_req(struct qedf_rport *fcport, struct qedf_ioreq *io_req)
struct Scsi_Host *host = sc_cmd->device->host;
struct fc_lport *lport = shost_priv(host);
struct qedf_ctx *qedf = lport_priv(lport);
struct e4_fcoe_task_context *task_ctx;
struct fcoe_task_context *task_ctx;
u16 xid;
struct fcoe_wqe *sqe;
u16 sqe_idx;
@ -2293,7 +2293,7 @@ static int qedf_execute_tmf(struct qedf_rport *fcport, struct scsi_cmnd *sc_cmd,
uint8_t tm_flags)
{
struct qedf_ioreq *io_req;
struct e4_fcoe_task_context *task;
struct fcoe_task_context *task;
struct qedf_ctx *qedf = fcport->qedf;
struct fc_lport *lport = qedf->lport;
int rc = 0;

8
drivers/scsi/qedf/qedf_main.c
View File

@ -2170,7 +2170,7 @@ static bool qedf_fp_has_work(struct qedf_fastpath *fp)
struct qedf_ctx *qedf = fp->qedf;
struct global_queue *que;
struct qed_sb_info *sb_info = fp->sb_info;
struct status_block_e4 *sb = sb_info->sb_virt;
struct status_block *sb = sb_info->sb_virt;
u16 prod_idx;
/* Get the pointer to the global CQ this completion is on */
@ -2197,7 +2197,7 @@ static bool qedf_process_completions(struct qedf_fastpath *fp)
{
struct qedf_ctx *qedf = fp->qedf;
struct qed_sb_info *sb_info = fp->sb_info;
struct status_block_e4 *sb = sb_info->sb_virt;
struct status_block *sb = sb_info->sb_virt;
struct global_queue *que;
u16 prod_idx;
struct fcoe_cqe *cqe;
@ -2688,12 +2688,12 @@ void qedf_fp_io_handler(struct work_struct *work)
static int qedf_alloc_and_init_sb(struct qedf_ctx *qedf,
struct qed_sb_info *sb_info, u16 sb_id)
{
struct status_block_e4 *sb_virt;
struct status_block *sb_virt;
dma_addr_t sb_phys;
int ret;
sb_virt = dma_alloc_coherent(&qedf->pdev->dev,
sizeof(struct status_block_e4), &sb_phys, GFP_KERNEL);
sizeof(struct status_block), &sb_phys, GFP_KERNEL);
if (!sb_virt) {
QEDF_ERR(&qedf->dbg_ctx,

4
drivers/scsi/qedi/qedi_debugfs.c
View File

@ -136,7 +136,7 @@ qedi_gbl_ctx_show(struct seq_file *s, void *unused)
{
struct qedi_fastpath *fp = NULL;
struct qed_sb_info *sb_info = NULL;
struct status_block_e4 *sb = NULL;
struct status_block *sb = NULL;
struct global_queue *que = NULL;
int id;
u16 prod_idx;
@ -152,7 +152,7 @@ qedi_gbl_ctx_show(struct seq_file *s, void *unused)
sb_info = fp->sb_info;
sb = sb_info->sb_virt;
prod_idx = (sb->pi_array[QEDI_PROTO_CQ_PROD_IDX] &
STATUS_BLOCK_E4_PROD_INDEX_MASK);
STATUS_BLOCK_PROD_INDEX_MASK);
seq_printf(s, "SB PROD IDX: %d\n", prod_idx);
que = qedi->global_queues[fp->sb_id];
seq_printf(s, "DRV CONS IDX: %d\n", que->cq_cons_idx);

40
drivers/scsi/qedi/qedi_fw.c
View File

@ -85,7 +85,7 @@ static void qedi_process_text_resp(struct qedi_ctx *qedi,
{
struct iscsi_conn *conn = qedi_conn->cls_conn->dd_data;
struct iscsi_session *session = conn->session;
struct e4_iscsi_task_context *task_ctx;
struct iscsi_task_context *task_ctx;
struct iscsi_text_rsp *resp_hdr_ptr;
struct iscsi_text_response_hdr *cqe_text_response;
struct qedi_cmd *cmd;
@ -261,7 +261,7 @@ static void qedi_process_login_resp(struct qedi_ctx *qedi,
{
struct iscsi_conn *conn = qedi_conn->cls_conn->dd_data;
struct iscsi_session *session = conn->session;
struct e4_iscsi_task_context *task_ctx;
struct iscsi_task_context *task_ctx;
struct iscsi_login_rsp *resp_hdr_ptr;
struct iscsi_login_response_hdr *cqe_login_response;
struct qedi_cmd *cmd;
@ -970,7 +970,7 @@ int qedi_send_iscsi_login(struct qedi_conn *qedi_conn,
struct scsi_sgl_task_params tx_sgl_task_params;
struct scsi_sgl_task_params rx_sgl_task_params;
struct iscsi_task_params task_params;
struct e4_iscsi_task_context *fw_task_ctx;
struct iscsi_task_context *fw_task_ctx;
struct qedi_ctx *qedi = qedi_conn->qedi;
struct iscsi_login_req *login_hdr;
struct scsi_sge *resp_sge = NULL;
@ -990,9 +990,9 @@ int qedi_send_iscsi_login(struct qedi_conn *qedi_conn,
return -ENOMEM;
fw_task_ctx =
(struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
(struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
tid);
memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
qedi_cmd->task_id = tid;
@ -1073,7 +1073,7 @@ int qedi_send_iscsi_logout(struct qedi_conn *qedi_conn,
struct scsi_sgl_task_params tx_sgl_task_params;
struct scsi_sgl_task_params rx_sgl_task_params;
struct iscsi_task_params task_params;
struct e4_iscsi_task_context *fw_task_ctx;
struct iscsi_task_context *fw_task_ctx;
struct iscsi_logout *logout_hdr = NULL;
struct qedi_ctx *qedi = qedi_conn->qedi;
struct qedi_cmd *qedi_cmd;
@ -1091,9 +1091,9 @@ int qedi_send_iscsi_logout(struct qedi_conn *qedi_conn,
return -ENOMEM;
fw_task_ctx =
(struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
(struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
tid);
memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
qedi_cmd->task_id = tid;
@ -1434,7 +1434,7 @@ static int send_iscsi_tmf(struct qedi_conn *qedi_conn, struct iscsi_task *mtask,
struct iscsi_tmf_request_hdr tmf_pdu_header;
struct iscsi_task_params task_params;
struct qedi_ctx *qedi = qedi_conn->qedi;
struct e4_iscsi_task_context *fw_task_ctx;
struct iscsi_task_context *fw_task_ctx;
struct iscsi_tm *tmf_hdr;
struct qedi_cmd *qedi_cmd;
struct qedi_cmd *cmd;
@ -1454,9 +1454,9 @@ static int send_iscsi_tmf(struct qedi_conn *qedi_conn, struct iscsi_task *mtask,
return -ENOMEM;
fw_task_ctx =
(struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
(struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
tid);
memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
qedi_cmd->task_id = tid;
@ -1548,7 +1548,7 @@ int qedi_send_iscsi_text(struct qedi_conn *qedi_conn,
struct scsi_sgl_task_params tx_sgl_task_params;
struct scsi_sgl_task_params rx_sgl_task_params;
struct iscsi_task_params task_params;
struct e4_iscsi_task_context *fw_task_ctx;
struct iscsi_task_context *fw_task_ctx;
struct qedi_ctx *qedi = qedi_conn->qedi;
struct iscsi_text *text_hdr;
struct scsi_sge *req_sge = NULL;
@ -1570,9 +1570,9 @@ int qedi_send_iscsi_text(struct qedi_conn *qedi_conn,
return -ENOMEM;
fw_task_ctx =
(struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
(struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
tid);
memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
qedi_cmd->task_id = tid;
@ -1649,7 +1649,7 @@ int qedi_send_iscsi_nopout(struct qedi_conn *qedi_conn,
struct scsi_sgl_task_params rx_sgl_task_params;
struct iscsi_task_params task_params;
struct qedi_ctx *qedi = qedi_conn->qedi;
struct e4_iscsi_task_context *fw_task_ctx;
struct iscsi_task_context *fw_task_ctx;
struct iscsi_nopout *nopout_hdr;
struct scsi_sge *resp_sge = NULL;
struct qedi_cmd *qedi_cmd;
@ -1669,9 +1669,9 @@ int qedi_send_iscsi_nopout(struct qedi_conn *qedi_conn,
return -ENOMEM;
fw_task_ctx =
(struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
(struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
tid);
memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
qedi_cmd->task_id = tid;
@ -1991,7 +1991,7 @@ int qedi_iscsi_send_ioreq(struct iscsi_task *task)
struct iscsi_task_params task_params;
struct iscsi_conn_params conn_params;
struct scsi_initiator_cmd_params cmd_params;
struct e4_iscsi_task_context *fw_task_ctx;
struct iscsi_task_context *fw_task_ctx;
struct iscsi_cls_conn *cls_conn;
struct iscsi_scsi_req *hdr = (struct iscsi_scsi_req *)task->hdr;
enum iscsi_task_type task_type = MAX_ISCSI_TASK_TYPE;
@ -2014,9 +2014,9 @@ int qedi_iscsi_send_ioreq(struct iscsi_task *task)
return -ENOMEM;
fw_task_ctx =
(struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
(struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
tid);
memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
cmd->task_id = tid;

22
drivers/scsi/qedi/qedi_fw_api.c
View File

@ -202,7 +202,7 @@ static void init_default_iscsi_task(struct iscsi_task_params *task_params,
struct data_hdr *pdu_header,
enum iscsi_task_type task_type)
{
struct e4_iscsi_task_context *context;
struct iscsi_task_context *context;
u32 val;
u16 index;
u8 val_byte;
@ -224,7 +224,7 @@ static void init_default_iscsi_task(struct iscsi_task_params *task_params,
cpu_to_le16(task_params->conn_icid);
SET_FIELD(context->ustorm_ag_context.flags1,
E4_USTORM_ISCSI_TASK_AG_CTX_R2T2RECV, 1);
USTORM_ISCSI_TASK_AG_CTX_R2T2RECV, 1);
context->ustorm_st_context.task_type = task_type;
context->ustorm_st_context.cq_rss_number = task_params->cq_rss_number;
@ -254,7 +254,7 @@ void init_initiator_rw_cdb_ystorm_context(struct ystorm_iscsi_task_st_ctx *ystc,
static
void init_ustorm_task_contexts(struct ustorm_iscsi_task_st_ctx *ustorm_st_cxt,
struct e4_ustorm_iscsi_task_ag_ctx *ustorm_ag_cxt,
struct ustorm_iscsi_task_ag_ctx *ustorm_ag_cxt,
u32 remaining_recv_len, u32 expected_data_transfer_len,
u8 num_sges, bool tx_dif_conn_err_en)
{
@ -266,12 +266,12 @@ void init_ustorm_task_contexts(struct ustorm_iscsi_task_st_ctx *ustorm_st_cxt,
ustorm_st_cxt->exp_data_transfer_len = val;
SET_FIELD(ustorm_st_cxt->reg1.reg1_map, ISCSI_REG1_NUM_SGES, num_sges);
SET_FIELD(ustorm_ag_cxt->flags2,
E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN,
USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN,
tx_dif_conn_err_en ? 1 : 0);
}
static
void set_rw_exp_data_acked_and_cont_len(struct e4_iscsi_task_context *context,
void set_rw_exp_data_acked_and_cont_len(struct iscsi_task_context *context,
struct iscsi_conn_params *conn_params,
enum iscsi_task_type task_type,
u32 task_size,
@ -470,7 +470,7 @@ void init_rtdif_task_context(struct rdif_task_context *rdif_context,
}
}
static void set_local_completion_context(struct e4_iscsi_task_context *context)
static void set_local_completion_context(struct iscsi_task_context *context)
{
SET_FIELD(context->ystorm_st_context.state.flags,
YSTORM_ISCSI_TASK_STATE_LOCAL_COMP, 1);
@ -487,7 +487,7 @@ static int init_rw_iscsi_task(struct iscsi_task_params *task_params,
struct scsi_dif_task_params *dif_task_params)
{
u32 exp_data_transfer_len = conn_params->max_burst_length;
struct e4_iscsi_task_context *cxt;
struct iscsi_task_context *cxt;
bool slow_io = false;
u32 task_size, val;
u8 num_sges = 0;
@ -615,7 +615,7 @@ int init_initiator_login_request_task(struct iscsi_task_params *task_params,
struct scsi_sgl_task_params *tx_params,
struct scsi_sgl_task_params *rx_params)
{
struct e4_iscsi_task_context *cxt;
struct iscsi_task_context *cxt;
cxt = task_params->context;
@ -657,7 +657,7 @@ int init_initiator_nop_out_task(struct iscsi_task_params *task_params,
struct scsi_sgl_task_params *tx_sgl_task_params,
struct scsi_sgl_task_params *rx_sgl_task_params)
{
struct e4_iscsi_task_context *cxt;
struct iscsi_task_context *cxt;
cxt = task_params->context;
@ -703,7 +703,7 @@ int init_initiator_logout_request_task(struct iscsi_task_params *task_params,
struct scsi_sgl_task_params *tx_params,
struct scsi_sgl_task_params *rx_params)
{
struct e4_iscsi_task_context *cxt;
struct iscsi_task_context *cxt;
cxt = task_params->context;
@ -758,7 +758,7 @@ int init_initiator_text_request_task(struct iscsi_task_params *task_params,
struct scsi_sgl_task_params *tx_params,
struct scsi_sgl_task_params *rx_params)
{
struct e4_iscsi_task_context *cxt;
struct iscsi_task_context *cxt;
cxt = task_params->context;

2
drivers/scsi/qedi/qedi_fw_iscsi.h
View File

@ -10,7 +10,7 @@
#include "qedi_fw_scsi.h"
struct iscsi_task_params {
struct e4_iscsi_task_context *context;
struct iscsi_task_context *context;
struct iscsi_wqe *sqe;
u32 tx_io_size;
u32 rx_io_size;

2
drivers/scsi/qedi/qedi_iscsi.h
View File

@ -182,7 +182,7 @@ struct qedi_cmd {
struct scsi_cmnd *scsi_cmd;
struct scatterlist *sg;
struct qedi_io_bdt io_tbl;
struct e4_iscsi_task_context request;
struct iscsi_task_context request;
unsigned char *sense_buffer;
dma_addr_t sense_buffer_dma;
u16 task_id;

8
drivers/scsi/qedi/qedi_main.c
View File

@ -351,12 +351,12 @@ static int qedi_init_uio(struct qedi_ctx *qedi)
static int qedi_alloc_and_init_sb(struct qedi_ctx *qedi,
struct qed_sb_info *sb_info, u16 sb_id)
{
struct status_block_e4 *sb_virt;
struct status_block *sb_virt;
dma_addr_t sb_phys;
int ret;
sb_virt = dma_alloc_coherent(&qedi->pdev->dev,
sizeof(struct status_block_e4), &sb_phys,
sizeof(struct status_block), &sb_phys,
GFP_KERNEL);
if (!sb_virt) {
QEDI_ERR(&qedi->dbg_ctx,
@ -1259,7 +1259,7 @@ static bool qedi_process_completions(struct qedi_fastpath *fp)
{
struct qedi_ctx *qedi = fp->qedi;
struct qed_sb_info *sb_info = fp->sb_info;
struct status_block_e4 *sb = sb_info->sb_virt;
struct status_block *sb = sb_info->sb_virt;
struct qedi_percpu_s *p = NULL;
struct global_queue *que;
u16 prod_idx;
@ -1315,7 +1315,7 @@ static bool qedi_fp_has_work(struct qedi_fastpath *fp)
struct qedi_ctx *qedi = fp->qedi;
struct global_queue *que;
struct qed_sb_info *sb_info = fp->sb_info;
struct status_block_e4 *sb = sb_info->sb_virt;
struct status_block *sb = sb_info->sb_virt;
u16 prod_idx;
barrier();

28
include/linux/qed/common_hsi.h
View File

@ -133,7 +133,7 @@
#define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1)
/* CIDs */
#define NUM_OF_CONNECTION_TYPES_E4 (8)
#define NUM_OF_CONNECTION_TYPES (8)
#define NUM_OF_LCIDS (320)
#define NUM_OF_LTIDS (320)
@ -379,7 +379,7 @@
#define CAU_FSM_ETH_TX 1
/* Number of Protocol Indices per Status Block */
#define PIS_PER_SB_E4 12
#define PIS_PER_SB 12
#define MAX_PIS_PER_SB PIS_PER_SB
#define CAU_HC_STOPPED_STATE 3
@ -1221,20 +1221,20 @@ struct rdif_task_context {
};
/* Status block structure */
struct status_block_e4 {
__le16 pi_array[PIS_PER_SB_E4];
struct status_block {
__le16 pi_array[PIS_PER_SB];
__le32 sb_num;
#define STATUS_BLOCK_E4_SB_NUM_MASK 0x1FF
#define STATUS_BLOCK_E4_SB_NUM_SHIFT 0
#define STATUS_BLOCK_E4_ZERO_PAD_MASK 0x7F
#define STATUS_BLOCK_E4_ZERO_PAD_SHIFT 9
#define STATUS_BLOCK_E4_ZERO_PAD2_MASK 0xFFFF
#define STATUS_BLOCK_E4_ZERO_PAD2_SHIFT 16
#define STATUS_BLOCK_SB_NUM_MASK 0x1FF
#define STATUS_BLOCK_SB_NUM_SHIFT 0
#define STATUS_BLOCK_ZERO_PAD_MASK 0x7F
#define STATUS_BLOCK_ZERO_PAD_SHIFT 9
#define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF
#define STATUS_BLOCK_ZERO_PAD2_SHIFT 16
__le32 prod_index;
#define STATUS_BLOCK_E4_PROD_INDEX_MASK 0xFFFFFF
#define STATUS_BLOCK_E4_PROD_INDEX_SHIFT 0
#define STATUS_BLOCK_E4_ZERO_PAD3_MASK 0xFF
#define STATUS_BLOCK_E4_ZERO_PAD3_SHIFT 24
#define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF
#define STATUS_BLOCK_PROD_INDEX_SHIFT 0
#define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF
#define STATUS_BLOCK_ZERO_PAD3_SHIFT 24
};
/* Tdif context */

362
include/linux/qed/fcoe_common.h
View File

@ -150,49 +150,49 @@ struct ystorm_fcoe_task_st_ctx {
u8 reserved2[8];
};
struct e4_ystorm_fcoe_task_ag_ctx {
struct ystorm_fcoe_task_ag_ctx {
u8 byte0;
u8 byte1;
__le16 word0;
u8 flags0;
#define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF
#define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0
#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4
#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF
#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0
#define YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4
#define YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
#define YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
#define YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
#define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
#define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0
#define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
#define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
#define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
#define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
#define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6
#define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
#define YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
#define YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0
#define YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
#define YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6
#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
u8 flags2;
#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
#define YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0
#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6
#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
u8 byte2;
__le32 reg0;
u8 byte3;
@ -206,73 +206,73 @@ struct e4_ystorm_fcoe_task_ag_ctx {
__le32 reg2;
};
struct e4_tstorm_fcoe_task_ag_ctx {
struct tstorm_fcoe_task_ag_ctx {
u8 reserved;
u8 byte1;
__le16 icid;
u8 flags0;
#define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
#define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6
#define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7
#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6
#define TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7
u8 flags1;
#define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0
#define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1
#define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3
#define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2
#define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3
#define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4
#define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
#define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6
#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0
#define TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1
#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2
#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4
#define TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6
u8 flags2;
#define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3
#define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0
#define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
#define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2
#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3
#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4
#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3
#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6
#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0
#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6
u8 flags3;
#define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3
#define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0
#define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2
#define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3
#define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4
#define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5
#define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7
#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0
#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2
#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3
#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4
#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5
#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7
u8 flags4;
#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0
#define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0
#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1
#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2
#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3
#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4
#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5
#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6
#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7
u8 cleanup_state;
__le16 last_sent_tid;
__le32 rec_rr_tov_exp_timeout;
@ -352,49 +352,49 @@ struct tstorm_fcoe_task_st_ctx {
struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only;
};
struct e4_mstorm_fcoe_task_ag_ctx {
struct mstorm_fcoe_task_ag_ctx {
u8 byte0;
u8 byte1;
__le16 icid;
u8 flags0;
#define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5
#define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
#define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5
#define MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
#define MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
#define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
#define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0
#define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
#define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
#define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
#define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4
#define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
#define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0
#define MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
#define MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
#define MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
#define MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4
#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
u8 flags2;
#define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
#define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0
#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6
#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
u8 cleanup_state;
__le32 received_bytes;
u8 byte3;
@ -440,56 +440,56 @@ struct mstorm_fcoe_task_st_ctx {
struct scsi_cached_sges data_desc;
};
struct e4_ustorm_fcoe_task_ag_ctx {
struct ustorm_fcoe_task_ag_ctx {
u8 reserved;
u8 byte1;
__le16 icid;
u8 flags0;
#define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
#define E4_USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
#define E4_USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6
#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
#define USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
#define USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6
u8 flags1;
#define E4_USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
#define E4_USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0
#define E4_USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
#define E4_USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2
#define E4_USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3
#define E4_USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4
#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
#define USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
#define USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0
#define USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
#define USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2
#define USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3
#define USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4
#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
u8 flags2;
#define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0
#define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1
#define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2
#define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3
#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7
#define USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0
#define USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1
#define USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2
#define USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3
#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5
#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6
#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7
u8 flags3;
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3
#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0
#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1
#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2
#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3
#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
__le32 dif_err_intervals;
__le32 dif_error_1st_interval;
__le32 global_cq_num;
@ -499,18 +499,18 @@ struct e4_ustorm_fcoe_task_ag_ctx {
};
/* FCoE task context */
struct e4_fcoe_task_context {
struct fcoe_task_context {
struct ystorm_fcoe_task_st_ctx ystorm_st_context;
struct regpair ystorm_st_padding[2];
struct tdif_task_context tdif_context;
struct e4_ystorm_fcoe_task_ag_ctx ystorm_ag_context;
struct e4_tstorm_fcoe_task_ag_ctx tstorm_ag_context;
struct ystorm_fcoe_task_ag_ctx ystorm_ag_context;
struct tstorm_fcoe_task_ag_ctx tstorm_ag_context;
struct timers_context timer_context;
struct tstorm_fcoe_task_st_ctx tstorm_st_context;
struct regpair tstorm_st_padding[2];
struct e4_mstorm_fcoe_task_ag_ctx mstorm_ag_context;
struct mstorm_fcoe_task_ag_ctx mstorm_ag_context;
struct mstorm_fcoe_task_st_ctx mstorm_st_context;
struct e4_ustorm_fcoe_task_ag_ctx ustorm_ag_context;
struct ustorm_fcoe_task_ag_ctx ustorm_ag_context;
struct rdif_task_context rdif_context;
};

360
include/linux/qed/iscsi_common.h
View File

@ -714,49 +714,49 @@ struct ystorm_iscsi_task_st_ctx {
union iscsi_task_hdr pdu_hdr;
};
struct e4_ystorm_iscsi_task_ag_ctx {
struct ystorm_iscsi_task_ag_ctx {
u8 reserved;
u8 byte1;
__le16 word0;
u8 flags0;
#define E4_YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
#define E4_YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
#define E4_YSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
#define E4_YSTORM_ISCSI_TASK_AG_CTX_TTT_VALID_MASK 0x1 /* bit3 */
#define E4_YSTORM_ISCSI_TASK_AG_CTX_TTT_VALID_SHIFT 7
#define YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
#define YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
#define YSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
#define YSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
#define YSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
#define YSTORM_ISCSI_TASK_AG_CTX_TTT_VALID_MASK 0x1 /* bit3 */
#define YSTORM_ISCSI_TASK_AG_CTX_TTT_VALID_SHIFT 7
u8 flags1;
#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 0
#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 6
#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
#define YSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
#define YSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 0
#define YSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
#define YSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
#define YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
#define YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
#define YSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 6
#define YSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
u8 flags2;
#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
#define YSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
#define YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
#define YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
#define YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
#define YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
#define YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
#define YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
u8 byte2;
__le32 TTT;
u8 byte3;
@ -764,49 +764,49 @@ struct e4_ystorm_iscsi_task_ag_ctx {
__le16 word1;
};
struct e4_mstorm_iscsi_task_ag_ctx {
struct mstorm_iscsi_task_ag_ctx {
u8 cdu_validation;
u8 byte1;
__le16 task_cid;
u8 flags0;
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define E4_MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_SHIFT 5
#define E4_MSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_SHIFT 7
#define MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define MSTORM_ISCSI_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_SHIFT 5
#define MSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_SHIFT 7
u8 flags1;
#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_MASK 0x3
#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_SHIFT 0
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 4
#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_SHIFT 6
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_MASK 0x3
#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_SHIFT 0
#define MSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
#define MSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
#define MSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
#define MSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 4
#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_SHIFT 6
#define MSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
u8 flags2;
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 0
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
#define MSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 0
#define MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
#define MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
#define MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
#define MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
#define MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
#define MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
u8 byte2;
__le32 reg0;
u8 byte3;
@ -814,56 +814,56 @@ struct e4_mstorm_iscsi_task_ag_ctx {
__le16 word1;
};
struct e4_ustorm_iscsi_task_ag_ctx {
struct ustorm_iscsi_task_ag_ctx {
u8 reserved;
u8 state;
__le16 icid;
u8 flags0;
#define E4_USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define E4_USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define E4_USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define E4_USTORM_ISCSI_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_SHIFT 5
#define E4_USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_MASK 0x3
#define E4_USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_SHIFT 6
#define USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define USTORM_ISCSI_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_SHIFT 5
#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_MASK 0x3
#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_SHIFT 6
u8 flags1;
#define E4_USTORM_ISCSI_TASK_AG_CTX_RESERVED1_MASK 0x3
#define E4_USTORM_ISCSI_TASK_AG_CTX_RESERVED1_SHIFT 0
#define E4_USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_MASK 0x3
#define E4_USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_SHIFT 2
#define E4_USTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
#define E4_USTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 4
#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
#define USTORM_ISCSI_TASK_AG_CTX_RESERVED1_MASK 0x3
#define USTORM_ISCSI_TASK_AG_CTX_RESERVED1_SHIFT 0
#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_MASK 0x3
#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_SHIFT 2
#define USTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
#define USTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 4
#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
u8 flags2;
#define E4_USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_SHIFT 0
#define E4_USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_SHIFT 1
#define E4_USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_SHIFT 2
#define E4_USTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 3
#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
#define E4_USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_SHIFT 5
#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 6
#define E4_USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_SHIFT 7
#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_SHIFT 0
#define USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_SHIFT 1
#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_SHIFT 2
#define USTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 3
#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
#define USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_SHIFT 5
#define USTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 6
#define USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_SHIFT 7
u8 flags3;
#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 0
#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 1
#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 2
#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 3
#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
#define USTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 0
#define USTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 1
#define USTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 2
#define USTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 3
#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
__le32 dif_err_intervals;
__le32 dif_error_1st_interval;
__le32 rcv_cont_len;
@ -952,14 +952,14 @@ struct ustorm_iscsi_task_st_ctx {
};
/* iscsi task context */
struct e4_iscsi_task_context {
struct iscsi_task_context {
struct ystorm_iscsi_task_st_ctx ystorm_st_context;
struct e4_ystorm_iscsi_task_ag_ctx ystorm_ag_context;
struct ystorm_iscsi_task_ag_ctx ystorm_ag_context;
struct regpair ystorm_ag_padding[2];
struct tdif_task_context tdif_context;
struct e4_mstorm_iscsi_task_ag_ctx mstorm_ag_context;
struct mstorm_iscsi_task_ag_ctx mstorm_ag_context;
struct regpair mstorm_ag_padding[2];
struct e4_ustorm_iscsi_task_ag_ctx ustorm_ag_context;
struct ustorm_iscsi_task_ag_ctx ustorm_ag_context;
struct mstorm_iscsi_task_st_ctx mstorm_st_context;
struct ustorm_iscsi_task_st_ctx ustorm_st_context;
struct rdif_task_context rdif_context;
@ -1431,73 +1431,73 @@ struct ystorm_iscsi_stats_drv {
struct regpair iscsi_tx_tcp_pkt_cnt;
};
struct e4_tstorm_iscsi_task_ag_ctx {
struct tstorm_iscsi_task_ag_ctx {
u8 byte0;
u8 byte1;
__le16 word0;
u8 flags0;
#define E4_TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
#define E4_TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT2_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT2_SHIFT 6
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7
#define TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
#define TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
#define TSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
#define TSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
#define TSTORM_ISCSI_TASK_AG_CTX_BIT2_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_BIT2_SHIFT 6
#define TSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT5_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT5_SHIFT 1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 2
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 4
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 6
#define TSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
#define TSTORM_ISCSI_TASK_AG_CTX_BIT5_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_BIT5_SHIFT 1
#define TSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 2
#define TSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 4
#define TSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 6
u8 flags2;
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 0
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF4_MASK 0x3
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF4_SHIFT 2
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF5_MASK 0x3
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF5_SHIFT 4
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF6_MASK 0x3
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF6_SHIFT 6
#define TSTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 0
#define TSTORM_ISCSI_TASK_AG_CTX_CF4_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF4_SHIFT 2
#define TSTORM_ISCSI_TASK_AG_CTX_CF5_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF5_SHIFT 4
#define TSTORM_ISCSI_TASK_AG_CTX_CF6_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF6_SHIFT 6
u8 flags3;
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF7_MASK 0x3
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF7_SHIFT 0
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 2
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 3
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 4
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 5
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF4EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF4EN_SHIFT 6
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF5EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF5EN_SHIFT 7
#define TSTORM_ISCSI_TASK_AG_CTX_CF7_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF7_SHIFT 0
#define TSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 2
#define TSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 3
#define TSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 4
#define TSTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 5
#define TSTORM_ISCSI_TASK_AG_CTX_CF4EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF4EN_SHIFT 6
#define TSTORM_ISCSI_TASK_AG_CTX_CF5EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF5EN_SHIFT 7
u8 flags4;
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF6EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF6EN_SHIFT 0
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF7EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF7EN_SHIFT 1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 2
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 3
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 4
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 5
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 6
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 7
#define TSTORM_ISCSI_TASK_AG_CTX_CF6EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF6EN_SHIFT 0
#define TSTORM_ISCSI_TASK_AG_CTX_CF7EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF7EN_SHIFT 1
#define TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 2
#define TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 3
#define TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 4
#define TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 5
#define TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 6
#define TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 7
u8 byte2;
__le16 word1;
__le32 reg0;

18
include/linux/qed/nvmetcp_common.h
View File

@ -410,7 +410,7 @@ struct e5_ystorm_nvmetcp_task_ag_ctx {
u8 byte2;
u8 byte3;
u8 byte4;
u8 e4_reserved7;
u8 reserved7;
};
struct e5_mstorm_nvmetcp_task_ag_ctx {
@ -445,7 +445,7 @@ struct e5_mstorm_nvmetcp_task_ag_ctx {
u8 byte2;
u8 byte3;
u8 byte4;
u8 e4_reserved7;
u8 reserved7;
};
struct e5_ustorm_nvmetcp_task_ag_ctx {
@ -489,17 +489,17 @@ struct e5_ustorm_nvmetcp_task_ag_ctx {
#define E5_USTORM_NVMETCP_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_SHIFT 7
u8 flags3;
u8 flags4;
#define E5_USTORM_NVMETCP_TASK_AG_CTX_E4_RESERVED5_MASK 0x3
#define E5_USTORM_NVMETCP_TASK_AG_CTX_E4_RESERVED5_SHIFT 0
#define E5_USTORM_NVMETCP_TASK_AG_CTX_E4_RESERVED6_MASK 0x1
#define E5_USTORM_NVMETCP_TASK_AG_CTX_E4_RESERVED6_SHIFT 2
#define E5_USTORM_NVMETCP_TASK_AG_CTX_E4_RESERVED7_MASK 0x1
#define E5_USTORM_NVMETCP_TASK_AG_CTX_E4_RESERVED7_SHIFT 3
#define E5_USTORM_NVMETCP_TASK_AG_CTX_RESERVED5_MASK 0x3
#define E5_USTORM_NVMETCP_TASK_AG_CTX_RESERVED5_SHIFT 0
#define E5_USTORM_NVMETCP_TASK_AG_CTX_RESERVED6_MASK 0x1
#define E5_USTORM_NVMETCP_TASK_AG_CTX_RESERVED6_SHIFT 2
#define E5_USTORM_NVMETCP_TASK_AG_CTX_RESERVED7_MASK 0x1
#define E5_USTORM_NVMETCP_TASK_AG_CTX_RESERVED7_SHIFT 3
#define E5_USTORM_NVMETCP_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
#define E5_USTORM_NVMETCP_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
u8 byte2;
u8 byte3;
u8 e4_reserved8;
u8 reserved8;
__le32 dif_err_intervals;
__le32 dif_error_1st_interval;
__le32 rcv_cont_len;

5
include/linux/qed/qed_if.h
View File

@ -588,7 +588,7 @@ enum qed_int_mode {
};
struct qed_sb_info {
struct status_block_e4 *sb_virt;
struct status_block *sb_virt;
dma_addr_t sb_phys;
u32 sb_ack; /* Last given ack */
u16 igu_sb_id;
@ -613,7 +613,6 @@ enum qed_hw_err_type {
enum qed_dev_type {
QED_DEV_TYPE_BB,
QED_DEV_TYPE_AH,
QED_DEV_TYPE_E5,
};
struct qed_dev_info {
@ -1411,7 +1410,7 @@ static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
u16 rc = 0;
prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
STATUS_BLOCK_E4_PROD_INDEX_MASK;
STATUS_BLOCK_PROD_INDEX_MASK;
if (sb_info->sb_ack != prod) {
sb_info->sb_ack = prod;
rc |= QED_SB_IDX;