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Check whether the TLB operations need broadcasting on SMP systems
ARMv7 SMP hardware can handle the TLB maintenance operations broadcasting in hardware so that the software can avoid the costly IPIs. This patch adds the necessary checks (the MMFR3 CPUID register) to avoid the broadcasting if already supported by the hardware. (this patch is based on the work done by Tony Thompson @ ARM) Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Catalin Marinas
parent
da055eb52e
commit
faa7bc51c1
@ -8,6 +8,21 @@
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#define CPUID_TCM 2
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#define CPUID_TLBTYPE 3
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#define CPUID_EXT_PFR0 "c1, 0"
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#define CPUID_EXT_PFR1 "c1, 1"
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#define CPUID_EXT_DFR0 "c1, 2"
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#define CPUID_EXT_AFR0 "c1, 3"
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#define CPUID_EXT_MMFR0 "c1, 4"
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#define CPUID_EXT_MMFR1 "c1, 5"
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#define CPUID_EXT_MMFR2 "c1, 6"
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#define CPUID_EXT_MMFR3 "c1, 7"
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#define CPUID_EXT_ISAR0 "c2, 0"
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#define CPUID_EXT_ISAR1 "c2, 1"
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#define CPUID_EXT_ISAR2 "c2, 2"
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#define CPUID_EXT_ISAR3 "c2, 3"
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#define CPUID_EXT_ISAR4 "c2, 4"
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#define CPUID_EXT_ISAR5 "c2, 5"
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#ifdef CONFIG_CPU_CP15
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#define read_cpuid(reg) \
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({ \
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@ -18,9 +33,19 @@
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: "cc"); \
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__val; \
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})
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#define read_cpuid_ext(ext_reg) \
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({ \
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unsigned int __val; \
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asm("mrc p15, 0, %0, c0, " ext_reg \
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: "=r" (__val) \
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: \
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: "cc"); \
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__val; \
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})
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#else
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extern unsigned int processor_id;
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#define read_cpuid(reg) (processor_id)
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#define read_cpuid_ext(reg) 0
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#endif
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/*
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@ -40,6 +40,12 @@
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#define TLB_V6_I_ASID (1 << 18)
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#define TLB_BTB (1 << 28)
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/* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */
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#define TLB_V7_UIS_PAGE (1 << 19)
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#define TLB_V7_UIS_FULL (1 << 20)
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#define TLB_V7_UIS_ASID (1 << 21)
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#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */
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#define TLB_DCLEAN (1 << 30)
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#define TLB_WB (1 << 31)
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@ -176,9 +182,17 @@
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# define v6wbi_always_flags (-1UL)
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#endif
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#ifdef CONFIG_SMP
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#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
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TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
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#else
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#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
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TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
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#endif
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#ifdef CONFIG_CPU_TLB_V7
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# define v7wbi_possible_flags v6wbi_tlb_flags
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# define v7wbi_always_flags v6wbi_tlb_flags
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# define v7wbi_possible_flags v7wbi_tlb_flags
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# define v7wbi_always_flags v7wbi_tlb_flags
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# ifdef _TLB
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# define MULTI_TLB 1
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# else
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@ -316,6 +330,8 @@ static inline void local_flush_tlb_all(void)
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asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
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asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_V7_UIS_FULL))
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asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_BTB)) {
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/* flush the branch target cache */
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@ -351,6 +367,8 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
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asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
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if (tlb_flag(TLB_V6_I_ASID))
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asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
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if (tlb_flag(TLB_V7_UIS_ASID))
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asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc");
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if (tlb_flag(TLB_BTB)) {
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/* flush the branch target cache */
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@ -389,6 +407,8 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
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asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
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if (tlb_flag(TLB_V6_I_PAGE))
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asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
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if (tlb_flag(TLB_V7_UIS_PAGE))
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asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc");
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if (tlb_flag(TLB_BTB)) {
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/* flush the branch target cache */
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@ -424,6 +444,8 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
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asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
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if (tlb_flag(TLB_V6_I_PAGE))
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asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
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if (tlb_flag(TLB_V7_UIS_PAGE))
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asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (kaddr) : "cc");
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if (tlb_flag(TLB_BTB)) {
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/* flush the branch target cache */
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@ -32,6 +32,7 @@
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#include <asm/processor.h>
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#include <asm/tlbflush.h>
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#include <asm/ptrace.h>
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#include <asm/cputype.h>
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/*
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* as from 2.5, kernels no longer have an init_tasks structure
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@ -545,6 +546,12 @@ struct tlb_args {
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unsigned long ta_end;
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};
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/* all SMP configurations have the extended CPUID registers */
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static inline int tlb_ops_need_broadcast(void)
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{
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return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
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}
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static inline void ipi_flush_tlb_all(void *ignored)
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{
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local_flush_tlb_all();
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@ -587,51 +594,61 @@ static inline void ipi_flush_tlb_kernel_range(void *arg)
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void flush_tlb_all(void)
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{
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on_each_cpu(ipi_flush_tlb_all, NULL, 1);
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if (tlb_ops_need_broadcast())
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on_each_cpu(ipi_flush_tlb_all, NULL, 1);
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else
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local_flush_tlb_all();
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}
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void flush_tlb_mm(struct mm_struct *mm)
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{
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on_each_cpu_mask(ipi_flush_tlb_mm, mm, 1, &mm->cpu_vm_mask);
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if (tlb_ops_need_broadcast())
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on_each_cpu_mask(ipi_flush_tlb_mm, mm, 1, &mm->cpu_vm_mask);
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else
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local_flush_tlb_mm(mm);
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}
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void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
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{
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struct tlb_args ta;
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ta.ta_vma = vma;
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ta.ta_start = uaddr;
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on_each_cpu_mask(ipi_flush_tlb_page, &ta, 1, &vma->vm_mm->cpu_vm_mask);
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if (tlb_ops_need_broadcast()) {
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struct tlb_args ta;
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ta.ta_vma = vma;
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ta.ta_start = uaddr;
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on_each_cpu_mask(ipi_flush_tlb_page, &ta, 1, &vma->vm_mm->cpu_vm_mask);
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} else
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local_flush_tlb_page(vma, uaddr);
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}
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void flush_tlb_kernel_page(unsigned long kaddr)
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{
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struct tlb_args ta;
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ta.ta_start = kaddr;
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on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1);
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if (tlb_ops_need_broadcast()) {
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struct tlb_args ta;
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ta.ta_start = kaddr;
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on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1);
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} else
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local_flush_tlb_kernel_page(kaddr);
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}
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void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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struct tlb_args ta;
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ta.ta_vma = vma;
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ta.ta_start = start;
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ta.ta_end = end;
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on_each_cpu_mask(ipi_flush_tlb_range, &ta, 1, &vma->vm_mm->cpu_vm_mask);
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if (tlb_ops_need_broadcast()) {
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struct tlb_args ta;
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ta.ta_vma = vma;
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ta.ta_start = start;
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ta.ta_end = end;
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on_each_cpu_mask(ipi_flush_tlb_range, &ta, 1, &vma->vm_mm->cpu_vm_mask);
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} else
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local_flush_tlb_range(vma, start, end);
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}
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void flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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struct tlb_args ta;
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ta.ta_start = start;
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ta.ta_end = end;
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on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
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if (tlb_ops_need_broadcast()) {
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struct tlb_args ta;
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ta.ta_start = start;
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ta.ta_end = end;
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on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
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} else
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local_flush_tlb_kernel_range(start, end);
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}
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@ -176,8 +176,8 @@ cpu_v7_name:
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*/
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__v7_setup:
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#ifdef CONFIG_SMP
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mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode
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orr r0, r0, #(0x1 << 6)
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mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode and
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orr r0, r0, #(1 << 6) | (1 << 0) @ TLB ops broadcasting
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mcr p15, 0, r0, c1, c0, 1
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#endif
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adr r12, __v7_setup_stack @ the local stack
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@ -42,9 +42,11 @@ ENTRY(v7wbi_flush_user_tlb_range)
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mov r1, r1, lsl #PAGE_SHIFT
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vma_vm_flags r2, r2 @ get vma->vm_flags
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1:
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mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
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tst r2, #VM_EXEC @ Executable area ?
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mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
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#ifdef CONFIG_SMP
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mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable)
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#else
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mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate U MVA
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#endif
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add r0, r0, #PAGE_SZ
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cmp r0, r1
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blo 1b
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@ -69,8 +71,11 @@ ENTRY(v7wbi_flush_kern_tlb_range)
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mov r0, r0, lsl #PAGE_SHIFT
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mov r1, r1, lsl #PAGE_SHIFT
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1:
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mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
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mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
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#ifdef CONFIG_SMP
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mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable)
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#else
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mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate U MVA
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#endif
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add r0, r0, #PAGE_SZ
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cmp r0, r1
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blo 1b
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@ -87,5 +92,5 @@ ENDPROC(v7wbi_flush_kern_tlb_range)
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ENTRY(v7wbi_tlb_fns)
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.long v7wbi_flush_user_tlb_range
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.long v7wbi_flush_kern_tlb_range
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.long v6wbi_tlb_flags
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.long v7wbi_tlb_flags
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.size v7wbi_tlb_fns, . - v7wbi_tlb_fns
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