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Merge branch 'remotes/lorenzo/pci/tegra'
- Revert tegra RAW fixup that caused a regression (Nicolas Chauvet) - Remove PLL power supplies from tegra driver and DT binding (Thierry Reding) * remotes/lorenzo/pci/tegra: PCI: tegra: Remove PLL power supplies dt-bindings: pci: tegra: Remove PLL power supplies PCI: tegra: Revert tegra124 raw_violation_fixup
This commit is contained in:
Bjorn Helgaas
commit
fa6cc79a3e
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@ -112,28 +112,16 @@ Power supplies for Tegra124:
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- Required:
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- avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
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- dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
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- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
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supply 1.05 V.
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- hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
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Must supply 3.3 V.
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- hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
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Must supply 3.3 V.
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- vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
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supply 2.8-3.3 V.
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- avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must
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supply 1.05 V.
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Power supplies for Tegra210:
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- Required:
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- avdd-pll-uerefe-supply: Power supply for PLLE (shared with USB3). Must
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supply 1.05 V.
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- hvddio-pex-supply: High-voltage supply for PCIe I/O and PCIe output
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clocks. Must supply 1.8 V.
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- dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
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- dvdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
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supply 1.05 V.
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- hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
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Must supply 3.3 V.
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- vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
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supply 1.8 V.
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@ -181,13 +181,6 @@
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#define AFI_PEXBIAS_CTRL_0 0x168
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#define RP_PRIV_XP_DL 0x00000494
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#define RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD (0x1ff << 1)
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#define RP_RX_HDR_LIMIT 0x00000e00
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#define RP_RX_HDR_LIMIT_PW_MASK (0xff << 8)
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#define RP_RX_HDR_LIMIT_PW (0x0e << 8)
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#define RP_ECTL_2_R1 0x00000e84
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#define RP_ECTL_2_R1_RX_CTLE_1C_MASK 0xffff
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@ -323,7 +316,6 @@ struct tegra_pcie_soc {
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bool program_uphy;
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bool update_clamp_threshold;
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bool program_deskew_time;
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bool raw_violation_fixup;
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bool update_fc_timer;
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bool has_cache_bars;
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struct {
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@ -659,23 +651,6 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
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writel(value, port->base + RP_VEND_CTL0);
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}
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/* Fixup for read after write violation. */
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if (soc->raw_violation_fixup) {
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value = readl(port->base + RP_RX_HDR_LIMIT);
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value &= ~RP_RX_HDR_LIMIT_PW_MASK;
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value |= RP_RX_HDR_LIMIT_PW;
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writel(value, port->base + RP_RX_HDR_LIMIT);
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value = readl(port->base + RP_PRIV_XP_DL);
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value |= RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD;
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writel(value, port->base + RP_PRIV_XP_DL);
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value = readl(port->base + RP_VEND_XP);
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value &= ~RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK;
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value |= soc->update_fc_threshold;
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writel(value, port->base + RP_VEND_XP);
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}
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if (soc->update_fc_timer) {
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value = readl(port->base + RP_VEND_XP);
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value &= ~RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK;
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@ -2025,7 +2000,7 @@ static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)
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pcie->supplies[i++].supply = "hvdd-pex";
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pcie->supplies[i++].supply = "vddio-pexctl-aud";
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} else if (of_device_is_compatible(np, "nvidia,tegra210-pcie")) {
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pcie->num_supplies = 6;
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pcie->num_supplies = 3;
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pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
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sizeof(*pcie->supplies),
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@ -2033,14 +2008,11 @@ static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)
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if (!pcie->supplies)
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return -ENOMEM;
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pcie->supplies[i++].supply = "avdd-pll-uerefe";
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pcie->supplies[i++].supply = "hvddio-pex";
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pcie->supplies[i++].supply = "dvddio-pex";
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pcie->supplies[i++].supply = "dvdd-pex-pll";
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pcie->supplies[i++].supply = "hvdd-pex-pll-e";
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pcie->supplies[i++].supply = "vddio-pex-ctl";
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} else if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) {
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pcie->num_supplies = 7;
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pcie->num_supplies = 4;
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pcie->supplies = devm_kcalloc(dev, pcie->num_supplies,
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sizeof(*pcie->supplies),
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@ -2050,11 +2022,8 @@ static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)
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pcie->supplies[i++].supply = "avddio-pex";
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pcie->supplies[i++].supply = "dvddio-pex";
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pcie->supplies[i++].supply = "avdd-pex-pll";
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pcie->supplies[i++].supply = "hvdd-pex";
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pcie->supplies[i++].supply = "hvdd-pex-pll-e";
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pcie->supplies[i++].supply = "vddio-pex-ctl";
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pcie->supplies[i++].supply = "avdd-pll-erefe";
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} else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
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bool need_pexa = false, need_pexb = false;
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@ -2416,7 +2385,6 @@ static const struct tegra_pcie_soc tegra20_pcie = {
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.program_uphy = true,
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.update_clamp_threshold = false,
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.program_deskew_time = false,
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.raw_violation_fixup = false,
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.update_fc_timer = false,
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.has_cache_bars = true,
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.ectl.enable = false,
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@ -2446,7 +2414,6 @@ static const struct tegra_pcie_soc tegra30_pcie = {
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.program_uphy = true,
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.update_clamp_threshold = false,
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.program_deskew_time = false,
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.raw_violation_fixup = false,
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.update_fc_timer = false,
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.has_cache_bars = false,
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.ectl.enable = false,
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@ -2459,8 +2426,6 @@ static const struct tegra_pcie_soc tegra124_pcie = {
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.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
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.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
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.pads_refclk_cfg0 = 0x44ac44ac,
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/* FC threshold is bit[25:18] */
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.update_fc_threshold = 0x03fc0000,
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.has_pex_clkreq_en = true,
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.has_pex_bias_ctrl = true,
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.has_intr_prsnt_sense = true,
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@ -2470,7 +2435,6 @@ static const struct tegra_pcie_soc tegra124_pcie = {
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.program_uphy = true,
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.update_clamp_threshold = true,
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.program_deskew_time = false,
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.raw_violation_fixup = true,
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.update_fc_timer = false,
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.has_cache_bars = false,
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.ectl.enable = false,
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@ -2494,7 +2458,6 @@ static const struct tegra_pcie_soc tegra210_pcie = {
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.program_uphy = true,
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.update_clamp_threshold = true,
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.program_deskew_time = true,
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.raw_violation_fixup = false,
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.update_fc_timer = true,
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.has_cache_bars = false,
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.ectl = {
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@ -2536,7 +2499,6 @@ static const struct tegra_pcie_soc tegra186_pcie = {
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.program_uphy = false,
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.update_clamp_threshold = false,
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.program_deskew_time = false,
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.raw_violation_fixup = false,
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.update_fc_timer = false,
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.has_cache_bars = false,
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.ectl.enable = false,
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