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ASoC: mmp: add sspa support
The SSPA is a configurable multi-channel audio serial (TDM) interface. It's configurable at runtime to support up to 128 channels and the number of bits per sample: 8, 12, 16, 20, 24 and 32 bits. It also support stereo format: I2S, left-justified or right-justified. Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Leo Yan <leoy@marvell.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Zhangfei Gao
Mark Brown
parent
7a824e214e
commit
fa375d42f0
@ -35,6 +35,9 @@ config SND_PXA_SOC_SSP
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tristate
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select PXA_SSP
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config SND_MMP_SOC_SSPA
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tristate
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config SND_PXA2XX_SOC_CORGI
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tristate "SoC Audio support for Sharp Zaurus SL-C7x0"
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depends on SND_PXA2XX_SOC && PXA_SHARP_C7xx
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@ -4,12 +4,14 @@ snd-soc-pxa2xx-ac97-objs := pxa2xx-ac97.o
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snd-soc-pxa2xx-i2s-objs := pxa2xx-i2s.o
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snd-soc-pxa-ssp-objs := pxa-ssp.o
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snd-soc-mmp-objs := mmp-pcm.o
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snd-soc-mmp-sspa-objs := mmp-sspa.o
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obj-$(CONFIG_SND_PXA2XX_SOC) += snd-soc-pxa2xx.o
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obj-$(CONFIG_SND_PXA2XX_SOC_AC97) += snd-soc-pxa2xx-ac97.o
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obj-$(CONFIG_SND_PXA2XX_SOC_I2S) += snd-soc-pxa2xx-i2s.o
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obj-$(CONFIG_SND_PXA_SOC_SSP) += snd-soc-pxa-ssp.o
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obj-$(CONFIG_SND_MMP_SOC) += snd-soc-mmp.o
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obj-$(CONFIG_SND_MMP_SOC_SSPA) += snd-soc-mmp-sspa.o
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# PXA Machine Support
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snd-soc-corgi-objs := corgi.o
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480
sound/soc/pxa/mmp-sspa.c
Normal file
480
sound/soc/pxa/mmp-sspa.c
Normal file
@ -0,0 +1,480 @@
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/*
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* linux/sound/soc/pxa/mmp-sspa.c
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* Base on pxa2xx-ssp.c
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*
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* Copyright (C) 2011 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/pxa2xx_ssp.h>
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#include <linux/io.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/initval.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/pxa2xx-lib.h>
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#include "mmp-sspa.h"
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/*
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* SSPA audio private data
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*/
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struct sspa_priv {
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struct ssp_device *sspa;
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struct pxa2xx_pcm_dma_params *dma_params;
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struct clk *audio_clk;
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struct clk *sysclk;
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int dai_fmt;
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int running_cnt;
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};
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static void mmp_sspa_write_reg(struct ssp_device *sspa, u32 reg, u32 val)
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{
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__raw_writel(val, sspa->mmio_base + reg);
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}
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static u32 mmp_sspa_read_reg(struct ssp_device *sspa, u32 reg)
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{
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return __raw_readl(sspa->mmio_base + reg);
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}
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static void mmp_sspa_tx_enable(struct ssp_device *sspa)
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{
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unsigned int sspa_sp;
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sspa_sp = mmp_sspa_read_reg(sspa, SSPA_TXSP);
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sspa_sp |= SSPA_SP_S_EN;
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sspa_sp |= SSPA_SP_WEN;
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mmp_sspa_write_reg(sspa, SSPA_TXSP, sspa_sp);
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}
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static void mmp_sspa_tx_disable(struct ssp_device *sspa)
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{
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unsigned int sspa_sp;
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sspa_sp = mmp_sspa_read_reg(sspa, SSPA_TXSP);
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sspa_sp &= ~SSPA_SP_S_EN;
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sspa_sp |= SSPA_SP_WEN;
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mmp_sspa_write_reg(sspa, SSPA_TXSP, sspa_sp);
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}
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static void mmp_sspa_rx_enable(struct ssp_device *sspa)
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{
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unsigned int sspa_sp;
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sspa_sp = mmp_sspa_read_reg(sspa, SSPA_RXSP);
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sspa_sp |= SSPA_SP_S_EN;
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sspa_sp |= SSPA_SP_WEN;
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mmp_sspa_write_reg(sspa, SSPA_RXSP, sspa_sp);
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}
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static void mmp_sspa_rx_disable(struct ssp_device *sspa)
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{
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unsigned int sspa_sp;
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sspa_sp = mmp_sspa_read_reg(sspa, SSPA_RXSP);
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sspa_sp &= ~SSPA_SP_S_EN;
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sspa_sp |= SSPA_SP_WEN;
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mmp_sspa_write_reg(sspa, SSPA_RXSP, sspa_sp);
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}
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static int mmp_sspa_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct sspa_priv *priv = snd_soc_dai_get_drvdata(dai);
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clk_enable(priv->sysclk);
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clk_enable(priv->sspa->clk);
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return 0;
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}
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static void mmp_sspa_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct sspa_priv *priv = snd_soc_dai_get_drvdata(dai);
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clk_disable(priv->sspa->clk);
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clk_disable(priv->sysclk);
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return;
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}
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/*
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* Set the SSP ports SYSCLK.
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*/
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static int mmp_sspa_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
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int clk_id, unsigned int freq, int dir)
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{
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struct sspa_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
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int ret = 0;
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switch (clk_id) {
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case MMP_SSPA_CLK_AUDIO:
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ret = clk_set_rate(priv->audio_clk, freq);
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if (ret)
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return ret;
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break;
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case MMP_SSPA_CLK_PLL:
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case MMP_SSPA_CLK_VCXO:
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/* not support yet */
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return -EINVAL;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int mmp_sspa_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
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int source, unsigned int freq_in,
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unsigned int freq_out)
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{
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struct sspa_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
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int ret = 0;
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switch (pll_id) {
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case MMP_SYSCLK:
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ret = clk_set_rate(priv->sysclk, freq_out);
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if (ret)
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return ret;
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break;
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case MMP_SSPA_CLK:
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ret = clk_set_rate(priv->sspa->clk, freq_out);
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if (ret)
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return ret;
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break;
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default:
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return -ENODEV;
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}
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return 0;
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}
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/*
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* Set up the sspa dai format. The sspa port must be inactive
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* before calling this function as the physical
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* interface format is changed.
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*/
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static int mmp_sspa_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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unsigned int fmt)
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{
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struct sspa_priv *sspa_priv = snd_soc_dai_get_drvdata(cpu_dai);
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struct ssp_device *sspa = sspa_priv->sspa;
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u32 sspa_sp, sspa_ctrl;
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/* check if we need to change anything at all */
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if (sspa_priv->dai_fmt == fmt)
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return 0;
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/* we can only change the settings if the port is not in use */
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if ((mmp_sspa_read_reg(sspa, SSPA_TXSP) & SSPA_SP_S_EN) ||
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(mmp_sspa_read_reg(sspa, SSPA_RXSP) & SSPA_SP_S_EN)) {
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dev_err(&sspa->pdev->dev,
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"can't change hardware dai format: stream is in use\n");
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return -EINVAL;
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}
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/* reset port settings */
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sspa_sp = SSPA_SP_WEN | SSPA_SP_S_RST | SSPA_SP_FFLUSH;
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sspa_ctrl = 0;
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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sspa_sp |= SSPA_SP_MSL;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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break;
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default:
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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sspa_sp |= SSPA_SP_FSP;
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break;
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default:
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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sspa_sp |= SSPA_TXSP_FPER(63);
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sspa_sp |= SSPA_SP_FWID(31);
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sspa_ctrl |= SSPA_CTL_XDATDLY(1);
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break;
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default:
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return -EINVAL;
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}
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mmp_sspa_write_reg(sspa, SSPA_TXSP, sspa_sp);
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mmp_sspa_write_reg(sspa, SSPA_RXSP, sspa_sp);
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sspa_sp &= ~(SSPA_SP_S_RST | SSPA_SP_FFLUSH);
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mmp_sspa_write_reg(sspa, SSPA_TXSP, sspa_sp);
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mmp_sspa_write_reg(sspa, SSPA_RXSP, sspa_sp);
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/*
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* FIXME: hw issue, for the tx serial port,
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* can not config the master/slave mode;
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* so must clean this bit.
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* The master/slave mode has been set in the
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* rx port.
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*/
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sspa_sp &= ~SSPA_SP_MSL;
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mmp_sspa_write_reg(sspa, SSPA_TXSP, sspa_sp);
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mmp_sspa_write_reg(sspa, SSPA_TXCTL, sspa_ctrl);
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mmp_sspa_write_reg(sspa, SSPA_RXCTL, sspa_ctrl);
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/* Since we are configuring the timings for the format by hand
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* we have to defer some things until hw_params() where we
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* know parameters like the sample size.
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*/
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sspa_priv->dai_fmt = fmt;
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return 0;
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}
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/*
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* Set the SSPA audio DMA parameters and sample size.
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* Can be called multiple times by oss emulation.
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*/
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static int mmp_sspa_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
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struct sspa_priv *sspa_priv = snd_soc_dai_get_drvdata(dai);
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struct ssp_device *sspa = sspa_priv->sspa;
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struct pxa2xx_pcm_dma_params *dma_params;
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u32 sspa_ctrl;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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sspa_ctrl = mmp_sspa_read_reg(sspa, SSPA_TXCTL);
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else
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sspa_ctrl = mmp_sspa_read_reg(sspa, SSPA_RXCTL);
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sspa_ctrl &= ~SSPA_CTL_XFRLEN1_MASK;
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sspa_ctrl |= SSPA_CTL_XFRLEN1(params_channels(params) - 1);
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sspa_ctrl &= ~SSPA_CTL_XWDLEN1_MASK;
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sspa_ctrl |= SSPA_CTL_XWDLEN1(SSPA_CTL_32_BITS);
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sspa_ctrl &= ~SSPA_CTL_XSSZ1_MASK;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S8:
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sspa_ctrl |= SSPA_CTL_XSSZ1(SSPA_CTL_8_BITS);
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break;
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case SNDRV_PCM_FORMAT_S16_LE:
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sspa_ctrl |= SSPA_CTL_XSSZ1(SSPA_CTL_16_BITS);
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break;
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case SNDRV_PCM_FORMAT_S20_3LE:
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sspa_ctrl |= SSPA_CTL_XSSZ1(SSPA_CTL_20_BITS);
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break;
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case SNDRV_PCM_FORMAT_S24_3LE:
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sspa_ctrl |= SSPA_CTL_XSSZ1(SSPA_CTL_24_BITS);
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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sspa_ctrl |= SSPA_CTL_XSSZ1(SSPA_CTL_32_BITS);
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break;
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default:
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return -EINVAL;
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}
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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mmp_sspa_write_reg(sspa, SSPA_TXCTL, sspa_ctrl);
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mmp_sspa_write_reg(sspa, SSPA_TXFIFO_LL, 0x1);
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} else {
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mmp_sspa_write_reg(sspa, SSPA_RXCTL, sspa_ctrl);
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mmp_sspa_write_reg(sspa, SSPA_RXFIFO_UL, 0x0);
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}
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dma_params = &sspa_priv->dma_params[substream->stream];
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dma_params->dev_addr = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
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(sspa->phys_base + SSPA_TXD) :
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(sspa->phys_base + SSPA_RXD);
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snd_soc_dai_set_dma_data(cpu_dai, substream, dma_params);
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return 0;
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}
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static int mmp_sspa_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct sspa_priv *sspa_priv = snd_soc_dai_get_drvdata(dai);
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struct ssp_device *sspa = sspa_priv->sspa;
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int ret = 0;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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/*
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* whatever playback or capture, must enable rx.
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* this is a hw issue, so need check if rx has been
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* enabled or not; if has been enabled by another
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* stream, do not enable again.
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*/
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if (!sspa_priv->running_cnt)
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mmp_sspa_rx_enable(sspa);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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mmp_sspa_tx_enable(sspa);
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sspa_priv->running_cnt++;
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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sspa_priv->running_cnt--;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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mmp_sspa_tx_disable(sspa);
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/* have no capture stream, disable rx port */
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if (!sspa_priv->running_cnt)
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mmp_sspa_rx_disable(sspa);
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break;
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default:
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ret = -EINVAL;
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}
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return ret;
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}
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static int mmp_sspa_probe(struct snd_soc_dai *dai)
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{
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struct sspa_priv *priv = dev_get_drvdata(dai->dev);
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snd_soc_dai_set_drvdata(dai, priv);
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return 0;
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}
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#define MMP_SSPA_RATES SNDRV_PCM_RATE_8000_192000
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#define MMP_SSPA_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
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SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S24_LE | \
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SNDRV_PCM_FMTBIT_S24_LE | \
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SNDRV_PCM_FMTBIT_S32_LE)
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static struct snd_soc_dai_ops mmp_sspa_dai_ops = {
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.startup = mmp_sspa_startup,
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.shutdown = mmp_sspa_shutdown,
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.trigger = mmp_sspa_trigger,
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.hw_params = mmp_sspa_hw_params,
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.set_sysclk = mmp_sspa_set_dai_sysclk,
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.set_pll = mmp_sspa_set_dai_pll,
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.set_fmt = mmp_sspa_set_dai_fmt,
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};
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struct snd_soc_dai_driver mmp_sspa_dai = {
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.probe = mmp_sspa_probe,
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.playback = {
|
||||
.channels_min = 1,
|
||||
.channels_max = 128,
|
||||
.rates = MMP_SSPA_RATES,
|
||||
.formats = MMP_SSPA_FORMATS,
|
||||
},
|
||||
.capture = {
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = MMP_SSPA_RATES,
|
||||
.formats = MMP_SSPA_FORMATS,
|
||||
},
|
||||
.ops = &mmp_sspa_dai_ops,
|
||||
};
|
||||
|
||||
static __devinit int asoc_mmp_sspa_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct sspa_priv *priv;
|
||||
struct resource *res;
|
||||
|
||||
priv = devm_kzalloc(&pdev->dev,
|
||||
sizeof(struct sspa_priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->sspa = devm_kzalloc(&pdev->dev,
|
||||
sizeof(struct ssp_device), GFP_KERNEL);
|
||||
if (priv->sspa == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->dma_params = devm_kzalloc(&pdev->dev,
|
||||
2 * sizeof(struct pxa2xx_pcm_dma_params), GFP_KERNEL);
|
||||
if (priv->dma_params == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (res == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->sspa->mmio_base = devm_request_and_ioremap(&pdev->dev, res);
|
||||
if (priv->sspa->mmio_base == NULL)
|
||||
return -ENODEV;
|
||||
|
||||
priv->sspa->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(priv->sspa->clk))
|
||||
return PTR_ERR(priv->sspa->clk);
|
||||
|
||||
priv->audio_clk = clk_get(NULL, "mmp-audio");
|
||||
if (IS_ERR(priv->audio_clk))
|
||||
return PTR_ERR(priv->audio_clk);
|
||||
|
||||
priv->sysclk = clk_get(NULL, "mmp-sysclk");
|
||||
if (IS_ERR(priv->sysclk)) {
|
||||
clk_put(priv->audio_clk);
|
||||
return PTR_ERR(priv->sysclk);
|
||||
}
|
||||
clk_enable(priv->audio_clk);
|
||||
priv->dai_fmt = (unsigned int) -1;
|
||||
platform_set_drvdata(pdev, priv);
|
||||
|
||||
return snd_soc_register_dai(&pdev->dev, &mmp_sspa_dai);
|
||||
}
|
||||
|
||||
static int __devexit asoc_mmp_sspa_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sspa_priv *priv = platform_get_drvdata(pdev);
|
||||
|
||||
clk_disable(priv->audio_clk);
|
||||
clk_put(priv->audio_clk);
|
||||
clk_put(priv->sysclk);
|
||||
snd_soc_unregister_dai(&pdev->dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver asoc_mmp_sspa_driver = {
|
||||
.driver = {
|
||||
.name = "mmp-sspa-dai",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.probe = asoc_mmp_sspa_probe,
|
||||
.remove = __devexit_p(asoc_mmp_sspa_remove),
|
||||
};
|
||||
|
||||
module_platform_driver(asoc_mmp_sspa_driver);
|
||||
|
||||
MODULE_AUTHOR("Leo Yan <leoy@marvell.com>");
|
||||
MODULE_DESCRIPTION("MMP SSPA SoC Interface");
|
||||
MODULE_LICENSE("GPL");
|
||||
92
sound/soc/pxa/mmp-sspa.h
Normal file
92
sound/soc/pxa/mmp-sspa.h
Normal file
@ -0,0 +1,92 @@
|
||||
/*
|
||||
* linux/sound/soc/pxa/mmp-sspa.h
|
||||
*
|
||||
* Copyright (C) 2011 Marvell International Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
#ifndef _MMP_SSPA_H
|
||||
#define _MMP_SSPA_H
|
||||
|
||||
/*
|
||||
* SSPA Registers
|
||||
*/
|
||||
#define SSPA_RXD (0x00)
|
||||
#define SSPA_RXID (0x04)
|
||||
#define SSPA_RXCTL (0x08)
|
||||
#define SSPA_RXSP (0x0c)
|
||||
#define SSPA_RXFIFO_UL (0x10)
|
||||
#define SSPA_RXINT_MASK (0x14)
|
||||
#define SSPA_RXC (0x18)
|
||||
#define SSPA_RXFIFO_NOFS (0x1c)
|
||||
#define SSPA_RXFIFO_SIZE (0x20)
|
||||
|
||||
#define SSPA_TXD (0x80)
|
||||
#define SSPA_TXID (0x84)
|
||||
#define SSPA_TXCTL (0x88)
|
||||
#define SSPA_TXSP (0x8c)
|
||||
#define SSPA_TXFIFO_LL (0x90)
|
||||
#define SSPA_TXINT_MASK (0x94)
|
||||
#define SSPA_TXC (0x98)
|
||||
#define SSPA_TXFIFO_NOFS (0x9c)
|
||||
#define SSPA_TXFIFO_SIZE (0xa0)
|
||||
|
||||
/* SSPA Control Register */
|
||||
#define SSPA_CTL_XPH (1 << 31) /* Read Phase */
|
||||
#define SSPA_CTL_XFIG (1 << 15) /* Transmit Zeros when FIFO Empty */
|
||||
#define SSPA_CTL_JST (1 << 3) /* Audio Sample Justification */
|
||||
#define SSPA_CTL_XFRLEN2_MASK (7 << 24)
|
||||
#define SSPA_CTL_XFRLEN2(x) ((x) << 24) /* Transmit Frame Length in Phase 2 */
|
||||
#define SSPA_CTL_XWDLEN2_MASK (7 << 21)
|
||||
#define SSPA_CTL_XWDLEN2(x) ((x) << 21) /* Transmit Word Length in Phase 2 */
|
||||
#define SSPA_CTL_XDATDLY(x) ((x) << 19) /* Tansmit Data Delay */
|
||||
#define SSPA_CTL_XSSZ2_MASK (7 << 16)
|
||||
#define SSPA_CTL_XSSZ2(x) ((x) << 16) /* Transmit Sample Audio Size */
|
||||
#define SSPA_CTL_XFRLEN1_MASK (7 << 8)
|
||||
#define SSPA_CTL_XFRLEN1(x) ((x) << 8) /* Transmit Frame Length in Phase 1 */
|
||||
#define SSPA_CTL_XWDLEN1_MASK (7 << 5)
|
||||
#define SSPA_CTL_XWDLEN1(x) ((x) << 5) /* Transmit Word Length in Phase 1 */
|
||||
#define SSPA_CTL_XSSZ1_MASK (7 << 0)
|
||||
#define SSPA_CTL_XSSZ1(x) ((x) << 0) /* XSSZ1 */
|
||||
|
||||
#define SSPA_CTL_8_BITS (0x0) /* Sample Size */
|
||||
#define SSPA_CTL_12_BITS (0x1)
|
||||
#define SSPA_CTL_16_BITS (0x2)
|
||||
#define SSPA_CTL_20_BITS (0x3)
|
||||
#define SSPA_CTL_24_BITS (0x4)
|
||||
#define SSPA_CTL_32_BITS (0x5)
|
||||
|
||||
/* SSPA Serial Port Register */
|
||||
#define SSPA_SP_WEN (1 << 31) /* Write Configuration Enable */
|
||||
#define SSPA_SP_MSL (1 << 18) /* Master Slave Configuration */
|
||||
#define SSPA_SP_CLKP (1 << 17) /* CLKP Polarity Clock Edge Select */
|
||||
#define SSPA_SP_FSP (1 << 16) /* FSP Polarity Clock Edge Select */
|
||||
#define SSPA_SP_FFLUSH (1 << 2) /* FIFO Flush */
|
||||
#define SSPA_SP_S_RST (1 << 1) /* Active High Reset Signal */
|
||||
#define SSPA_SP_S_EN (1 << 0) /* Serial Clock Domain Enable */
|
||||
#define SSPA_SP_FWID(x) ((x) << 20) /* Frame-Sync Width */
|
||||
#define SSPA_TXSP_FPER(x) ((x) << 4) /* Frame-Sync Active */
|
||||
|
||||
/* sspa clock sources */
|
||||
#define MMP_SSPA_CLK_PLL 0
|
||||
#define MMP_SSPA_CLK_VCXO 1
|
||||
#define MMP_SSPA_CLK_AUDIO 3
|
||||
|
||||
/* sspa pll id */
|
||||
#define MMP_SYSCLK 0
|
||||
#define MMP_SSPA_CLK 1
|
||||
|
||||
#endif /* _MMP_SSPA_H */
|
||||
Loading…
Reference in New Issue
Block a user