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KVM: VMX: Add proper cache tracking for CR4
Move CR4 caching into the standard register caching mechanism in order to take advantage of the availability checks provided by regs_avail. This avoids multiple VMREADs and retpolines (when configured) during nested VMX transitions as kvm_read_cr4_bits() is invoked multiple times on each transition, e.g. when stuffing CR0 and CR3. As an added bonus, this eliminates a kvm_x86_ops hook, saves a retpoline on SVM when reading CR4, and squashes the confusing naming discrepancy of "cache_reg" vs. "decache_cr4_guest_bits". No functional change intended. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Message-Id: <20200502043234.12481-7-sean.j.christopherson@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -168,6 +168,7 @@ enum kvm_reg {
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VCPU_EXREG_PDPTR = NR_VCPU_REGS,
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VCPU_EXREG_CR3,
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VCPU_EXREG_CR4,
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VCPU_EXREG_RFLAGS,
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VCPU_EXREG_SEGMENTS,
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VCPU_EXREG_EXIT_INFO_1,
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@ -1092,7 +1093,6 @@ struct kvm_x86_ops {
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struct kvm_segment *var, int seg);
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void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l);
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void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu);
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void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu);
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void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0);
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int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4);
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void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer);
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@ -129,8 +129,9 @@ static inline ulong kvm_read_cr0(struct kvm_vcpu *vcpu)
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static inline ulong kvm_read_cr4_bits(struct kvm_vcpu *vcpu, ulong mask)
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{
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ulong tmask = mask & KVM_POSSIBLE_CR4_GUEST_BITS;
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if (tmask & vcpu->arch.cr4_guest_owned_bits)
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kvm_x86_ops.decache_cr4_guest_bits(vcpu);
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if ((tmask & vcpu->arch.cr4_guest_owned_bits) &&
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!kvm_register_is_available(vcpu, VCPU_EXREG_CR4))
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kvm_x86_ops.cache_reg(vcpu, VCPU_EXREG_CR4);
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return vcpu->arch.cr4 & mask;
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}
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@ -1525,10 +1525,6 @@ static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
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{
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}
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static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
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{
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}
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static void update_cr0_intercept(struct vcpu_svm *svm)
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{
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ulong gcr0 = svm->vcpu.arch.cr0;
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@ -4007,7 +4003,6 @@ static struct kvm_x86_ops svm_x86_ops __initdata = {
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.get_cpl = svm_get_cpl,
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.get_cs_db_l_bits = kvm_get_cs_db_l_bits,
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.decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
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.decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
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.set_cr0 = svm_set_cr0,
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.set_cr4 = svm_set_cr4,
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.set_efer = svm_set_efer,
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@ -2204,6 +2204,8 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
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{
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unsigned long guest_owned_bits;
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kvm_register_mark_available(vcpu, reg);
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switch (reg) {
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@ -2221,6 +2223,12 @@ static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
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if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
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vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
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break;
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case VCPU_EXREG_CR4:
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guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
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vcpu->arch.cr4 &= ~guest_owned_bits;
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vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits;
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break;
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default:
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WARN_ON_ONCE(1);
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break;
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@ -2922,14 +2930,6 @@ static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
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vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
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}
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static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
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{
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ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
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vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
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vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
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}
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static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
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{
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struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
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@ -3128,6 +3128,7 @@ int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
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return 1;
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vcpu->arch.cr4 = cr4;
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kvm_register_mark_available(vcpu, VCPU_EXREG_CR4);
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if (!enable_unrestricted_guest) {
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if (enable_ept) {
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@ -7809,7 +7810,6 @@ static struct kvm_x86_ops vmx_x86_ops __initdata = {
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.get_cpl = vmx_get_cpl,
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.get_cs_db_l_bits = vmx_get_cs_db_l_bits,
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.decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
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.decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
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.set_cr0 = vmx_set_cr0,
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.set_cr4 = vmx_set_cr4,
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.set_efer = vmx_set_efer,
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@ -453,6 +453,7 @@ static inline void vmx_register_cache_reset(struct kvm_vcpu *vcpu)
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| (1 << VCPU_EXREG_PDPTR)
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| (1 << VCPU_EXREG_SEGMENTS)
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| (1 << VCPU_EXREG_CR3)
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| (1 << VCPU_EXREG_CR4)
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| (1 << VCPU_EXREG_EXIT_INFO_1)
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| (1 << VCPU_EXREG_EXIT_INFO_2));
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vcpu->arch.regs_dirty = 0;
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