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Update peci-next for v6.6-rc1
* Add Intel Sapphire Rapids support. * Add Nuvoton controller driver. -----BEGIN PGP SIGNATURE----- iQJOBAABCAA4FiEEVeIYQcCloMPRsCC93RgStozwYHYFAmTRcpMaHGl3b25hLndp bmlhcnNrYUBpbnRlbC5jb20ACgkQ3RgStozwYHa/mg/7Bhm/+rOfN3F6yYIVZtAk kc+VskI4H20wmr76D5mx5lzOlhbXQZIN2J2G8dhOJVVVJa+9OzS5Gw5LsVeLZTaf PYZxmkn20hidIz6ULH+CmeN1+JcwSrnbOWzXO/BJbfp9QRbxX2qINB5yi8TgRB9T rJSxzxb98aFXAtZJ1jqJSDGN2LZDmr5M7weFN6k9jMT+x0xivqAny6lKeJdjaMye /IwMWKWzLObUFvgpWsIVAY/RZWIg+vy6JqREu1RdA7HAALco2f0HpE96tkXLv+g0 QiAXzWErcmBsQiN04EX+g+J24tpwuyA8TuDZYg49duX9I8BmI0ydIO/9PRtM3H9J 4wd5EI3vWmH/3gERSHg7QAj9EplJyexWv33gZo0DerglxikfpNryZPhPz+6GEUPr r16oFu+kY/kSaGTcZaQ9Jsvtv/dZWZm+8oDVHNNX5VWH0ZUC8JbPK7PgBovvzAYq KwbyvqVYhzVMBDk0oWP/cEcWhEwA8Q2/v63dE2+ExVcfimHPai0PBwF5sgUyir3p ud9fzjLZUWRumASlRzZNZa3EztP2wuWO/GAo0lJdGDvylX5y8Ms5upwr8RKKhCBi F3ceO0S5Ff4zqKjBvKrhBgzyyFkU6ARoEXhoSVAvr8yAOyxMd+HE+Ci08fx6GvKv VGL4cvD6E5dzbgoOanZk09o= =KO5M -----END PGP SIGNATURE----- Merge tag 'peci-next-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/iwi/linux into char-misc-next Iwona writes: Update peci-next for v6.6-rc1 * Add Intel Sapphire Rapids support. * Add Nuvoton controller driver. * tag 'peci-next-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/iwi/linux: arm64: dts: nuvoton: Add PECI controller node ARM: dts: nuvoton: Add PECI controller node peci: Add peci-npcm controller driver dt-bindings: Add bindings for peci-npcm hwmon: (peci/dimmtemp) Add Sapphire Rapids support hwmon: (peci/cputemp) Add Intel Sapphire Rapids support peci: cpu: Add Intel Sapphire Rapids support
This commit is contained in:
Greg Kroah-Hartman
commit
f90bebb36a
@ -0,0 +1,56 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/peci/nuvoton,npcm-peci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Nuvoton PECI Bus
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maintainers:
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- Tomer Maimon <tmaimon77@gmail.com>
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allOf:
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- $ref: peci-controller.yaml#
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properties:
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compatible:
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enum:
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- nuvoton,npcm750-peci
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- nuvoton,npcm845-peci
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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description:
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Clock source for PECI controller. Should reference the APB clock.
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maxItems: 1
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cmd-timeout-ms:
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minimum: 1
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maximum: 1000
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default: 1000
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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peci-controller@f0100000 {
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compatible = "nuvoton,npcm750-peci";
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reg = <0xf0100000 0x200>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk NPCM7XX_CLK_APB3>;
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cmd-timeout-ms = <1000>;
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};
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...
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@ -220,6 +220,15 @@
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};
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};
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peci: peci-controller@f0100000 {
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compatible = "nuvoton,npcm750-peci";
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reg = <0xf0100000 0x200>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk NPCM7XX_CLK_APB3>;
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cmd-timeout-ms = <1000>;
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status = "disabled";
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};
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spi0: spi@200000 {
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compatible = "nuvoton,npcm750-pspi";
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reg = <0x200000 0x1000>;
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@ -68,6 +68,15 @@
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ranges = <0x0 0x0 0xf0000000 0x00300000>,
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<0xfff00000 0x0 0xfff00000 0x00016000>;
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peci: peci-controller@100000 {
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compatible = "nuvoton,npcm845-peci";
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reg = <0x100000 0x1000>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk NPCM8XX_CLK_APB3>;
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cmd-timeout-ms = <1000>;
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status = "disabled";
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};
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timer0: timer@8000 {
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compatible = "nuvoton,npcm845-timer";
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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@ -363,6 +363,7 @@ static int init_core_mask(struct peci_cputemp *priv)
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switch (peci_dev->info.model) {
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case INTEL_FAM6_ICELAKE_X:
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case INTEL_FAM6_ICELAKE_D:
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case INTEL_FAM6_SAPPHIRERAPIDS_X:
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ret = peci_ep_pci_local_read(peci_dev, 0, reg->bus, reg->dev,
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reg->func, reg->offset + 4, &data);
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if (ret)
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@ -531,6 +532,13 @@ static struct resolved_cores_reg resolved_cores_reg_icx = {
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.offset = 0xd0,
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};
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static struct resolved_cores_reg resolved_cores_reg_spr = {
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.bus = 31,
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.dev = 30,
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.func = 6,
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.offset = 0x80,
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};
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static const struct cpu_info cpu_hsx = {
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.reg = &resolved_cores_reg_hsx,
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.min_peci_revision = 0x33,
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@ -549,6 +557,12 @@ static const struct cpu_info cpu_icx = {
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.thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree,
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};
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static const struct cpu_info cpu_spr = {
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.reg = &resolved_cores_reg_spr,
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.min_peci_revision = 0x40,
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.thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree,
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};
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static const struct auxiliary_device_id peci_cputemp_ids[] = {
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{
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.name = "peci_cpu.cputemp.hsx",
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@ -574,6 +588,10 @@ static const struct auxiliary_device_id peci_cputemp_ids[] = {
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.name = "peci_cpu.cputemp.icxd",
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.driver_data = (kernel_ulong_t)&cpu_icx,
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},
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{
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.name = "peci_cpu.cputemp.spr",
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.driver_data = (kernel_ulong_t)&cpu_spr,
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},
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{ }
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};
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MODULE_DEVICE_TABLE(auxiliary, peci_cputemp_ids);
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@ -30,6 +30,8 @@
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#define DIMM_IDX_MAX_ON_ICX 2
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#define CHAN_RANK_MAX_ON_ICXD 4
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#define DIMM_IDX_MAX_ON_ICXD 2
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#define CHAN_RANK_MAX_ON_SPR 8
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#define DIMM_IDX_MAX_ON_SPR 2
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#define CHAN_RANK_MAX CHAN_RANK_MAX_ON_HSX
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#define DIMM_IDX_MAX DIMM_IDX_MAX_ON_HSX
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@ -530,6 +532,43 @@ read_thresholds_icx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u
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return 0;
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}
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static int
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read_thresholds_spr(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
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{
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u32 reg_val;
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u64 offset;
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int ret;
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u8 dev;
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ret = peci_ep_pci_local_read(priv->peci_dev, 0, 30, 0, 2, 0xd4, ®_val);
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if (ret || !(reg_val & BIT(31)))
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return -ENODATA; /* Use default or previous value */
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ret = peci_ep_pci_local_read(priv->peci_dev, 0, 30, 0, 2, 0xd0, ®_val);
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if (ret)
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return -ENODATA; /* Use default or previous value */
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/*
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* Device 26, Offset 219a8: IMC 0 channel 0 -> rank 0
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* Device 26, Offset 299a8: IMC 0 channel 1 -> rank 1
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* Device 27, Offset 219a8: IMC 1 channel 0 -> rank 2
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* Device 27, Offset 299a8: IMC 1 channel 1 -> rank 3
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* Device 28, Offset 219a8: IMC 2 channel 0 -> rank 4
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* Device 28, Offset 299a8: IMC 2 channel 1 -> rank 5
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* Device 29, Offset 219a8: IMC 3 channel 0 -> rank 6
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* Device 29, Offset 299a8: IMC 3 channel 1 -> rank 7
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*/
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dev = 26 + chan_rank / 2;
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offset = 0x219a8 + dimm_order * 4 + (chan_rank % 2) * 0x8000;
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ret = peci_mmio_read(priv->peci_dev, 0, GET_CPU_SEG(reg_val), GET_CPU_BUS(reg_val),
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dev, 0, offset, data);
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if (ret)
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return ret;
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return 0;
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}
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static const struct dimm_info dimm_hsx = {
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.chan_rank_max = CHAN_RANK_MAX_ON_HSX,
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.dimm_idx_max = DIMM_IDX_MAX_ON_HSX,
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@ -572,6 +611,13 @@ static const struct dimm_info dimm_icxd = {
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.read_thresholds = &read_thresholds_icx,
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};
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static const struct dimm_info dimm_spr = {
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.chan_rank_max = CHAN_RANK_MAX_ON_SPR,
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.dimm_idx_max = DIMM_IDX_MAX_ON_SPR,
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.min_peci_revision = 0x40,
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.read_thresholds = &read_thresholds_spr,
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};
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static const struct auxiliary_device_id peci_dimmtemp_ids[] = {
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{
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.name = "peci_cpu.dimmtemp.hsx",
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@ -597,6 +643,10 @@ static const struct auxiliary_device_id peci_dimmtemp_ids[] = {
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.name = "peci_cpu.dimmtemp.icxd",
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.driver_data = (kernel_ulong_t)&dimm_icxd,
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},
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{
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.name = "peci_cpu.dimmtemp.spr",
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.driver_data = (kernel_ulong_t)&dimm_spr,
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},
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{ }
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};
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MODULE_DEVICE_TABLE(auxiliary, peci_dimmtemp_ids);
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@ -16,3 +16,19 @@ config PECI_ASPEED
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This driver can also be built as a module. If so, the module will
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be called peci-aspeed.
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config PECI_NPCM
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tristate "Nuvoton NPCM PECI support"
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depends on ARCH_NPCM || COMPILE_TEST
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depends on OF
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select REGMAP_MMIO
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help
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This option enables PECI controller driver for Nuvoton NPCM7XX
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and NPCM8XX SoCs. It allows BMC to discover devices connected
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to it and communicate with them using PECI protocol.
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Say Y here if you want support for the Platform Environment Control
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Interface (PECI) bus adapter driver on the Nuvoton NPCM SoCs.
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This support is also available as a module. If so, the module
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will be called peci-npcm.
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@ -1,3 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_PECI_ASPEED) += peci-aspeed.o
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obj-$(CONFIG_PECI_NPCM) += peci-npcm.o
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298
drivers/peci/controller/peci-npcm.c
Normal file
298
drivers/peci/controller/peci-npcm.c
Normal file
@ -0,0 +1,298 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2019 Nuvoton Technology corporation
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/jiffies.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/peci.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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/* NPCM GCR module */
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#define NPCM_INTCR3_OFFSET 0x9C
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#define NPCM_INTCR3_PECIVSEL BIT(19)
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/* NPCM PECI Registers */
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#define NPCM_PECI_CTL_STS 0x00
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#define NPCM_PECI_RD_LENGTH 0x04
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#define NPCM_PECI_ADDR 0x08
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#define NPCM_PECI_CMD 0x0C
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#define NPCM_PECI_CTL2 0x10
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#define NPCM_PECI_WR_LENGTH 0x1C
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#define NPCM_PECI_PDDR 0x2C
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#define NPCM_PECI_DAT_INOUT(n) (0x100 + ((n) * 4))
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#define NPCM_PECI_MAX_REG 0x200
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/* NPCM_PECI_CTL_STS - 0x00 : Control Register */
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#define NPCM_PECI_CTRL_DONE_INT_EN BIT(6)
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#define NPCM_PECI_CTRL_ABRT_ERR BIT(4)
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#define NPCM_PECI_CTRL_CRC_ERR BIT(3)
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#define NPCM_PECI_CTRL_DONE BIT(1)
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#define NPCM_PECI_CTRL_START_BUSY BIT(0)
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/* NPCM_PECI_RD_LENGTH - 0x04 : Command Register */
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#define NPCM_PECI_RD_LEN_MASK GENMASK(6, 0)
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/* NPCM_PECI_CMD - 0x10 : Command Register */
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#define NPCM_PECI_CTL2_MASK GENMASK(7, 6)
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/* NPCM_PECI_WR_LENGTH - 0x1C : Command Register */
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#define NPCM_PECI_WR_LEN_MASK GENMASK(6, 0)
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/* NPCM_PECI_PDDR - 0x2C : Command Register */
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#define NPCM_PECI_PDDR_MASK GENMASK(4, 0)
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#define NPCM_PECI_INT_MASK (NPCM_PECI_CTRL_ABRT_ERR | \
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NPCM_PECI_CTRL_CRC_ERR | \
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NPCM_PECI_CTRL_DONE)
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#define NPCM_PECI_IDLE_CHECK_TIMEOUT_USEC (50 * USEC_PER_MSEC)
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#define NPCM_PECI_IDLE_CHECK_INTERVAL_USEC (10 * USEC_PER_MSEC)
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#define NPCM_PECI_CMD_TIMEOUT_MS_DEFAULT 1000
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#define NPCM_PECI_CMD_TIMEOUT_MS_MAX 60000
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#define NPCM_PECI_HOST_NEG_BIT_RATE_DEFAULT 15
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#define NPCM_PECI_PULL_DOWN_DEFAULT 0
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struct npcm_peci {
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u32 cmd_timeout_ms;
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struct completion xfer_complete;
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struct regmap *regmap;
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u32 status;
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spinlock_t lock; /* to sync completion status handling */
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struct peci_controller *controller;
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struct device *dev;
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struct clk *clk;
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int irq;
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};
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static int npcm_peci_xfer(struct peci_controller *controller, u8 addr, struct peci_request *req)
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{
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struct npcm_peci *priv = dev_get_drvdata(controller->dev.parent);
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unsigned long timeout = msecs_to_jiffies(priv->cmd_timeout_ms);
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unsigned int msg_rd;
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u32 cmd_sts;
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int i, ret;
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/* Check command sts and bus idle state */
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ret = regmap_read_poll_timeout(priv->regmap, NPCM_PECI_CTL_STS, cmd_sts,
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!(cmd_sts & NPCM_PECI_CTRL_START_BUSY),
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NPCM_PECI_IDLE_CHECK_INTERVAL_USEC,
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NPCM_PECI_IDLE_CHECK_TIMEOUT_USEC);
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if (ret)
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return ret; /* -ETIMEDOUT */
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spin_lock_irq(&priv->lock);
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reinit_completion(&priv->xfer_complete);
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regmap_write(priv->regmap, NPCM_PECI_ADDR, addr);
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regmap_write(priv->regmap, NPCM_PECI_RD_LENGTH, NPCM_PECI_WR_LEN_MASK & req->rx.len);
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regmap_write(priv->regmap, NPCM_PECI_WR_LENGTH, NPCM_PECI_WR_LEN_MASK & req->tx.len);
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if (req->tx.len) {
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regmap_write(priv->regmap, NPCM_PECI_CMD, req->tx.buf[0]);
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for (i = 0; i < (req->tx.len - 1); i++)
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regmap_write(priv->regmap, NPCM_PECI_DAT_INOUT(i), req->tx.buf[i + 1]);
|
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}
|
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#if IS_ENABLED(CONFIG_DYNAMIC_DEBUG)
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dev_dbg(priv->dev, "addr : %#02x, tx.len : %#02x, rx.len : %#02x\n",
|
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addr, req->tx.len, req->rx.len);
|
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print_hex_dump_bytes("TX : ", DUMP_PREFIX_NONE, req->tx.buf, req->tx.len);
|
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#endif
|
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priv->status = 0;
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regmap_update_bits(priv->regmap, NPCM_PECI_CTL_STS, NPCM_PECI_CTRL_START_BUSY,
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NPCM_PECI_CTRL_START_BUSY);
|
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spin_unlock_irq(&priv->lock);
|
||||
|
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ret = wait_for_completion_interruptible_timeout(&priv->xfer_complete, timeout);
|
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if (ret < 0)
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return ret;
|
||||
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if (ret == 0) {
|
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dev_dbg(priv->dev, "timeout waiting for a response\n");
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||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
spin_lock_irq(&priv->lock);
|
||||
|
||||
if (priv->status != NPCM_PECI_CTRL_DONE) {
|
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spin_unlock_irq(&priv->lock);
|
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dev_dbg(priv->dev, "no valid response, status: %#02x\n", priv->status);
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||||
return -EIO;
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||||
}
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||||
|
||||
regmap_write(priv->regmap, NPCM_PECI_CMD, 0);
|
||||
|
||||
for (i = 0; i < req->rx.len; i++) {
|
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regmap_read(priv->regmap, NPCM_PECI_DAT_INOUT(i), &msg_rd);
|
||||
req->rx.buf[i] = (u8)msg_rd;
|
||||
}
|
||||
|
||||
spin_unlock_irq(&priv->lock);
|
||||
|
||||
#if IS_ENABLED(CONFIG_DYNAMIC_DEBUG)
|
||||
print_hex_dump_bytes("RX : ", DUMP_PREFIX_NONE, req->rx.buf, req->rx.len);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
static irqreturn_t npcm_peci_irq_handler(int irq, void *arg)
|
||||
{
|
||||
struct npcm_peci *priv = arg;
|
||||
u32 status_ack = 0;
|
||||
u32 status;
|
||||
|
||||
spin_lock(&priv->lock);
|
||||
regmap_read(priv->regmap, NPCM_PECI_CTL_STS, &status);
|
||||
priv->status |= (status & NPCM_PECI_INT_MASK);
|
||||
|
||||
if (status & NPCM_PECI_CTRL_CRC_ERR)
|
||||
status_ack |= NPCM_PECI_CTRL_CRC_ERR;
|
||||
|
||||
if (status & NPCM_PECI_CTRL_ABRT_ERR)
|
||||
status_ack |= NPCM_PECI_CTRL_ABRT_ERR;
|
||||
|
||||
/*
|
||||
* All commands should be ended up with a NPCM_PECI_CTRL_DONE
|
||||
* bit set even in an error case.
|
||||
*/
|
||||
if (status & NPCM_PECI_CTRL_DONE) {
|
||||
status_ack |= NPCM_PECI_CTRL_DONE;
|
||||
complete(&priv->xfer_complete);
|
||||
}
|
||||
|
||||
regmap_write_bits(priv->regmap, NPCM_PECI_CTL_STS, NPCM_PECI_INT_MASK, status_ack);
|
||||
|
||||
spin_unlock(&priv->lock);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int npcm_peci_init_ctrl(struct npcm_peci *priv)
|
||||
{
|
||||
u32 cmd_sts;
|
||||
int ret;
|
||||
|
||||
priv->clk = devm_clk_get_enabled(priv->dev, NULL);
|
||||
if (IS_ERR(priv->clk)) {
|
||||
dev_err(priv->dev, "failed to get ref clock\n");
|
||||
return PTR_ERR(priv->clk);
|
||||
}
|
||||
|
||||
ret = device_property_read_u32(priv->dev, "cmd-timeout-ms", &priv->cmd_timeout_ms);
|
||||
if (ret) {
|
||||
priv->cmd_timeout_ms = NPCM_PECI_CMD_TIMEOUT_MS_DEFAULT;
|
||||
} else if (priv->cmd_timeout_ms > NPCM_PECI_CMD_TIMEOUT_MS_MAX ||
|
||||
priv->cmd_timeout_ms == 0) {
|
||||
dev_warn(priv->dev, "invalid cmd-timeout-ms: %u, falling back to: %u\n",
|
||||
priv->cmd_timeout_ms, NPCM_PECI_CMD_TIMEOUT_MS_DEFAULT);
|
||||
|
||||
priv->cmd_timeout_ms = NPCM_PECI_CMD_TIMEOUT_MS_DEFAULT;
|
||||
}
|
||||
|
||||
regmap_update_bits(priv->regmap, NPCM_PECI_CTL2, NPCM_PECI_CTL2_MASK,
|
||||
NPCM_PECI_PULL_DOWN_DEFAULT << 6);
|
||||
|
||||
regmap_update_bits(priv->regmap, NPCM_PECI_PDDR, NPCM_PECI_PDDR_MASK,
|
||||
NPCM_PECI_HOST_NEG_BIT_RATE_DEFAULT);
|
||||
|
||||
ret = regmap_read_poll_timeout(priv->regmap, NPCM_PECI_CTL_STS, cmd_sts,
|
||||
!(cmd_sts & NPCM_PECI_CTRL_START_BUSY),
|
||||
NPCM_PECI_IDLE_CHECK_INTERVAL_USEC,
|
||||
NPCM_PECI_IDLE_CHECK_TIMEOUT_USEC);
|
||||
if (ret)
|
||||
return ret; /* -ETIMEDOUT */
|
||||
|
||||
/* PECI interrupt enable */
|
||||
regmap_update_bits(priv->regmap, NPCM_PECI_CTL_STS, NPCM_PECI_CTRL_DONE_INT_EN,
|
||||
NPCM_PECI_CTRL_DONE_INT_EN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct regmap_config npcm_peci_regmap_config = {
|
||||
.reg_bits = 8,
|
||||
.val_bits = 8,
|
||||
.max_register = NPCM_PECI_MAX_REG,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static struct peci_controller_ops npcm_ops = {
|
||||
.xfer = npcm_peci_xfer,
|
||||
};
|
||||
|
||||
static int npcm_peci_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct peci_controller *controller;
|
||||
struct npcm_peci *priv;
|
||||
void __iomem *base;
|
||||
int ret;
|
||||
|
||||
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->dev = &pdev->dev;
|
||||
dev_set_drvdata(&pdev->dev, priv);
|
||||
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, &npcm_peci_regmap_config);
|
||||
if (IS_ERR(priv->regmap))
|
||||
return PTR_ERR(priv->regmap);
|
||||
|
||||
priv->irq = platform_get_irq(pdev, 0);
|
||||
if (priv->irq < 0)
|
||||
return priv->irq;
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, priv->irq, npcm_peci_irq_handler,
|
||||
0, "peci-npcm-irq", priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
init_completion(&priv->xfer_complete);
|
||||
spin_lock_init(&priv->lock);
|
||||
|
||||
ret = npcm_peci_init_ctrl(priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
controller = devm_peci_controller_add(priv->dev, &npcm_ops);
|
||||
if (IS_ERR(controller))
|
||||
return dev_err_probe(priv->dev, PTR_ERR(controller),
|
||||
"failed to add npcm peci controller\n");
|
||||
|
||||
priv->controller = controller;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id npcm_peci_of_table[] = {
|
||||
{ .compatible = "nuvoton,npcm750-peci", },
|
||||
{ .compatible = "nuvoton,npcm845-peci", },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, npcm_peci_of_table);
|
||||
|
||||
static struct platform_driver npcm_peci_driver = {
|
||||
.probe = npcm_peci_probe,
|
||||
.driver = {
|
||||
.name = KBUILD_MODNAME,
|
||||
.of_match_table = npcm_peci_of_table,
|
||||
},
|
||||
};
|
||||
module_platform_driver(npcm_peci_driver);
|
||||
|
||||
MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
|
||||
MODULE_DESCRIPTION("NPCM PECI driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_IMPORT_NS(PECI);
|
||||
@ -323,6 +323,11 @@ static const struct peci_device_id peci_cpu_device_ids[] = {
|
||||
.model = INTEL_FAM6_ICELAKE_D,
|
||||
.data = "icxd",
|
||||
},
|
||||
{ /* Sapphire Rapids Xeon */
|
||||
.family = 6,
|
||||
.model = INTEL_FAM6_SAPPHIRERAPIDS_X,
|
||||
.data = "spr",
|
||||
},
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(peci, peci_cpu_device_ids);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user