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This pull request is full of clk driver changes. In fact, there aren't any

Browse Source 
changes to the clk framework this time around. That's probably because everyone
 was on vacation (yours truly included). We did lose a couple clk drivers this
 time around because nobody was using those devices. That skews the diffstat a
 bit, but either way, nothing looks out of the ordinary here. The usual suspects
 are chugging along adding support for more SoCs and fixing bugs.
 
 If I had to choose, I'd say the theme for the past few months has been
 "polish". There's quite a few patches that migrate to
 devm_platform_ioremap_resource() in here. And there's more than a handful of
 patches that move the NR_CLKS define from the DT binding header to the driver.
 There's even patches that migrate drivers to use clk_parent_data and clk_hw to
 describe clk tree topology. It seems that the spring (summer?) cleaning bug got
 some folks, or the semiconductor shortage finally hit the software side.
 
 New Drivers:
  - StarFive JH7110 SoC clock drivers
  - Qualcomm IPQ5018 Global Clock Controller driver
  - Versa3 clk generator to support 48KHz playback/record with audio codec on
    RZ/G2L SMARC EVK
 
 Removed Drivers:
  - Remove non-OF mmp clk drivers
  - Remove OXNAS clk driver
 
 Updates:
  - Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc
  - Move defines for numbers of clks (NR_CLKS) from DT headers to drivers
  - Introduce kstrdup_and_replace() and use it
  - Add PLL rates for Rockchip rk3568
  - Add the display clock tree for Rockchip rv1126
  - Add Audio Clock Generator (ADG) clocks on Renesas R-Car Gen3 and RZ/G2 SoCs
  - Convert sun9i-mmc clock to use devm_platform_get_and_ioremap_resource()
  - Fix function name in a comment in ccu_mmc_timing.c
  - Parameter name correction for ccu_nkm_round_rate()
  - Implement CLK_SET_RATE_PARENT for Allwinner NKM clocks, i.e. consider alternative
    parent rates when determining clock rates
  - Set CLK_SET_RATE_PARENT for Allwinner A64 pll-mipi
  - Support finding closest (as opposed to closest but not higher) clock rate
    for NM, NKM, mux and div type clocks, as use it for Allwinner A64 pll-video0
  - Prefer current parent rate if able to generate ideal clock rate for Allwinner NKM clocks
  - Clean up Qualcomm SMD RPM driver, with interconnect bus clocks moved out to
    the interconnect drivers
  - Fix various PM runtime bugs across many Qualcomm clk drivers
  - Migrate Qualcomm MDM9615 is to parent_hw and parent_data
  - Add network related resets on Qualcomm IPQ4019
  - Add a couple missing USB related clocks to Qualcomm IPQ9574
  - Add missing gpll0_sleep_clk_src to Qualcomm MSM8917 global clock controller
  - In the Qualcomm QDU1000 global clock controller, GDSCs, clkrefs, and GPLL1 are
    added, while PCIe pipe clock, SDCC rcg ops are corrected
  - Add missing GDSCs to and correct GDSCs for the SC8280XP global clock controller driver
  - Support retention for the Qualcomm SC8280XP display clock controller GDSCs.
  - Qualcommm's SDCC apps_clk_src is marked with CLK_OPS_PARENT_ENABLE to fix
    issues with missing parent clocks across sc7180, sm7150, sm6350 and sm8250,
    while sm8450 is corrected to use floor ops
  - Correct Qualcomm SM6350 GPU clock controller's clock supplies
  - Drop unwanted clocks from the Qualcomm IPQ5332 GCC driver
  - Add missing OXILICX GDSC to Qualcomm MSM8226 GCC
  - Change the delay in the Qualcomm reset controller to fsleep() for correctness
  - Extend the Qualcomm SM83550 Video clock controller to support SC8280XP
  - Add graphics clock support on Renesas RZ/G2M, RZ/G2N, RZ/G2E, and R-Car H3,
    M3-W, and M3-N SoCs
  - Add Clocked Serial Interface (CSI) clocks on Renesas RZ/V2M
  - Add PWM (MTU3) clock and reset on Renesas RZ/G2UL and RZ/Five
  - Add the PDM IPC clock for i.MX93
  - Add 519.75MHz frequency support for i.MX9 PLL
  - Simplify the .determine_rate() implementation for i.MX GPR mux
  - Make the i.MX8QXP LPCG clock use devm_platform_ioremap_resource()
  - Add the audio mux clock to i.MX8
  - Fix the SPLL2 MULT range for PLLv4
  - Update the SPLL2 type in i.MX8ULP
  - Fix the SAI4 clock on i.MX8MP
  - Add silicon revision print for i.MX25 on clocks init
  - Drop the return value from __mx25_clocks_init()
  - Fix the clock pauses on no-op set_rate for i.MX8M composite clock
  - Drop restrictions for i.MX PLL14xx and fix its max prediv value
  - Drop the 393216000 and 361267200 from i.MX PLL14xx rate table to allow
    glitch free switching
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk subsystem updates from Stephen Boyd:
 "This pull request is full of clk driver changes. In fact, there aren't
  any changes to the clk framework this time around. That's probably
  because everyone was on vacation (yours truly included). We did lose a
  couple clk drivers this time around because nobody was using those
  devices. That skews the diffstat a bit, but either way, nothing looks
  out of the ordinary here. The usual suspects are chugging along adding
  support for more SoCs and fixing bugs.

  If I had to choose, I'd say the theme for the past few months has been
  "polish". There's quite a few patches that migrate to
  devm_platform_ioremap_resource() in here. And there's more than a
  handful of patches that move the NR_CLKS define from the DT binding
  header to the driver. There's even patches that migrate drivers to use
  clk_parent_data and clk_hw to describe clk tree topology. It seems
  that the spring (summer?) cleaning bug got some folks, or the
  semiconductor shortage finally hit the software side.

  New Drivers:
   - StarFive JH7110 SoC clock drivers
   - Qualcomm IPQ5018 Global Clock Controller driver
   - Versa3 clk generator to support 48KHz playback/record with audio
     codec on RZ/G2L SMARC EVK

  Removed Drivers:
   - Remove non-OF mmp clk drivers
   - Remove OXNAS clk driver

  Updates:
   - Add __counted_by to struct clk_hw_onecell_data and struct
     spmi_pmic_div_clk_cc
   - Move defines for numbers of clks (NR_CLKS) from DT headers to
     drivers
   - Introduce kstrdup_and_replace() and use it
   - Add PLL rates for Rockchip rk3568
   - Add the display clock tree for Rockchip rv1126
   - Add Audio Clock Generator (ADG) clocks on Renesas R-Car Gen3 and
     RZ/G2 SoCs
   - Convert sun9i-mmc clock to use
     devm_platform_get_and_ioremap_resource()
   - Fix function name in a comment in ccu_mmc_timing.c
   - Parameter name correction for ccu_nkm_round_rate()
   - Implement CLK_SET_RATE_PARENT for Allwinner NKM clocks, i.e.
     consider alternative parent rates when determining clock rates
   - Set CLK_SET_RATE_PARENT for Allwinner A64 pll-mipi
   - Support finding closest (as opposed to closest but not higher)
     clock rate for NM, NKM, mux and div type clocks, as use it for
     Allwinner A64 pll-video0
   - Prefer current parent rate if able to generate ideal clock rate for
     Allwinner NKM clocks
   - Clean up Qualcomm SMD RPM driver, with interconnect bus clocks
     moved out to the interconnect drivers
   - Fix various PM runtime bugs across many Qualcomm clk drivers
   - Migrate Qualcomm MDM9615 is to parent_hw and parent_data
   - Add network related resets on Qualcomm IPQ4019
   - Add a couple missing USB related clocks to Qualcomm IPQ9574
   - Add missing gpll0_sleep_clk_src to Qualcomm MSM8917 global clock
     controller
   - In the Qualcomm QDU1000 global clock controller, GDSCs, clkrefs,
     and GPLL1 are added, while PCIe pipe clock, SDCC rcg ops are
     corrected
   - Add missing GDSCs to and correct GDSCs for the SC8280XP global
     clock controller driver
   - Support retention for the Qualcomm SC8280XP display clock
     controller GDSCs.
   - Qualcommm's SDCC apps_clk_src is marked with CLK_OPS_PARENT_ENABLE
     to fix issues with missing parent clocks across sc7180, sm7150,
     sm6350 and sm8250, while sm8450 is corrected to use floor ops
   - Correct Qualcomm SM6350 GPU clock controller's clock supplies
   - Drop unwanted clocks from the Qualcomm IPQ5332 GCC driver
   - Add missing OXILICX GDSC to Qualcomm MSM8226 GCC
   - Change the delay in the Qualcomm reset controller to fsleep() for
     correctness
   - Extend the Qualcomm SM83550 Video clock controller to support
     SC8280XP
   - Add graphics clock support on Renesas RZ/G2M, RZ/G2N, RZ/G2E, and
     R-Car H3, M3-W, and M3-N SoCs
   - Add Clocked Serial Interface (CSI) clocks on Renesas RZ/V2M
   - Add PWM (MTU3) clock and reset on Renesas RZ/G2UL and RZ/Five
   - Add the PDM IPC clock for i.MX93
   - Add 519.75MHz frequency support for i.MX9 PLL
   - Simplify the .determine_rate() implementation for i.MX GPR mux
   - Make the i.MX8QXP LPCG clock use devm_platform_ioremap_resource()
   - Add the audio mux clock to i.MX8
   - Fix the SPLL2 MULT range for PLLv4
   - Update the SPLL2 type in i.MX8ULP
   - Fix the SAI4 clock on i.MX8MP
   - Add silicon revision print for i.MX25 on clocks init
   - Drop the return value from __mx25_clocks_init()
   - Fix the clock pauses on no-op set_rate for i.MX8M composite clock
   - Drop restrictions for i.MX PLL14xx and fix its max prediv value
   - Drop the 393216000 and 361267200 from i.MX PLL14xx rate table to
     allow glitch free switching"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (207 commits)
  clk: qcom: Fix SM_GPUCC_8450 dependencies
  clk: lmk04832: Support using PLL1_LD as SPI readback pin
  clk: lmk04832: Don't disable vco clock on probe fail
  clk: lmk04832: Set missing parent_names for output clocks
  clk: mvebu: Convert to devm_platform_ioremap_resource()
  clk: nuvoton: Convert to devm_platform_ioremap_resource()
  clk: socfpga: agilex: Convert to devm_platform_ioremap_resource()
  clk: ti: Use devm_platform_get_and_ioremap_resource()
  clk: mediatek: Convert to devm_platform_ioremap_resource()
  clk: hsdk-pll: Convert to devm_platform_ioremap_resource()
  clk: gemini: Convert to devm_platform_ioremap_resource()
  clk: fsl-sai: Convert to devm_platform_ioremap_resource()
  clk: bm1880: Convert to devm_platform_ioremap_resource()
  clk: axm5516: Convert to devm_platform_ioremap_resource()
  clk: actions: Convert to devm_platform_ioremap_resource()
  clk: cdce925: Remove redundant of_match_ptr()
  clk: pxa910: Move number of clocks to driver source
  clk: pxa1928: Move number of clocks to driver source
  clk: pxa168: Move number of clocks to driver source
  clk: mmp2: Move number of clocks to driver source
  ...
This commit is contained in:
Linus Torvalds 2023-08-30 19:53:39 -07:00
commit f8fd5c2483
421 changed files with 12697 additions and 7106 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml
View File

@ -29,6 +29,26 @@ properties:
ranges: true
patternProperties:
"^clock@[0-9a-f]+$":
type: object
additionalProperties: false
properties:
compatible:
const: hisilicon,hix5hd2-clock
reg:
maxItems: 1
"#clock-cells":
const: 1
required:
- compatible
- reg
- "#clock-cells"
required:
- compatible
- reg

64
Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
View File

@ -1,64 +0,0 @@
* Amlogic GXBB AO Clock and Reset Unit
The Amlogic GXBB AO clock controller generates and supplies clock to various
controllers within the Always-On part of the SoC.
Required Properties:
- compatible: value should be different for each SoC family as :
- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
- GXM (S912) : "amlogic,meson-gxm-aoclkc"
- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
- G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc"
followed by the common "amlogic,meson-gx-aoclkc"
- clocks: list of clock phandle, one for each entry clock-names.
- clock-names: should contain the following:
* "xtal" : the platform xtal
* "mpeg-clk" : the main clock controller mother clock (aka clk81)
* "ext-32k-0" : external 32kHz reference #0 if any (optional)
* "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only)
* "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only)
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/gxbb-aoclkc.h header and can be
used in device tree sources.
- #reset-cells: should be 1.
Each reset is assigned an identifier and client nodes can use this identifier
to specify the reset which they consume. All available resets are defined as
preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
used in device tree sources.
Parent node should have the following properties :
- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
- reg: base address and size of the AO system control register space.
Example: AO Clock controller node:
ao_sysctrl: sys-ctrl@0 {
compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
reg = <0x0 0x0 0x0 0x100>;
clkc_AO: clock-controller {
compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&xtal>, <&clkc CLKID_CLK81>;
clock-names = "xtal", "mpeg-clk";
};
Example: UART controller node that consumes the clock and reset generated
by the clock controller:
uart_AO: serial@4c0 {
compatible = "amlogic,meson-uart";
reg = <0x4c0 0x14>;
interrupts = <0 90 1>;
clocks = <&clkc_AO CLKID_AO_UART1>;
resets = <&clkc_AO RESET_AO_UART1>;
};

85
Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.yaml Normal file
View File

@ -0,0 +1,85 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,gxbb-aoclkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Always-On Clock Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
properties:
compatible:
oneOf:
- items:
- enum:
- amlogic,meson-gxbb-aoclkc
- amlogic,meson-gxl-aoclkc
- amlogic,meson-gxm-aoclkc
- amlogic,meson-axg-aoclkc
- const: amlogic,meson-gx-aoclkc
- enum:
- amlogic,meson-axg-aoclkc
- amlogic,meson-g12a-aoclkc
clocks:
minItems: 2
maxItems: 5
clock-names:
minItems: 2
items:
- const: xtal
- const: mpeg-clk
- const: ext-32k-0
- const: ext-32k-1
- const: ext-32k-2
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
allOf:
- if:
properties:
compatible:
enum:
- amlogic,meson-g12a-aoclkc
then:
properties:
clocks:
minItems: 2
maxItems: 3
clock-names:
minItems: 2
maxItems: 3
- if:
properties:
compatible:
enum:
- amlogic,meson-gxl-aoclkc
- amlogic,meson-gxm-aoclkc
- amlogic,meson-axg-aoclkc
then:
properties:
clocks:
maxItems: 2
clock-names:
maxItems: 2
additionalProperties: false

53
Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
View File

@ -1,53 +0,0 @@
* Amlogic GXBB Clock and Reset Unit
The Amlogic GXBB clock controller generates and supplies clock to various
controllers within the SoC.
Required Properties:
- compatible: should be:
"amlogic,gxbb-clkc" for GXBB SoC,
"amlogic,gxl-clkc" for GXL and GXM SoC,
"amlogic,axg-clkc" for AXG SoC.
"amlogic,g12a-clkc" for G12A SoC.
"amlogic,g12b-clkc" for G12B SoC.
"amlogic,sm1-clkc" for SM1 SoC.
- clocks : list of clock phandle, one for each entry clock-names.
- clock-names : should contain the following:
* "xtal": the platform xtal
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be
used in device tree sources.
Parent node should have the following properties :
- compatible: "syscon", "simple-mfd, and "amlogic,meson-gx-hhi-sysctrl" or
"amlogic,meson-axg-hhi-sysctrl"
- reg: base address and size of the HHI system control register space.
Example: Clock controller node:
sysctrl: system-controller@0 {
compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
reg = <0 0 0 0x400>;
clkc: clock-controller {
#clock-cells = <1>;
compatible = "amlogic,gxbb-clkc";
clocks = <&xtal>;
clock-names = "xtal";
};
};
Example: UART controller node that consumes the clock generated by the clock
controller:
uart_AO: serial@c81004c0 {
compatible = "amlogic,meson-uart";
reg = <0xc81004c0 0x14>;
interrupts = <0 90 1>;
clocks = <&clkc CLKID_CLK81>;
};

37
Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.yaml Normal file
View File

@ -0,0 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,gxbb-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Clock Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
properties:
compatible:
enum:
- amlogic,gxbb-clkc
- amlogic,gxl-clkc
- amlogic,axg-clkc
- amlogic,g12a-clkc
- amlogic,g12b-clkc
- amlogic,sm1-clkc
clocks:
maxItems: 1
clock-names:
const: xtal
'#clock-cells':
const: 1
required:
- compatible
- clocks
- clock-names
- '#clock-cells'
additionalProperties: false

282
Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml Normal file
View File

@ -0,0 +1,282 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,imx8-acm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8 Audio Clock Mux
maintainers:
- Shengjiu Wang <shengjiu.wang@nxp.com>
description: |
NXP i.MX8 Audio Clock Mux is dedicated clock muxing IP
used to control Audio related clock on the SoC.
properties:
compatible:
enum:
- fsl,imx8dxl-acm
- fsl,imx8qm-acm
- fsl,imx8qxp-acm
reg:
maxItems: 1
power-domains:
minItems: 13
maxItems: 21
'#clock-cells':
const: 1
description:
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8-clock.h
for the full list of i.MX8 ACM clock IDs.
clocks:
minItems: 13
maxItems: 27
clock-names:
minItems: 13
maxItems: 27
required:
- compatible
- reg
- power-domains
- '#clock-cells'
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8qxp-acm
then:
properties:
power-domains:
items:
- description: power domain of IMX_SC_R_AUDIO_CLK_0
- description: power domain of IMX_SC_R_AUDIO_CLK_1
- description: power domain of IMX_SC_R_MCLK_OUT_0
- description: power domain of IMX_SC_R_MCLK_OUT_1
- description: power domain of IMX_SC_R_AUDIO_PLL_0
- description: power domain of IMX_SC_R_AUDIO_PLL_1
- description: power domain of IMX_SC_R_ASRC_0
- description: power domain of IMX_SC_R_ASRC_1
- description: power domain of IMX_SC_R_ESAI_0
- description: power domain of IMX_SC_R_SAI_0
- description: power domain of IMX_SC_R_SAI_1
- description: power domain of IMX_SC_R_SAI_2
- description: power domain of IMX_SC_R_SAI_3
- description: power domain of IMX_SC_R_SAI_4
- description: power domain of IMX_SC_R_SAI_5
- description: power domain of IMX_SC_R_SPDIF_0
- description: power domain of IMX_SC_R_MQS_0
clocks:
minItems: 18
maxItems: 18
clock-names:
items:
- const: aud_rec_clk0_lpcg_clk
- const: aud_rec_clk1_lpcg_clk
- const: aud_pll_div_clk0_lpcg_clk
- const: aud_pll_div_clk1_lpcg_clk
- const: ext_aud_mclk0
- const: ext_aud_mclk1
- const: esai0_rx_clk
- const: esai0_rx_hf_clk
- const: esai0_tx_clk
- const: esai0_tx_hf_clk
- const: spdif0_rx
- const: sai0_rx_bclk
- const: sai0_tx_bclk
- const: sai1_rx_bclk
- const: sai1_tx_bclk
- const: sai2_rx_bclk
- const: sai3_rx_bclk
- const: sai4_rx_bclk
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8qm-acm
then:
properties:
power-domains:
items:
- description: power domain of IMX_SC_R_AUDIO_CLK_0
- description: power domain of IMX_SC_R_AUDIO_CLK_1
- description: power domain of IMX_SC_R_MCLK_OUT_0
- description: power domain of IMX_SC_R_MCLK_OUT_1
- description: power domain of IMX_SC_R_AUDIO_PLL_0
- description: power domain of IMX_SC_R_AUDIO_PLL_1
- description: power domain of IMX_SC_R_ASRC_0
- description: power domain of IMX_SC_R_ASRC_1
- description: power domain of IMX_SC_R_ESAI_0
- description: power domain of IMX_SC_R_ESAI_1
- description: power domain of IMX_SC_R_SAI_0
- description: power domain of IMX_SC_R_SAI_1
- description: power domain of IMX_SC_R_SAI_2
- description: power domain of IMX_SC_R_SAI_3
- description: power domain of IMX_SC_R_SAI_4
- description: power domain of IMX_SC_R_SAI_5
- description: power domain of IMX_SC_R_SAI_6
- description: power domain of IMX_SC_R_SAI_7
- description: power domain of IMX_SC_R_SPDIF_0
- description: power domain of IMX_SC_R_SPDIF_1
- description: power domain of IMX_SC_R_MQS_0
clocks:
minItems: 27
maxItems: 27
clock-names:
items:
- const: aud_rec_clk0_lpcg_clk
- const: aud_rec_clk1_lpcg_clk
- const: aud_pll_div_clk0_lpcg_clk
- const: aud_pll_div_clk1_lpcg_clk
- const: mlb_clk
- const: hdmi_rx_mclk
- const: ext_aud_mclk0
- const: ext_aud_mclk1
- const: esai0_rx_clk
- const: esai0_rx_hf_clk
- const: esai0_tx_clk
- const: esai0_tx_hf_clk
- const: esai1_rx_clk
- const: esai1_rx_hf_clk
- const: esai1_tx_clk
- const: esai1_tx_hf_clk
- const: spdif0_rx
- const: spdif1_rx
- const: sai0_rx_bclk
- const: sai0_tx_bclk
- const: sai1_rx_bclk
- const: sai1_tx_bclk
- const: sai2_rx_bclk
- const: sai3_rx_bclk
- const: sai4_rx_bclk
- const: sai5_tx_bclk
- const: sai6_rx_bclk
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8dxl-acm
then:
properties:
power-domains:
items:
- description: power domain of IMX_SC_R_AUDIO_CLK_0
- description: power domain of IMX_SC_R_AUDIO_CLK_1
- description: power domain of IMX_SC_R_MCLK_OUT_0
- description: power domain of IMX_SC_R_MCLK_OUT_1
- description: power domain of IMX_SC_R_AUDIO_PLL_0
- description: power domain of IMX_SC_R_AUDIO_PLL_1
- description: power domain of IMX_SC_R_ASRC_0
- description: power domain of IMX_SC_R_SAI_0
- description: power domain of IMX_SC_R_SAI_1
- description: power domain of IMX_SC_R_SAI_2
- description: power domain of IMX_SC_R_SAI_3
- description: power domain of IMX_SC_R_SPDIF_0
- description: power domain of IMX_SC_R_MQS_0
clocks:
minItems: 13
maxItems: 13
clock-names:
items:
- const: aud_rec_clk0_lpcg_clk
- const: aud_rec_clk1_lpcg_clk
- const: aud_pll_div_clk0_lpcg_clk
- const: aud_pll_div_clk1_lpcg_clk
- const: ext_aud_mclk0
- const: ext_aud_mclk1
- const: spdif0_rx
- const: sai0_rx_bclk
- const: sai0_tx_bclk
- const: sai1_rx_bclk
- const: sai1_tx_bclk
- const: sai2_rx_bclk
- const: sai3_rx_bclk
additionalProperties: false
examples:
# Clock Control Module node:
- |
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
clock-controller@59e00000 {
compatible = "fsl,imx8qxp-acm";
reg = <0x59e00000 0x1d0000>;
#clock-cells = <1>;
power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
<&pd IMX_SC_R_AUDIO_CLK_1>,
<&pd IMX_SC_R_MCLK_OUT_0>,
<&pd IMX_SC_R_MCLK_OUT_1>,
<&pd IMX_SC_R_AUDIO_PLL_0>,
<&pd IMX_SC_R_AUDIO_PLL_1>,
<&pd IMX_SC_R_ASRC_0>,
<&pd IMX_SC_R_ASRC_1>,
<&pd IMX_SC_R_ESAI_0>,
<&pd IMX_SC_R_SAI_0>,
<&pd IMX_SC_R_SAI_1>,
<&pd IMX_SC_R_SAI_2>,
<&pd IMX_SC_R_SAI_3>,
<&pd IMX_SC_R_SAI_4>,
<&pd IMX_SC_R_SAI_5>,
<&pd IMX_SC_R_SPDIF_0>,
<&pd IMX_SC_R_MQS_0>;
clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>,
<&aud_rec1_lpcg IMX_LPCG_CLK_0>,
<&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
<&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
<&clk_ext_aud_mclk0>,
<&clk_ext_aud_mclk1>,
<&clk_esai0_rx_clk>,
<&clk_esai0_rx_hf_clk>,
<&clk_esai0_tx_clk>,
<&clk_esai0_tx_hf_clk>,
<&clk_spdif0_rx>,
<&clk_sai0_rx_bclk>,
<&clk_sai0_tx_bclk>,
<&clk_sai1_rx_bclk>,
<&clk_sai1_tx_bclk>,
<&clk_sai2_rx_bclk>,
<&clk_sai3_rx_bclk>,
<&clk_sai4_rx_bclk>;
clock-names = "aud_rec_clk0_lpcg_clk",
"aud_rec_clk1_lpcg_clk",
"aud_pll_div_clk0_lpcg_clk",
"aud_pll_div_clk1_lpcg_clk",
"ext_aud_mclk0",
"ext_aud_mclk1",
"esai0_rx_clk",
"esai0_rx_hf_clk",
"esai0_tx_clk",
"esai0_tx_hf_clk",
"spdif0_rx",
"sai0_rx_bclk",
"sai0_tx_bclk",
"sai1_rx_bclk",
"sai1_tx_bclk",
"sai2_rx_bclk",
"sai3_rx_bclk",
"sai4_rx_bclk";
};

30
Documentation/devicetree/bindings/clock/hix5hd2-clock.txt
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@ -1,30 +0,0 @@
* Hisilicon Hix5hd2 Clock Controller
The hix5hd2 clock controller generates and supplies clock to various
controllers within the hix5hd2 SoC.
Required Properties:
- compatible: should be "hisilicon,hix5hd2-clock"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
All these identifier could be found in <dt-bindings/clock/hix5hd2-clock.h>.
Examples:
clock: clock@f8a22000 {
compatible = "hisilicon,hix5hd2-clock";
reg = <0xf8a22000 0x1000>;
#clock-cells = <1>;
};
uart0: uart@f8b00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xf8b00000 0x1000>;
interrupts = <0 49 4>;
clocks = <&clock HIX5HD2_FIXED_83M>;
clock-names = "apb_pclk";
};

28
Documentation/devicetree/bindings/clock/oxnas,stdclk.txt
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@ -1,28 +0,0 @@
Oxford Semiconductor OXNAS SoC Family Standard Clocks
================================================
Please also refer to clock-bindings.txt in this directory for common clock
bindings usage.
Required properties:
- compatible: For OX810SE, should be "oxsemi,ox810se-stdclk"
For OX820, should be "oxsemi,ox820-stdclk"
- #clock-cells: 1, see below
Parent node should have the following properties :
- compatible: For OX810SE, should be
"oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"
For OX820, should be
"oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"
example:
sys: sys-ctrl@000000 {
compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
reg = <0x000000 0x100000>;
stdclk: stdclk {
compatible = "oxsemi,ox810se-stdclk";
#clock-cells = <1>;
};
};

2
Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
View File

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on APQ8064/MSM8960
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power

2
Documentation/devicetree/bindings/clock/qcom,gcc-ipq4019.yaml
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@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on IPQ4019
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
- Robert Marko <robert.markoo@sartura.hr>
description: |

2
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
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@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on IPQ8074
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power

2
Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml
View File

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on MSM8976
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power

2
Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml
View File

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on MSM8996
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module which provides the clocks, resets and

2
Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml
View File

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on MSM8998
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power

5
Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
View File

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
@ -19,8 +19,6 @@ description: |
include/dt-bindings/reset/qcom,gcc-ipq6018.h
include/dt-bindings/clock/qcom,gcc-msm8953.h
include/dt-bindings/clock/qcom,gcc-mdm9607.h
include/dt-bindings/clock/qcom,gcc-mdm9615.h
include/dt-bindings/reset/qcom,gcc-mdm9615.h
allOf:
- $ref: qcom,gcc.yaml#
@ -30,7 +28,6 @@ properties:
enum:
- qcom,gcc-ipq6018
- qcom,gcc-mdm9607
- qcom,gcc-mdm9615
required:
- compatible

2
Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml
View File

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on QCS404
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power

2
Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
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@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on SC7180
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power

2
Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power

2
Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
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@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on SDM670 and SDM845
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power

2
Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
View File

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on SM8150
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power

2
Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
View File

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on SM8250
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power

2
Documentation/devicetree/bindings/clock/qcom,gcc.yaml
View File

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller Common Properties
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Common bindings for Qualcomm global clock control module providing the

2
Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm graphics clock control module provides the clocks, resets and power

34
Documentation/devicetree/bindings/clock/qcom,lcc.yaml
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@ -76,6 +76,40 @@ allOf:
- clocks
- clock-names
- if:
properties:
compatible:
contains:
enum:
- qcom,lcc-mdm9615
then:
properties:
clocks:
items:
- description: Board CXO source
- description: PLL 4 Vote clock
- description: MI2S codec clock
- description: Mic I2S codec clock
- description: Mic I2S spare clock
- description: Speaker I2S codec clock
- description: Speaker I2S spare clock
- description: PCM codec clock
clock-names:
items:
- const: cxo
- const: pll4_vote
- const: mi2s_codec_clk
- const: codec_i2s_mic_codec_clk
- const: spare_i2s_mic_codec_clk
- const: codec_i2s_spkr_codec_clk
- const: spare_i2s_spkr_codec_clk
- const: pcm_codec_clk
required:
- clocks
- clock-names
examples:
- |
clock-controller@28000000 {

4
Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
View File

@ -8,7 +8,7 @@ title: Qualcomm Multimedia Clock & Reset Controller
maintainers:
- Jeffrey Hugo <quic_jhugo@quicinc.com>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm multimedia clock control module provides the clocks, resets and
@ -297,6 +297,7 @@ allOf:
- description: HDMI phy PLL clock
- description: DisplayPort phy PLL link clock
- description: DisplayPort phy PLL vco clock
- description: Global PLL 0 DIV clock
clock-names:
items:
@ -309,6 +310,7 @@ allOf:
- const: hdmipll
- const: dplink
- const: dpvco
- const: gpll0_div
- if:
properties:

4
Documentation/devicetree/bindings/clock/qcom,msm8996-cbf.yaml
View File

@ -15,7 +15,9 @@ description: >
properties:
compatible:
const: qcom,msm8996-cbf
enum:
- qcom,msm8996-cbf
- qcom,msm8996pro-cbf
reg:
maxItems: 1

2
Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on MSM8998
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm graphics clock control module provides the clocks, resets and power

3
Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml
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@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000
maintainers:
- Melody Olvera <quic_molvera@quicinc.com>
- Taniya Das <quic_tdas@quicinc.com>
- Imran Shaik <quic_imrashai@quicinc.com>
description: |
Qualcomm global clock control module which supports the clocks, resets and

2
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. RPMh Clocks
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Resource Power Manager Hardened (RPMh) manages shared resources on

2
Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller on SC7180
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and power

2
Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on SC7180
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm display clock control module provides the clocks, resets and power

2
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm LPASS Core Clock Controller on SC7180
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm LPASS core clock control module provides the clocks and power

2
Documentation/devicetree/bindings/clock/qcom,sc7180-mss.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Modem Clock Controller on SC7180
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm modem clock control module provides the clocks on SC7180.

2
Documentation/devicetree/bindings/clock/qcom,sc7280-camcc.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller on SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and

2
Documentation/devicetree/bindings/clock/qcom,sc7280-dispcc.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm display clock control module provides the clocks, resets and power

2
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm LPASS Core Clock Controller on SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm LPASS core clock control module provides the clocks and power

2
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm LPASS Core & Audio Clock Controller on SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm LPASS core and audio clock control module provides the clocks and

2
Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on SDM845
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm display clock control module provides the clocks, resets and power

4
Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml
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@ -19,7 +19,9 @@ description: |
properties:
compatible:
const: qcom,sm8350-videocc
enum:
- qcom,sc8280xp-videocc
- qcom,sm8350-videocc
clocks:
items:

2
Documentation/devicetree/bindings/clock/qcom,videocc.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Video Clock & Reset Controller
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm video clock control module provides the clocks, resets and power

86
Documentation/devicetree/bindings/clock/renesas,5p35023.yaml Normal file
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@ -0,0 +1,86 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,5p35023.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas 5p35023 VersaClock 3 programmable I2C clock generator
maintainers:
- Biju Das <biju.das.jz@bp.renesas.com>
description: |
The 5P35023 is a VersaClock programmable clock generator and
is designed for low-power, consumer, and high-performance PCI
express applications. The 5P35023 device is a three PLL
architecture design, and each PLL is individually programmable
and allowing for up to 6 unique frequency outputs.
An internal OTP memory allows the user to store the configuration
in the device. After power up, the user can change the device register
settings through the I2C interface when I2C mode is selected.
The driver can read a full register map from the DT, and will use that
register map to initialize the attached part (via I2C) when the system
boots. Any configuration not supported by the common clock framework
must be done via the full register map, including optimized settings.
Link to datasheet:
https://www.renesas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3s-programmable-clock-generator
properties:
compatible:
enum:
- renesas,5p35023
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
maxItems: 1
renesas,settings:
description: Optional, complete register map of the device.
Optimized settings for the device must be provided in full
and are written during initialization.
$ref: /schemas/types.yaml#/definitions/uint8-array
maxItems: 37
required:
- compatible
- reg
- '#clock-cells'
- clocks
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
versa3: clock-generator@68 {
compatible = "renesas,5p35023";
reg = <0x68>;
#clock-cells = <1>;
clocks = <&x1_x2>;
renesas,settings = [
80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
80 b0 45 c4 95
];
assigned-clocks = <&versa3 0>, <&versa3 1>,
<&versa3 2>, <&versa3 3>,
<&versa3 4>, <&versa3 5>;
assigned-clock-rates = <12288000>, <25000000>,
<12000000>, <11289600>,
<11289600>, <24000000>;
};
};

87
Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
View File

@ -14,11 +14,16 @@ description: |
reads required input clock frequencies from the devicetree and acts as clock
provider for all clock consumers of PS clocks.
select: false
properties:
compatible:
const: xlnx,versal-clk
oneOf:
- enum:
- xlnx,versal-clk
- xlnx,zynqmp-clk
- items:
- enum:
- xlnx,versal-net-clk
- const: xlnx,versal-clk
"#clock-cells":
const: 1
@ -26,16 +31,12 @@ properties:
clocks:
description: List of clock specifiers which are external input
clocks to the given clock controller.
items:
- description: reference clock
- description: alternate reference clock
- description: alternate reference clock for programmable logic
minItems: 3
maxItems: 8
clock-names:
items:
- const: ref
- const: alt_ref
- const: pl_alt_ref
minItems: 3
maxItems: 8
required:
- compatible
@ -45,6 +46,61 @@ required:
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- xlnx,versal-clk
then:
properties:
clocks:
items:
- description: reference clock
- description: alternate reference clock
- description: alternate reference clock for programmable logic
clock-names:
items:
- const: ref
- const: alt_ref
- const: pl_alt_ref
- if:
properties:
compatible:
contains:
enum:
- xlnx,zynqmp-clk
then:
properties:
clocks:
minItems: 5
items:
- description: PS reference clock
- description: reference clock for video system
- description: alternative PS reference clock
- description: auxiliary reference clock
- description: transceiver reference clock
- description: (E)MIO clock source (Optional clock)
- description: GEM emio clock (Optional clock)
- description: Watchdog external clock (Optional clock)
clock-names:
minItems: 5
items:
- const: pss_ref_clk
- const: video_clk
- const: pss_alt_ref_clk
- const: aux_ref_clk
- const: gt_crx_ref_clk
- pattern: "^mio_clk[00-77]+.*$"
- pattern: "gem[0-3]+_emio_clk.*$"
- pattern: "swdt[0-1]+_ext_clk.*$"
examples:
- |
firmware {
@ -59,4 +115,13 @@ examples:
};
};
};
clock-controller {
#clock-cells = <1>;
compatible = "xlnx,zynqmp-clk";
clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
<&aux_ref_clk>, <&gt_crx_ref_clk>;
clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
"aux_ref_clk", "gt_crx_ref_clk";
};
...

63
Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt
View File

@ -1,63 +0,0 @@
--------------------------------------------------------------------------
Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
Zynq MPSoC firmware interface
--------------------------------------------------------------------------
The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
tree. It reads required input clock frequencies from the devicetree and acts
as clock provider for all clock consumers of PS clocks.
See clock_bindings.txt for more information on the generic clock bindings.
Required properties:
- #clock-cells: Must be 1
- compatible: Must contain: "xlnx,zynqmp-clk"
- clocks: List of clock specifiers which are external input
clocks to the given clock controller. Please refer
the next section to find the input clocks for a
given controller.
- clock-names: List of clock names which are exteral input clocks
to the given clock controller. Please refer to the
clock bindings for more details.
Input clocks for zynqmp Ultrascale+ clock controller:
The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
inputs. These required clock inputs are:
- pss_ref_clk (PS reference clock)
- video_clk (reference clock for video system )
- pss_alt_ref_clk (alternative PS reference clock)
- aux_ref_clk
- gt_crx_ref_clk (transceiver reference clock)
The following strings are optional parameters to the 'clock-names' property in
order to provide an optional (E)MIO clock source:
- swdt0_ext_clk
- swdt1_ext_clk
- gem0_emio_clk
- gem1_emio_clk
- gem2_emio_clk
- gem3_emio_clk
- mio_clk_XX # with XX = 00..77
- mio_clk_50_or_51 #for the mux clock to gem tsu from 50 or 51
Output clocks are registered based on clock information received
from firmware. Output clocks indexes are mentioned in
include/dt-bindings/clock/xlnx-zynqmp-clk.h.
-------
Example
-------
firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
method = "smc";
zynqmp_clk: clock-controller {
#clock-cells = <1>;
compatible = "xlnx,zynqmp-clk";
clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
};
};
};

160
Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml Normal file
View File

@ -0,0 +1,160 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson System Control registers
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
properties:
compatible:
items:
- enum:
- amlogic,meson-gx-hhi-sysctrl
- amlogic,meson-gx-ao-sysctrl
- amlogic,meson-axg-hhi-sysctrl
- amlogic,meson-axg-ao-sysctrl
- const: simple-mfd
- const: syscon
reg:
maxItems: 1
clock-controller:
type: object
power-controller:
$ref: /schemas/power/amlogic,meson-ee-pwrc.yaml
pinctrl:
type: object
phy:
type: object
allOf:
- if:
properties:
compatible:
enum:
- amlogic,meson-gx-hhi-sysctrl
- amlogic,meson-axg-hhi-sysctrl
then:
properties:
clock-controller:
$ref: /schemas/clock/amlogic,gxbb-clkc.yaml#
required:
- power-controller
- if:
properties:
compatible:
enum:
- amlogic,meson-gx-ao-sysctrl
- amlogic,meson-axg-ao-sysctrl
then:
properties:
clock-controller:
$ref: /schemas/clock/amlogic,gxbb-aoclkc.yaml#
power-controller: false
phy: false
- if:
properties:
compatible:
enum:
- amlogic,meson-gx-hhi-sysctrl
then:
properties:
phy: false
- if:
properties:
compatible:
enum:
- amlogic,meson-axg-hhi-sysctrl
then:
properties:
phy:
oneOf:
- $ref: /schemas/phy/amlogic,g12a-mipi-dphy-analog.yaml
- $ref: /schemas/phy/amlogic,meson-axg-mipi-pcie-analog.yaml
required:
- compatible
- reg
- clock-controller
additionalProperties: false
examples:
- |
bus@c883c000 {
compatible = "simple-bus";
reg = <0xc883c000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xc883c000 0x2000>;
sysctrl: system-controller@0 {
compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon";
reg = <0 0x400>;
clock-controller {
compatible = "amlogic,gxbb-clkc";
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "xtal";
};
power-controller {
compatible = "amlogic,meson-gxbb-pwrc";
#power-domain-cells = <1>;
amlogic,ao-sysctrl = <&sysctrl_AO>;
resets = <&reset_viu>,
<&reset_venc>,
<&reset_vcbus>,
<&reset_bt656>,
<&reset_dvin>,
<&reset_rdma>,
<&reset_venci>,
<&reset_vencp>,
<&reset_vdac>,
<&reset_vdi6>,
<&reset_vencl>,
<&reset_vid_lock>;
reset-names = "viu", "venc", "vcbus", "bt656", "dvin",
"rdma", "venci", "vencp", "vdac", "vdi6",
"vencl", "vid_lock";
clocks = <&clk_vpu>, <&clk_vapb>;
clock-names = "vpu", "vapb";
};
};
};
bus@c8100000 {
compatible = "simple-bus";
reg = <0xc8100000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xc8100000 0x100000>;
sysctrl_AO: system-controller@0 {
compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";
reg = <0 0x100>;
clock-controller {
compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&xtal>, <&clk81>;
clock-names = "xtal", "mpeg-clk";
};
};
};

6
MAINTAINERS
View File

@ -20369,6 +20369,12 @@ S: Supported
F: Documentation/devicetree/bindings/mmc/starfive*
F: drivers/mmc/host/dw_mmc-starfive.c
STARFIVE JH7110 PLL CLOCK DRIVER
M: Xingyu Wu <xingyu.wu@starfivetech.com>
S: Supported
F: Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
F: drivers/clk/starfive/clk-starfive-jh7110-pll.c
STARFIVE JH7110 SYSCON
M: William Qiu <william.qiu@starfivetech.com>
M: Xingyu Wu <xingyu.wu@starfivetech.com>

5
drivers/base/core.c
View File

@ -17,7 +17,6 @@
#include <linux/kstrtox.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/kdev_t.h>
#include <linux/notifier.h>
#include <linux/of.h>
@ -28,6 +27,7 @@
#include <linux/netdevice.h>
#include <linux/sched/signal.h>
#include <linux/sched/mm.h>
#include <linux/string_helpers.h>
#include <linux/swiotlb.h>
#include <linux/sysfs.h>
#include <linux/dma-map-ops.h> /* for dma_default_coherent */
@ -3908,10 +3908,9 @@ const char *device_get_devnode(const struct device *dev,
return dev_name(dev);
/* replace '!' in the name with '/' */
s = kstrdup(dev_name(dev), GFP_KERNEL);
s = kstrdup_and_replace(dev_name(dev), '!', '/', GFP_KERNEL);
if (!s)
return NULL;
strreplace(s, '!', '/');
return *tmp = s;
}

16
drivers/clk/Kconfig
View File

@ -360,13 +360,6 @@ config COMMON_CLK_PXA
help
Support for the Marvell PXA SoC.
config COMMON_CLK_OXNAS
bool "Clock driver for the OXNAS SoC Family"
depends on ARCH_OXNAS || COMPILE_TEST
select MFD_SYSCON
help
Support for the OXNAS SoC Family clocks.
config COMMON_CLK_RS9_PCIE
tristate "Clock driver for Renesas 9-series PCIe clock generators"
depends on I2C
@ -385,6 +378,15 @@ config COMMON_CLK_SI521XX
This driver supports the SkyWorks Si521xx PCIe clock generator
models Si52144/Si52146/Si52147.
config COMMON_CLK_VC3
tristate "Clock driver for Renesas VersaClock 3 devices"
depends on I2C
depends on OF
select REGMAP_I2C
help
This driver supports the Renesas VersaClock 3 programmable clock
generators.
config COMMON_CLK_VC5
tristate "Clock driver for IDT VersaClock 5,6 devices"
depends on I2C

2
drivers/clk/Makefile
View File

@ -52,7 +52,6 @@ obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
obj-$(CONFIG_ARCH_NPCM7XX) += clk-npcm7xx.o
obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
obj-$(CONFIG_COMMON_CLK_OXNAS) += clk-oxnas.o
obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o
obj-$(CONFIG_CLK_LS1028A_PLLDIG) += clk-plldig.o
obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
@ -76,6 +75,7 @@ obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_COMMON_CLK_RS9_PCIE) += clk-renesas-pcie.o
obj-$(CONFIG_COMMON_CLK_SI521XX) += clk-si521xx.o
obj-$(CONFIG_COMMON_CLK_VC3) += clk-versaclock3.o
obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o
obj-$(CONFIG_COMMON_CLK_VC7) += clk-versaclock7.o
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o

6
drivers/clk/actions/owl-common.c
View File

@ -8,8 +8,6 @@
// Copyright (c) 2018 Linaro Ltd.
// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
@ -43,10 +41,8 @@ int owl_clk_regmap_init(struct platform_device *pdev,
{
void __iomem *base;
struct regmap *regmap;
struct resource *res;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&pdev->dev, res);
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);

2
drivers/clk/actions/owl-common.h
View File

@ -12,10 +12,10 @@
#define _OWL_COMMON_H_
#include <linux/clk-provider.h>
#include <linux/of_platform.h>
#include <linux/regmap.h>
struct device_node;
struct platform_device;
struct owl_clk_common {
struct regmap *regmap;

5
drivers/clk/axs10x/pll_clock.c
View File

@ -12,10 +12,9 @@
#include <linux/err.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>
/* PLL registers addresses */
#define PLL_REG_IDIV 0x0

1
drivers/clk/baikal-t1/clk-ccu-div.c
View File

@ -20,7 +20,6 @@
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/ioport.h>
#include <linux/regmap.h>

2
drivers/clk/bcm/clk-bcm2835.c
View File

@ -32,7 +32,7 @@
#include <linux/io.h>
#include <linux/math.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <dt-bindings/clock/bcm2835.h>

1
drivers/clk/bcm/clk-bcm63xx-gate.c
View File

@ -3,7 +3,6 @@
#include <linux/clk-provider.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/bcm3368-clock.h>

2
drivers/clk/bcm/clk-sr.c
View File

@ -5,7 +5,7 @@
#include <linux/err.h>
#include <linux/clk-provider.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/bcm-sr.h>

5
drivers/clk/clk-aspeed.c
View File

@ -4,8 +4,8 @@
#define pr_fmt(fmt) "clk-aspeed: " fmt
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
@ -701,6 +701,7 @@ static void __init aspeed_cc_init(struct device_node *np)
GFP_KERNEL);
if (!aspeed_clk_data)
return;
aspeed_clk_data->num = ASPEED_NUM_CLKS;
/*
* This way all clocks fetched before the platform device probes,
@ -732,8 +733,6 @@ static void __init aspeed_cc_init(struct device_node *np)
aspeed_ast2500_cc(map);
else
pr_err("unknown platform, failed to add clocks\n");
aspeed_clk_data->num = ASPEED_NUM_CLKS;
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data);
if (ret)
pr_err("failed to add DT provider: %d\n", ret);

4
drivers/clk/clk-ast2600.c
View File

@ -5,8 +5,8 @@
#define pr_fmt(fmt) "clk-ast2600: " fmt
#include <linux/mfd/syscon.h>
#include <linux/mod_devicetable.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
@ -839,6 +839,7 @@ static void __init aspeed_g6_cc_init(struct device_node *np)
ASPEED_G6_NUM_CLKS), GFP_KERNEL);
if (!aspeed_g6_clk_data)
return;
aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
/*
* This way all clocks fetched before the platform device probes,
@ -860,7 +861,6 @@ static void __init aspeed_g6_cc_init(struct device_node *np)
}
aspeed_g6_cc(map);
aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data);
if (ret)
pr_err("failed to add DT provider: %d\n", ret);

4
drivers/clk/clk-axm5516.c
View File

@ -541,14 +541,12 @@ MODULE_DEVICE_TABLE(of, axmclk_match_table);
static int axmclk_probe(struct platform_device *pdev)
{
void __iomem *base;
struct resource *res;
int i, ret;
struct device *dev = &pdev->dev;
struct regmap *regmap;
size_t num_clks;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(dev, res);
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);

11
drivers/clk/clk-bm1880.c
View File

@ -7,10 +7,10 @@
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
@ -876,16 +876,13 @@ static int bm1880_clk_probe(struct platform_device *pdev)
struct bm1880_clock_data *clk_data;
void __iomem *pll_base, *sys_base;
struct device *dev = &pdev->dev;
struct resource *res;
int num_clks, i;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pll_base = devm_ioremap_resource(&pdev->dev, res);
pll_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pll_base))
return PTR_ERR(pll_base);
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
sys_base = devm_ioremap_resource(&pdev->dev, res);
sys_base = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(sys_base))
return PTR_ERR(sys_base);

2
drivers/clk/clk-cdce925.c
View File

@ -834,7 +834,7 @@ MODULE_DEVICE_TABLE(of, clk_cdce925_of_match);
static struct i2c_driver cdce925_driver = {
.driver = {
.name = "cdce925",
.of_match_table = of_match_ptr(clk_cdce925_of_match),
.of_match_table = clk_cdce925_of_match,
},
.probe = cdce925_probe,
.id_table = cdce925_id,

2
drivers/clk/clk-cs2000-cp.c
View File

@ -9,7 +9,7 @@
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/i2c.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/regmap.h>

3
drivers/clk/clk-en7523.c
View File

@ -2,9 +2,8 @@
#include <linux/delay.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/en7523-clk.h>

4
drivers/clk/clk-fsl-sai.c
View File

@ -33,14 +33,12 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
struct clk_parent_data pdata = { .index = 0 };
void __iomem *base;
struct clk_hw *hw;
struct resource *res;
sai_clk = devm_kzalloc(dev, sizeof(*sai_clk), GFP_KERNEL);
if (!sai_clk)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(dev, res);
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);

6
drivers/clk/clk-gemini.c
View File

@ -276,7 +276,6 @@ static int gemini_clk_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
unsigned int mult, div;
struct resource *res;
u32 val;
int ret;
int i;
@ -286,8 +285,7 @@ static int gemini_clk_probe(struct platform_device *pdev)
return -ENOMEM;
/* Remap the system controller for the exclusive register */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(dev, res);
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
@ -404,6 +402,7 @@ static void __init gemini_cc_init(struct device_node *np)
GFP_KERNEL);
if (!gemini_clk_data)
return;
gemini_clk_data->num = GEMINI_NUM_CLKS;
/*
* This way all clock fetched before the platform device probes,
@ -457,7 +456,6 @@ static void __init gemini_cc_init(struct device_node *np)
gemini_clk_data->hws[GEMINI_CLK_APB] = hw;
/* Register the clocks to be accessed by the device tree */
gemini_clk_data->num = GEMINI_NUM_CLKS;
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, gemini_clk_data);
}
CLK_OF_DECLARE_DRIVER(gemini_cc, "cortina,gemini-syscon", gemini_cc_init);

2
drivers/clk/clk-gpio.c
View File

@ -15,8 +15,8 @@
#include <linux/gpio/consumer.h>
#include <linux/err.h>
#include <linux/device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/of_device.h>
/**
* DOC: basic gpio gated clock which can be enabled and disabled

5
drivers/clk/clk-hsdk-pll.c
View File

@ -12,7 +12,6 @@
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
@ -304,7 +303,6 @@ static const struct clk_ops hsdk_pll_ops = {
static int hsdk_pll_clk_probe(struct platform_device *pdev)
{
int ret;
struct resource *mem;
const char *parent_name;
unsigned int num_parents;
struct hsdk_pll_clk *pll_clk;
@ -315,8 +313,7 @@ static int hsdk_pll_clk_probe(struct platform_device *pdev)
if (!pll_clk)
return -ENOMEM;
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pll_clk->regs = devm_ioremap_resource(dev, mem);
pll_clk->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pll_clk->regs))
return PTR_ERR(pll_clk->regs);

1
drivers/clk/clk-k210.c
View File

@ -11,7 +11,6 @@
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_clk.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/clk-provider.h>
#include <linux/bitfield.h>

35
drivers/clk/clk-lmk04832.c
View File

@ -134,6 +134,11 @@
/* 0x14b - 0x152 Holdover */
/* 0x153 - 0x15f PLL1 Configuration */
#define LMK04832_REG_PLL1_LD 0x15f
#define LMK04832_BIT_PLL1_LD_MUX GENMASK(7, 3)
#define LMK04832_VAL_PLL1_LD_MUX_SPI_RDBK 0x07
#define LMK04832_BIT_PLL1_LD_TYPE GENMASK(2, 0)
#define LMK04832_VAL_PLL1_LD_TYPE_OUT_PP 0x03
/* 0x160 - 0x16e PLL2 Configuration */
#define LMK04832_REG_PLL2_R_MSB 0x160
@ -206,6 +211,7 @@ enum lmk04832_rdbk_type {
RDBK_CLKIN_SEL0,
RDBK_CLKIN_SEL1,
RDBK_RESET,
RDBK_PLL1_LD,
};
struct lmk_dclk {
@ -1297,6 +1303,7 @@ static int lmk04832_register_clkout(struct lmk04832 *lmk, const int num)
sprintf(dclk_name, "lmk-dclk%02d_%02d", num, num + 1);
init.name = dclk_name;
parent_names[0] = clk_hw_get_name(&lmk->vco);
init.parent_names = parent_names;
init.ops = &lmk04832_dclk_ops;
init.flags = CLK_SET_RATE_PARENT;
init.num_parents = 1;
@ -1345,6 +1352,10 @@ static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin)
{
int reg;
int ret;
int val = FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX,
LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) |
FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE,
LMK04832_VAL_CLKIN_SEL_TYPE_OUT);
dev_info(lmk->dev, "setting up 4-wire mode\n");
ret = regmap_write(lmk->regmap, LMK04832_REG_RST3W,
@ -1362,15 +1373,18 @@ static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin)
case RDBK_RESET:
reg = LMK04832_REG_CLKIN_RST;
break;
case RDBK_PLL1_LD:
reg = LMK04832_REG_PLL1_LD;
val = FIELD_PREP(LMK04832_BIT_PLL1_LD_MUX,
LMK04832_VAL_PLL1_LD_MUX_SPI_RDBK) |
FIELD_PREP(LMK04832_BIT_PLL1_LD_TYPE,
LMK04832_VAL_PLL1_LD_TYPE_OUT_PP);
break;
default:
return -EINVAL;
}
return regmap_write(lmk->regmap, reg,
FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX,
LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) |
FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE,
LMK04832_VAL_CLKIN_SEL_TYPE_OUT));
return regmap_write(lmk->regmap, reg, val);
}
static int lmk04832_probe(struct spi_device *spi)
@ -1504,21 +1518,21 @@ static int lmk04832_probe(struct spi_device *spi)
ret = clk_set_rate(lmk->vco.clk, lmk->vco_rate);
if (ret) {
dev_err(lmk->dev, "failed to set VCO rate\n");
goto err_disable_vco;
goto err_disable_oscin;
}
}
ret = lmk04832_register_sclk(lmk);
if (ret) {
dev_err(lmk->dev, "failed to init SYNC/SYSREF clock path\n");
goto err_disable_vco;
goto err_disable_oscin;
}
for (i = 0; i < info->num_channels; i++) {
ret = lmk04832_register_clkout(lmk, i);
if (ret) {
dev_err(lmk->dev, "failed to register clk %d\n", i);
goto err_disable_vco;
goto err_disable_oscin;
}
}
@ -1527,16 +1541,13 @@ static int lmk04832_probe(struct spi_device *spi)
lmk->clk_data);
if (ret) {
dev_err(lmk->dev, "failed to add provider (%d)\n", ret);
goto err_disable_vco;
goto err_disable_oscin;
}
spi_set_drvdata(spi, lmk);
return 0;
err_disable_vco:
clk_disable_unprepare(lmk->vco.clk);
err_disable_oscin:
clk_disable_unprepare(lmk->oscin);

3
drivers/clk/clk-milbeaut.c
View File

@ -618,6 +618,7 @@ static void __init m10v_cc_init(struct device_node *np)
if (!m10v_clk_data)
return;
m10v_clk_data->num = M10V_NUM_CLKS;
base = of_iomap(np, 0);
if (!base) {
@ -654,8 +655,6 @@ static void __init m10v_cc_init(struct device_node *np)
base + CLKSEL(1), 0, 3, 0, rclk_table,
&m10v_crglock, NULL);
m10v_clk_data->hws[M10V_RCLK_ID] = hw;
m10v_clk_data->num = M10V_NUM_CLKS;
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, m10v_clk_data);
}
CLK_OF_DECLARE_DRIVER(m10v_cc, "socionext,milbeaut-m10v-ccu", m10v_cc_init);

251
drivers/clk/clk-oxnas.c
View File

@ -1,251 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2010 Broadcom
* Copyright (C) 2012 Stephen Warren
* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
*/
#include <linux/clk-provider.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/stringify.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <dt-bindings/clock/oxsemi,ox810se.h>
#include <dt-bindings/clock/oxsemi,ox820.h>
/* Standard regmap gate clocks */
struct clk_oxnas_gate {
struct clk_hw hw;
unsigned int bit;
struct regmap *regmap;
};
struct oxnas_stdclk_data {
struct clk_hw_onecell_data *onecell_data;
struct clk_oxnas_gate **gates;
unsigned int ngates;
struct clk_oxnas_pll **plls;
unsigned int nplls;
};
/* Regmap offsets */
#define CLK_STAT_REGOFFSET 0x24
#define CLK_SET_REGOFFSET 0x2c
#define CLK_CLR_REGOFFSET 0x30
static inline struct clk_oxnas_gate *to_clk_oxnas_gate(struct clk_hw *hw)
{
return container_of(hw, struct clk_oxnas_gate, hw);
}
static int oxnas_clk_gate_is_enabled(struct clk_hw *hw)
{
struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
int ret;
unsigned int val;
ret = regmap_read(std->regmap, CLK_STAT_REGOFFSET, &val);
if (ret < 0)
return ret;
return val & BIT(std->bit);
}
static int oxnas_clk_gate_enable(struct clk_hw *hw)
{
struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
regmap_write(std->regmap, CLK_SET_REGOFFSET, BIT(std->bit));
return 0;
}
static void oxnas_clk_gate_disable(struct clk_hw *hw)
{
struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
regmap_write(std->regmap, CLK_CLR_REGOFFSET, BIT(std->bit));
}
static const struct clk_ops oxnas_clk_gate_ops = {
.enable = oxnas_clk_gate_enable,
.disable = oxnas_clk_gate_disable,
.is_enabled = oxnas_clk_gate_is_enabled,
};
static const char *const osc_parents[] = {
"oscillator",
};
static const char *const eth_parents[] = {
"gmacclk",
};
#define OXNAS_GATE(_name, _bit, _parents) \
struct clk_oxnas_gate _name = { \
.bit = (_bit), \
.hw.init = &(struct clk_init_data) { \
.name = #_name, \
.ops = &oxnas_clk_gate_ops, \
.parent_names = _parents, \
.num_parents = ARRAY_SIZE(_parents), \
.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
}, \
}
static OXNAS_GATE(ox810se_leon, 0, osc_parents);
static OXNAS_GATE(ox810se_dma_sgdma, 1, osc_parents);
static OXNAS_GATE(ox810se_cipher, 2, osc_parents);
static OXNAS_GATE(ox810se_sata, 4, osc_parents);
static OXNAS_GATE(ox810se_audio, 5, osc_parents);
static OXNAS_GATE(ox810se_usbmph, 6, osc_parents);
static OXNAS_GATE(ox810se_etha, 7, eth_parents);
static OXNAS_GATE(ox810se_pciea, 8, osc_parents);
static OXNAS_GATE(ox810se_nand, 9, osc_parents);
static struct clk_oxnas_gate *ox810se_gates[] = {
&ox810se_leon,
&ox810se_dma_sgdma,
&ox810se_cipher,
&ox810se_sata,
&ox810se_audio,
&ox810se_usbmph,
&ox810se_etha,
&ox810se_pciea,
&ox810se_nand,
};
static OXNAS_GATE(ox820_leon, 0, osc_parents);
static OXNAS_GATE(ox820_dma_sgdma, 1, osc_parents);
static OXNAS_GATE(ox820_cipher, 2, osc_parents);
static OXNAS_GATE(ox820_sd, 3, osc_parents);
static OXNAS_GATE(ox820_sata, 4, osc_parents);
static OXNAS_GATE(ox820_audio, 5, osc_parents);
static OXNAS_GATE(ox820_usbmph, 6, osc_parents);
static OXNAS_GATE(ox820_etha, 7, eth_parents);
static OXNAS_GATE(ox820_pciea, 8, osc_parents);
static OXNAS_GATE(ox820_nand, 9, osc_parents);
static OXNAS_GATE(ox820_ethb, 10, eth_parents);
static OXNAS_GATE(ox820_pcieb, 11, osc_parents);
static OXNAS_GATE(ox820_ref600, 12, osc_parents);
static OXNAS_GATE(ox820_usbdev, 13, osc_parents);
static struct clk_oxnas_gate *ox820_gates[] = {
&ox820_leon,
&ox820_dma_sgdma,
&ox820_cipher,
&ox820_sd,
&ox820_sata,
&ox820_audio,
&ox820_usbmph,
&ox820_etha,
&ox820_pciea,
&ox820_nand,
&ox820_etha,
&ox820_pciea,
&ox820_ref600,
&ox820_usbdev,
};
static struct clk_hw_onecell_data ox810se_hw_onecell_data = {
.hws = {
[CLK_810_LEON] = &ox810se_leon.hw,
[CLK_810_DMA_SGDMA] = &ox810se_dma_sgdma.hw,
[CLK_810_CIPHER] = &ox810se_cipher.hw,
[CLK_810_SATA] = &ox810se_sata.hw,
[CLK_810_AUDIO] = &ox810se_audio.hw,
[CLK_810_USBMPH] = &ox810se_usbmph.hw,
[CLK_810_ETHA] = &ox810se_etha.hw,
[CLK_810_PCIEA] = &ox810se_pciea.hw,
[CLK_810_NAND] = &ox810se_nand.hw,
},
.num = ARRAY_SIZE(ox810se_gates),
};
static struct clk_hw_onecell_data ox820_hw_onecell_data = {
.hws = {
[CLK_820_LEON] = &ox820_leon.hw,
[CLK_820_DMA_SGDMA] = &ox820_dma_sgdma.hw,
[CLK_820_CIPHER] = &ox820_cipher.hw,
[CLK_820_SD] = &ox820_sd.hw,
[CLK_820_SATA] = &ox820_sata.hw,
[CLK_820_AUDIO] = &ox820_audio.hw,
[CLK_820_USBMPH] = &ox820_usbmph.hw,
[CLK_820_ETHA] = &ox820_etha.hw,
[CLK_820_PCIEA] = &ox820_pciea.hw,
[CLK_820_NAND] = &ox820_nand.hw,
[CLK_820_ETHB] = &ox820_ethb.hw,
[CLK_820_PCIEB] = &ox820_pcieb.hw,
[CLK_820_REF600] = &ox820_ref600.hw,
[CLK_820_USBDEV] = &ox820_usbdev.hw,
},
.num = ARRAY_SIZE(ox820_gates),
};
static struct oxnas_stdclk_data ox810se_stdclk_data = {
.onecell_data = &ox810se_hw_onecell_data,
.gates = ox810se_gates,
.ngates = ARRAY_SIZE(ox810se_gates),
};
static struct oxnas_stdclk_data ox820_stdclk_data = {
.onecell_data = &ox820_hw_onecell_data,
.gates = ox820_gates,
.ngates = ARRAY_SIZE(ox820_gates),
};
static const struct of_device_id oxnas_stdclk_dt_ids[] = {
{ .compatible = "oxsemi,ox810se-stdclk", &ox810se_stdclk_data },
{ .compatible = "oxsemi,ox820-stdclk", &ox820_stdclk_data },
{ }
};
static int oxnas_stdclk_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node, *parent_np;
const struct oxnas_stdclk_data *data;
struct regmap *regmap;
int ret;
int i;
data = of_device_get_match_data(&pdev->dev);
parent_np = of_get_parent(np);
regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap)) {
dev_err(&pdev->dev, "failed to have parent regmap\n");
return PTR_ERR(regmap);
}
for (i = 0 ; i < data->ngates ; ++i)
data->gates[i]->regmap = regmap;
for (i = 0; i < data->onecell_data->num; i++) {
if (!data->onecell_data->hws[i])
continue;
ret = devm_clk_hw_register(&pdev->dev,
data->onecell_data->hws[i]);
if (ret)
return ret;
}
return of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
data->onecell_data);
}
static struct platform_driver oxnas_stdclk_driver = {
.probe = oxnas_stdclk_probe,
.driver = {
.name = "oxnas-stdclk",
.suppress_bind_attrs = true,
.of_match_table = oxnas_stdclk_dt_ids,
},
};
builtin_platform_driver(oxnas_stdclk_driver);

1
drivers/clk/clk-palmas.c
View File

@ -14,7 +14,6 @@
#include <linux/mfd/palmas.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

2
drivers/clk/clk-plldig.c
View File

@ -12,8 +12,6 @@
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/bitfield.h>

2
drivers/clk/clk-qoriq.c
View File

@ -17,8 +17,8 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#define PLL_DIV1 0

1
drivers/clk/clk-scpi.c
View File

@ -10,7 +10,6 @@
#include <linux/err.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/scpi_protocol.h>

2
drivers/clk/clk-si5351.c
View File

@ -21,7 +21,7 @@
#include <linux/errno.h>
#include <linux/rational.h>
#include <linux/i2c.h>
#include <linux/of_platform.h>
#include <linux/of.h>
#include <linux/platform_data/si5351.h>
#include <linux/regmap.h>
#include <linux/slab.h>

3
drivers/clk/clk-sp7021.c
View File

@ -621,6 +621,7 @@ static int sp7021_clk_probe(struct platform_device *pdev)
GFP_KERNEL);
if (!clk_data)
return -ENOMEM;
clk_data->num = CLK_MAX;
hws = clk_data->hws;
pd_ext.index = 0;
@ -688,8 +689,6 @@ static int sp7021_clk_probe(struct platform_device *pdev)
return PTR_ERR(hws[i]);
}
clk_data->num = CLK_MAX;
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
}

1143
drivers/clk/clk-versaclock3.c Normal file
View File

File diff suppressed because it is too large Load Diff

3
drivers/clk/clk-versaclock5.c
View File

@ -19,7 +19,6 @@
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/slab.h>
@ -956,7 +955,7 @@ static int vc5_probe(struct i2c_client *client)
i2c_set_clientdata(client, vc5);
vc5->client = client;
vc5->chip_info = device_get_match_data(&client->dev);
vc5->chip_info = i2c_get_match_data(client);
vc5->pin_xin = devm_clk_get(&client->dev, "xin");
if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)

3
drivers/clk/clk-versaclock7.c
View File

@ -14,7 +14,6 @@
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/swab.h>
@ -1109,7 +1108,7 @@ static int vc7_probe(struct i2c_client *client)
i2c_set_clientdata(client, vc7);
vc7->client = client;
vc7->chip_info = device_get_match_data(&client->dev);
vc7->chip_info = i2c_get_match_data(client);
vc7->pin_xin = devm_clk_get(&client->dev, "xin");
if (PTR_ERR(vc7->pin_xin) == -EPROBE_DEFER) {

2
drivers/clk/hisilicon/clk-hi3559a.c
View File

@ -9,7 +9,7 @@
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

1
drivers/clk/hisilicon/clk-hi3620.c
View File

@ -14,7 +14,6 @@
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/slab.h>
#include <dt-bindings/clock/hi3620-clock.h>

2
drivers/clk/hisilicon/clk-hi3660.c
View File

@ -6,7 +6,7 @@
#include <dt-bindings/clock/hi3660-clock.h>
#include <linux/clk-provider.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "clk.h"

2
drivers/clk/hisilicon/clk-hi3670.c
View File

@ -9,7 +9,7 @@
#include <dt-bindings/clock/hi3670-clock.h>
#include <linux/clk-provider.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "clk.h"

2
drivers/clk/hisilicon/clk-hi6220-stub.c
View File

@ -14,7 +14,7 @@
#include <linux/mfd/syscon.h>
#include <linux/mailbox_client.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
/* Stub clocks id */

3
drivers/clk/hisilicon/clk-hi6220.c
View File

@ -11,9 +11,6 @@
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/slab.h>
#include <dt-bindings/clock/hi6220-clock.h>

3
drivers/clk/hisilicon/clk-hip04.c
View File

@ -11,9 +11,6 @@
#include <linux/kernel.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/slab.h>
#include <dt-bindings/clock/hip04-clock.h>

2
drivers/clk/hisilicon/clk.c
View File

@ -16,7 +16,7 @@
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "clk.h"

2
drivers/clk/hisilicon/crg-hi3516cv300.c
View File

@ -8,7 +8,7 @@
#include <dt-bindings/clock/hi3516cv300-clock.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "clk.h"
#include "crg.h"

2
drivers/clk/hisilicon/crg-hi3798cv200.c
View File

@ -8,7 +8,7 @@
#include <dt-bindings/clock/histb-clock.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "clk.h"
#include "crg.h"

3
drivers/clk/imx/Makefile
View File

@ -32,11 +32,12 @@ obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
obj-$(CONFIG_CLK_IMX93) += clk-imx93.o
obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o
obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o clk-imx-acm.o
clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \
clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o \
clk-imx8dxl-rsrc.o
clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o
clk-imx-acm-$(CONFIG_CLK_IMX8QXP) = clk-imx8-acm.o
obj-$(CONFIG_CLK_IMX8ULP) += clk-imx8ulp.o

12
drivers/clk/imx/clk-composite-8m.c
View File

@ -97,7 +97,7 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
int prediv_value;
int div_value;
int ret;
u32 val;
u32 orig, val;
ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,
&prediv_value, &div_value);
@ -106,13 +106,15 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
spin_lock_irqsave(divider->lock, flags);
val = readl(divider->reg);
val &= ~((clk_div_mask(divider->width) << divider->shift) |
(clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
orig = readl(divider->reg);
val = orig & ~((clk_div_mask(divider->width) << divider->shift) |
(clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
val |= (u32)(prediv_value - 1) << divider->shift;
val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
writel(val, divider->reg);
if (val != orig)
writel(val, divider->reg);
spin_unlock_irqrestore(divider->lock, flags);

1
drivers/clk/imx/clk-fracn-gppll.c
View File

@ -81,6 +81,7 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6),
PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8),
PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),

8
drivers/clk/imx/clk-gpr-mux.c
View File

@ -65,16 +65,10 @@ static int imx_clk_gpr_mux_set_parent(struct clk_hw *hw, u8 index)
return regmap_update_bits(priv->regmap, priv->reg, priv->mask, val);
}
static int imx_clk_gpr_mux_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
return clk_mux_determine_rate_flags(hw, req, 0);
}
static const struct clk_ops imx_clk_gpr_mux_ops = {
.get_parent = imx_clk_gpr_mux_get_parent,
.set_parent = imx_clk_gpr_mux_set_parent,
.determine_rate = imx_clk_gpr_mux_determine_rate,
.determine_rate = __clk_mux_determine_rate,
};
struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible,

5
drivers/clk/imx/clk-imx25.c
View File

@ -13,6 +13,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <soc/imx/revision.h>
#include "clk.h"
@ -73,7 +74,7 @@ enum mx25_clks {
static struct clk *clk[clk_max];
static int __init __mx25_clocks_init(void __iomem *ccm_base)
static void __init __mx25_clocks_init(void __iomem *ccm_base)
{
BUG_ON(!ccm_base);
@ -220,7 +221,7 @@ static int __init __mx25_clocks_init(void __iomem *ccm_base)
imx_register_uart_clocks();
return 0;
imx_print_silicon_rev("i.MX25", mx25_revision());
}
static void __init mx25_clocks_init_dt(struct device_node *np)

476
drivers/clk/imx/clk-imx8-acm.c Normal file
View File

@ -0,0 +1,476 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2023 NXP
//
#include <dt-bindings/clock/imx8-clock.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include "clk.h"
/**
* struct clk_imx_acm_pm_domains - structure for multi power domain
* @pd_dev: power domain device
* @pd_dev_link: power domain device link
* @num_domains: power domain nummber
*/
struct clk_imx_acm_pm_domains {
struct device **pd_dev;
struct device_link **pd_dev_link;
int num_domains;
};
/**
* struct clk_imx8_acm_sel - for clock mux
* @name: clock name
* @clkid: clock id
* @parents: clock parents
* @num_parents: clock parents number
* @reg: register offset
* @shift: bit shift in register
* @width: bits width
*/
struct clk_imx8_acm_sel {
const char *name;
int clkid;
const struct clk_parent_data *parents; /* For mux */
int num_parents;
u32 reg;
u8 shift;
u8 width;
};
/**
* struct imx8_acm_soc_data - soc specific data
* @sels: pointer to struct clk_imx8_acm_sel
* @num_sels: numbers of items
*/
struct imx8_acm_soc_data {
struct clk_imx8_acm_sel *sels;
unsigned int num_sels;
};
/**
* struct imx8_acm_priv - private structure
* @dev_pm: multi power domain
* @soc_data: pointer to soc data
* @reg: base address of registers
* @regs: save registers for suspend
*/
struct imx8_acm_priv {
struct clk_imx_acm_pm_domains dev_pm;
const struct imx8_acm_soc_data *soc_data;
void __iomem *reg;
u32 regs[IMX_ADMA_ACM_CLK_END];
};
static const struct clk_parent_data imx8qm_aud_clk_sels[] = {
{ .fw_name = "aud_rec_clk0_lpcg_clk" },
{ .fw_name = "aud_rec_clk1_lpcg_clk" },
{ .fw_name = "mlb_clk" },
{ .fw_name = "hdmi_rx_mclk" },
{ .fw_name = "ext_aud_mclk0" },
{ .fw_name = "ext_aud_mclk1" },
{ .fw_name = "esai0_rx_clk" },
{ .fw_name = "esai0_rx_hf_clk" },
{ .fw_name = "esai0_tx_clk" },
{ .fw_name = "esai0_tx_hf_clk" },
{ .fw_name = "esai1_rx_clk" },
{ .fw_name = "esai1_rx_hf_clk" },
{ .fw_name = "esai1_tx_clk" },
{ .fw_name = "esai1_tx_hf_clk" },
{ .fw_name = "spdif0_rx" },
{ .fw_name = "spdif1_rx" },
{ .fw_name = "sai0_rx_bclk" },
{ .fw_name = "sai0_tx_bclk" },
{ .fw_name = "sai1_rx_bclk" },
{ .fw_name = "sai1_tx_bclk" },
{ .fw_name = "sai2_rx_bclk" },
{ .fw_name = "sai3_rx_bclk" },
{ .fw_name = "sai4_rx_bclk" },
};
static const struct clk_parent_data imx8qm_mclk_out_sels[] = {
{ .fw_name = "aud_rec_clk0_lpcg_clk" },
{ .fw_name = "aud_rec_clk1_lpcg_clk" },
{ .fw_name = "mlb_clk" },
{ .fw_name = "hdmi_rx_mclk" },
{ .fw_name = "spdif0_rx" },
{ .fw_name = "spdif1_rx" },
{ .fw_name = "sai4_rx_bclk" },
{ .fw_name = "sai6_rx_bclk" },
};
static const struct clk_parent_data imx8qm_mclk_sels[] = {
{ .fw_name = "aud_pll_div_clk0_lpcg_clk" },
{ .fw_name = "aud_pll_div_clk1_lpcg_clk" },
{ .fw_name = "acm_aud_clk0_sel" },
{ .fw_name = "acm_aud_clk1_sel" },
};
static const struct clk_parent_data imx8qm_asrc_mux_clk_sels[] = {
{ .fw_name = "sai4_rx_bclk" },
{ .fw_name = "sai5_tx_bclk" },
{ .index = -1 },
{ .fw_name = "mlb_clk" },
};
static struct clk_imx8_acm_sel imx8qm_sels[] = {
{ "acm_aud_clk0_sel", IMX_ADMA_ACM_AUD_CLK0_SEL, imx8qm_aud_clk_sels, ARRAY_SIZE(imx8qm_aud_clk_sels), 0x000000, 0, 5 },
{ "acm_aud_clk1_sel", IMX_ADMA_ACM_AUD_CLK1_SEL, imx8qm_aud_clk_sels, ARRAY_SIZE(imx8qm_aud_clk_sels), 0x010000, 0, 5 },
{ "acm_mclkout0_sel", IMX_ADMA_ACM_MCLKOUT0_SEL, imx8qm_mclk_out_sels, ARRAY_SIZE(imx8qm_mclk_out_sels), 0x020000, 0, 3 },
{ "acm_mclkout1_sel", IMX_ADMA_ACM_MCLKOUT1_SEL, imx8qm_mclk_out_sels, ARRAY_SIZE(imx8qm_mclk_out_sels), 0x030000, 0, 3 },
{ "acm_asrc0_mclk_sel", IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL, imx8qm_asrc_mux_clk_sels, ARRAY_SIZE(imx8qm_asrc_mux_clk_sels), 0x040000, 0, 2 },
{ "acm_esai0_mclk_sel", IMX_ADMA_ACM_ESAI0_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x060000, 0, 2 },
{ "acm_esai1_mclk_sel", IMX_ADMA_ACM_ESAI1_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x070000, 0, 2 },
{ "acm_sai0_mclk_sel", IMX_ADMA_ACM_SAI0_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x0E0000, 0, 2 },
{ "acm_sai1_mclk_sel", IMX_ADMA_ACM_SAI1_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x0F0000, 0, 2 },
{ "acm_sai2_mclk_sel", IMX_ADMA_ACM_SAI2_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x100000, 0, 2 },
{ "acm_sai3_mclk_sel", IMX_ADMA_ACM_SAI3_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x110000, 0, 2 },
{ "acm_sai4_mclk_sel", IMX_ADMA_ACM_SAI4_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x120000, 0, 2 },
{ "acm_sai5_mclk_sel", IMX_ADMA_ACM_SAI5_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x130000, 0, 2 },
{ "acm_sai6_mclk_sel", IMX_ADMA_ACM_SAI6_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x140000, 0, 2 },
{ "acm_sai7_mclk_sel", IMX_ADMA_ACM_SAI7_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x150000, 0, 2 },
{ "acm_spdif0_mclk_sel", IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x1A0000, 0, 2 },
{ "acm_spdif1_mclk_sel", IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x1B0000, 0, 2 },
{ "acm_mqs_mclk_sel", IMX_ADMA_ACM_MQS_TX_CLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x1C0000, 0, 2 },
};
static const struct clk_parent_data imx8qxp_aud_clk_sels[] = {
{ .fw_name = "aud_rec_clk0_lpcg_clk" },
{ .fw_name = "aud_rec_clk1_lpcg_clk" },
{ .fw_name = "ext_aud_mclk0" },
{ .fw_name = "ext_aud_mclk1" },
{ .fw_name = "esai0_rx_clk" },
{ .fw_name = "esai0_rx_hf_clk" },
{ .fw_name = "esai0_tx_clk" },
{ .fw_name = "esai0_tx_hf_clk" },
{ .fw_name = "spdif0_rx" },
{ .fw_name = "sai0_rx_bclk" },
{ .fw_name = "sai0_tx_bclk" },
{ .fw_name = "sai1_rx_bclk" },
{ .fw_name = "sai1_tx_bclk" },
{ .fw_name = "sai2_rx_bclk" },
{ .fw_name = "sai3_rx_bclk" },
};
static const struct clk_parent_data imx8qxp_mclk_out_sels[] = {
{ .fw_name = "aud_rec_clk0_lpcg_clk" },
{ .fw_name = "aud_rec_clk1_lpcg_clk" },
{ .index = -1 },
{ .index = -1 },
{ .fw_name = "spdif0_rx" },
{ .index = -1 },
{ .index = -1 },
{ .fw_name = "sai4_rx_bclk" },
};
static const struct clk_parent_data imx8qxp_mclk_sels[] = {
{ .fw_name = "aud_pll_div_clk0_lpcg_clk" },
{ .fw_name = "aud_pll_div_clk1_lpcg_clk" },
{ .fw_name = "acm_aud_clk0_sel" },
{ .fw_name = "acm_aud_clk1_sel" },
};
static struct clk_imx8_acm_sel imx8qxp_sels[] = {
{ "acm_aud_clk0_sel", IMX_ADMA_ACM_AUD_CLK0_SEL, imx8qxp_aud_clk_sels, ARRAY_SIZE(imx8qxp_aud_clk_sels), 0x000000, 0, 5 },
{ "acm_aud_clk1_sel", IMX_ADMA_ACM_AUD_CLK1_SEL, imx8qxp_aud_clk_sels, ARRAY_SIZE(imx8qxp_aud_clk_sels), 0x010000, 0, 5 },
{ "acm_mclkout0_sel", IMX_ADMA_ACM_MCLKOUT0_SEL, imx8qxp_mclk_out_sels, ARRAY_SIZE(imx8qxp_mclk_out_sels), 0x020000, 0, 3 },
{ "acm_mclkout1_sel", IMX_ADMA_ACM_MCLKOUT1_SEL, imx8qxp_mclk_out_sels, ARRAY_SIZE(imx8qxp_mclk_out_sels), 0x030000, 0, 3 },
{ "acm_esai0_mclk_sel", IMX_ADMA_ACM_ESAI0_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x060000, 0, 2 },
{ "acm_sai0_mclk_sel", IMX_ADMA_ACM_SAI0_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x0E0000, 0, 2 },
{ "acm_sai1_mclk_sel", IMX_ADMA_ACM_SAI1_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x0F0000, 0, 2 },
{ "acm_sai2_mclk_sel", IMX_ADMA_ACM_SAI2_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x100000, 0, 2 },
{ "acm_sai3_mclk_sel", IMX_ADMA_ACM_SAI3_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x110000, 0, 2 },
{ "acm_sai4_mclk_sel", IMX_ADMA_ACM_SAI4_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x140000, 0, 2 },
{ "acm_sai5_mclk_sel", IMX_ADMA_ACM_SAI5_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x150000, 0, 2 },
{ "acm_spdif0_mclk_sel", IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x1A0000, 0, 2 },
{ "acm_mqs_mclk_sel", IMX_ADMA_ACM_MQS_TX_CLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x1C0000, 0, 2 },
};
static const struct clk_parent_data imx8dxl_aud_clk_sels[] = {
{ .fw_name = "aud_rec_clk0_lpcg_clk" },
{ .fw_name = "aud_rec_clk1_lpcg_clk" },
{ .fw_name = "ext_aud_mclk0" },
{ .fw_name = "ext_aud_mclk1" },
{ .index = -1 },
{ .index = -1 },
{ .index = -1 },
{ .index = -1 },
{ .fw_name = "spdif0_rx" },
{ .fw_name = "sai0_rx_bclk" },
{ .fw_name = "sai0_tx_bclk" },
{ .fw_name = "sai1_rx_bclk" },
{ .fw_name = "sai1_tx_bclk" },
{ .fw_name = "sai2_rx_bclk" },
{ .fw_name = "sai3_rx_bclk" },
};
static const struct clk_parent_data imx8dxl_mclk_out_sels[] = {
{ .fw_name = "aud_rec_clk0_lpcg_clk" },
{ .fw_name = "aud_rec_clk1_lpcg_clk" },
{ .index = -1 },
{ .index = -1 },
{ .fw_name = "spdif0_rx" },
{ .index = -1 },
{ .index = -1 },
{ .index = -1 },
};
static const struct clk_parent_data imx8dxl_mclk_sels[] = {
{ .fw_name = "aud_pll_div_clk0_lpcg_clk" },
{ .fw_name = "aud_pll_div_clk1_lpcg_clk" },
{ .fw_name = "acm_aud_clk0_sel" },
{ .fw_name = "acm_aud_clk1_sel" },
};
static struct clk_imx8_acm_sel imx8dxl_sels[] = {
{ "acm_aud_clk0_sel", IMX_ADMA_ACM_AUD_CLK0_SEL, imx8dxl_aud_clk_sels, ARRAY_SIZE(imx8dxl_aud_clk_sels), 0x000000, 0, 5 },
{ "acm_aud_clk1_sel", IMX_ADMA_ACM_AUD_CLK1_SEL, imx8dxl_aud_clk_sels, ARRAY_SIZE(imx8dxl_aud_clk_sels), 0x010000, 0, 5 },
{ "acm_mclkout0_sel", IMX_ADMA_ACM_MCLKOUT0_SEL, imx8dxl_mclk_out_sels, ARRAY_SIZE(imx8dxl_mclk_out_sels), 0x020000, 0, 3 },
{ "acm_mclkout1_sel", IMX_ADMA_ACM_MCLKOUT1_SEL, imx8dxl_mclk_out_sels, ARRAY_SIZE(imx8dxl_mclk_out_sels), 0x030000, 0, 3 },
{ "acm_sai0_mclk_sel", IMX_ADMA_ACM_SAI0_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x0E0000, 0, 2 },
{ "acm_sai1_mclk_sel", IMX_ADMA_ACM_SAI1_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x0F0000, 0, 2 },
{ "acm_sai2_mclk_sel", IMX_ADMA_ACM_SAI2_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x100000, 0, 2 },
{ "acm_sai3_mclk_sel", IMX_ADMA_ACM_SAI3_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x110000, 0, 2 },
{ "acm_spdif0_mclk_sel", IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x1A0000, 0, 2 },
{ "acm_mqs_mclk_sel", IMX_ADMA_ACM_MQS_TX_CLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x1C0000, 0, 2 },
};
/**
* clk_imx_acm_attach_pm_domains: attach multi power domains
* @dev: device pointer
* @dev_pm: power domains for device
*/
static int clk_imx_acm_attach_pm_domains(struct device *dev,
struct clk_imx_acm_pm_domains *dev_pm)
{
int ret;
int i;
dev_pm->num_domains = of_count_phandle_with_args(dev->of_node, "power-domains",
"#power-domain-cells");
if (dev_pm->num_domains <= 1)
return 0;
dev_pm->pd_dev = devm_kmalloc_array(dev, dev_pm->num_domains,
sizeof(*dev_pm->pd_dev),
GFP_KERNEL);
if (!dev_pm->pd_dev)
return -ENOMEM;
dev_pm->pd_dev_link = devm_kmalloc_array(dev,
dev_pm->num_domains,
sizeof(*dev_pm->pd_dev_link),
GFP_KERNEL);
if (!dev_pm->pd_dev_link)
return -ENOMEM;
for (i = 0; i < dev_pm->num_domains; i++) {
dev_pm->pd_dev[i] = dev_pm_domain_attach_by_id(dev, i);
if (IS_ERR(dev_pm->pd_dev[i]))
return PTR_ERR(dev_pm->pd_dev[i]);
dev_pm->pd_dev_link[i] = device_link_add(dev,
dev_pm->pd_dev[i],
DL_FLAG_STATELESS |
DL_FLAG_PM_RUNTIME |
DL_FLAG_RPM_ACTIVE);
if (IS_ERR(dev_pm->pd_dev_link[i])) {
dev_pm_domain_detach(dev_pm->pd_dev[i], false);
ret = PTR_ERR(dev_pm->pd_dev_link[i]);
goto detach_pm;
}
}
return 0;
detach_pm:
while (--i >= 0) {
device_link_del(dev_pm->pd_dev_link[i]);
dev_pm_domain_detach(dev_pm->pd_dev[i], false);
}
return ret;
}
/**
* clk_imx_acm_detach_pm_domains: detach multi power domains
* @dev: deivice pointer
* @dev_pm: multi power domain for device
*/
static int clk_imx_acm_detach_pm_domains(struct device *dev,
struct clk_imx_acm_pm_domains *dev_pm)
{
int i;
if (dev_pm->num_domains <= 1)
return 0;
for (i = 0; i < dev_pm->num_domains; i++) {
device_link_del(dev_pm->pd_dev_link[i]);
dev_pm_domain_detach(dev_pm->pd_dev[i], false);
}
return 0;
}
static int imx8_acm_clk_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_hw_data;
struct device *dev = &pdev->dev;
struct clk_imx8_acm_sel *sels;
struct imx8_acm_priv *priv;
struct clk_hw **hws;
void __iomem *base;
int ret;
int i;
base = devm_of_iomap(dev, dev->of_node, 0, NULL);
if (WARN_ON(IS_ERR(base)))
return PTR_ERR(base);
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->reg = base;
priv->soc_data = of_device_get_match_data(dev);
platform_set_drvdata(pdev, priv);
clk_hw_data = devm_kzalloc(&pdev->dev, struct_size(clk_hw_data, hws, IMX_ADMA_ACM_CLK_END),
GFP_KERNEL);
if (!clk_hw_data)
return -ENOMEM;
clk_hw_data->num = IMX_ADMA_ACM_CLK_END;
hws = clk_hw_data->hws;
ret = clk_imx_acm_attach_pm_domains(&pdev->dev, &priv->dev_pm);
if (ret)
return ret;
pm_runtime_enable(&pdev->dev);
pm_runtime_get_sync(&pdev->dev);
sels = priv->soc_data->sels;
for (i = 0; i < priv->soc_data->num_sels; i++) {
hws[sels[i].clkid] = devm_clk_hw_register_mux_parent_data_table(dev,
sels[i].name, sels[i].parents,
sels[i].num_parents, 0,
base + sels[i].reg,
sels[i].shift, sels[i].width,
0, NULL, NULL);
if (IS_ERR(hws[sels[i].clkid])) {
pm_runtime_disable(&pdev->dev);
goto err_clk_register;
}
}
imx_check_clk_hws(hws, IMX_ADMA_ACM_CLK_END);
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_hw_data);
if (ret < 0) {
dev_err(dev, "failed to register hws for ACM\n");
pm_runtime_disable(&pdev->dev);
}
err_clk_register:
pm_runtime_put_sync(&pdev->dev);
return ret;
}
static int imx8_acm_clk_remove(struct platform_device *pdev)
{
struct imx8_acm_priv *priv = dev_get_drvdata(&pdev->dev);
pm_runtime_disable(&pdev->dev);
clk_imx_acm_detach_pm_domains(&pdev->dev, &priv->dev_pm);
return 0;
}
static const struct imx8_acm_soc_data imx8qm_acm_data = {
.sels = imx8qm_sels,
.num_sels = ARRAY_SIZE(imx8qm_sels),
};
static const struct imx8_acm_soc_data imx8qxp_acm_data = {
.sels = imx8qxp_sels,
.num_sels = ARRAY_SIZE(imx8qxp_sels),
};
static const struct imx8_acm_soc_data imx8dxl_acm_data = {
.sels = imx8dxl_sels,
.num_sels = ARRAY_SIZE(imx8dxl_sels),
};
static const struct of_device_id imx8_acm_match[] = {
{ .compatible = "fsl,imx8qm-acm", .data = &imx8qm_acm_data },
{ .compatible = "fsl,imx8qxp-acm", .data = &imx8qxp_acm_data },
{ .compatible = "fsl,imx8dxl-acm", .data = &imx8dxl_acm_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx8_acm_match);
static int __maybe_unused imx8_acm_runtime_suspend(struct device *dev)
{
struct imx8_acm_priv *priv = dev_get_drvdata(dev);
struct clk_imx8_acm_sel *sels;
int i;
sels = priv->soc_data->sels;
for (i = 0; i < priv->soc_data->num_sels; i++)
priv->regs[i] = readl_relaxed(priv->reg + sels[i].reg);
return 0;
}
static int __maybe_unused imx8_acm_runtime_resume(struct device *dev)
{
struct imx8_acm_priv *priv = dev_get_drvdata(dev);
struct clk_imx8_acm_sel *sels;
int i;
sels = priv->soc_data->sels;
for (i = 0; i < priv->soc_data->num_sels; i++)
writel_relaxed(priv->regs[i], priv->reg + sels[i].reg);
return 0;
}
static const struct dev_pm_ops imx8_acm_pm_ops = {
SET_RUNTIME_PM_OPS(imx8_acm_runtime_suspend,
imx8_acm_runtime_resume, NULL)
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver imx8_acm_clk_driver = {
.driver = {
.name = "imx8-acm",
.of_match_table = imx8_acm_match,
.pm = &imx8_acm_pm_ops,
},
.probe = imx8_acm_clk_probe,
.remove = imx8_acm_clk_remove,
};
module_platform_driver(imx8_acm_clk_driver);
MODULE_AUTHOR("Shengjiu Wang <shengjiu.wang@nxp.com>");
MODULE_DESCRIPTION("Freescale i.MX8 Audio Clock Mux driver");
MODULE_LICENSE("GPL");

5
drivers/clk/imx/clk-imx8mp.c
View File

@ -178,10 +178,6 @@ static const char * const imx8mp_sai3_sels[] = {"osc_24m", "audio_pll1_out", "au
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
"clk_ext3", "clk_ext4", };
static const char * const imx8mp_sai4_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
"clk_ext1", "clk_ext2", };
static const char * const imx8mp_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
"clk_ext2", "clk_ext3", };
@ -567,7 +563,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_CLK_SAI1] = imx8m_clk_hw_composite("sai1", imx8mp_sai1_sels, ccm_base + 0xa580);
hws[IMX8MP_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mp_sai2_sels, ccm_base + 0xa600);
hws[IMX8MP_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mp_sai3_sels, ccm_base + 0xa680);
hws[IMX8MP_CLK_SAI4] = imx8m_clk_hw_composite("sai4", imx8mp_sai4_sels, ccm_base + 0xa700);
hws[IMX8MP_CLK_SAI5] = imx8m_clk_hw_composite("sai5", imx8mp_sai5_sels, ccm_base + 0xa780);
hws[IMX8MP_CLK_SAI6] = imx8m_clk_hw_composite("sai6", imx8mp_sai6_sels, ccm_base + 0xa800);
hws[IMX8MP_CLK_ENET_QOS] = imx8m_clk_hw_composite("enet_qos", imx8mp_enet_qos_sels, ccm_base + 0xa880);

6
drivers/clk/imx/clk-imx8qxp-lpcg.c
View File

@ -9,8 +9,6 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
@ -183,7 +181,6 @@ static int imx_lpcg_parse_clks_from_dt(struct platform_device *pdev,
unsigned int bit_offset[IMX_LPCG_MAX_CLKS];
struct clk_hw_onecell_data *clk_data;
struct clk_hw **clk_hws;
struct resource *res;
void __iomem *base;
int count;
int idx;
@ -193,8 +190,7 @@ static int imx_lpcg_parse_clks_from_dt(struct platform_device *pdev,
if (!of_device_is_compatible(np, "fsl,imx8qxp-lpcg"))
return -EINVAL;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&pdev->dev, res);
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);

1
drivers/clk/imx/clk-imx8qxp.c
View File

@ -9,7 +9,6 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

4
drivers/clk/imx/clk-imx8ulp.c
View File

@ -7,7 +7,7 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
@ -167,7 +167,7 @@ static int imx8ulp_clk_cgc1_init(struct platform_device *pdev)
clks[IMX8ULP_CLK_SPLL2_PRE_SEL] = imx_clk_hw_mux_flags("spll2_pre_sel", base + 0x510, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
clks[IMX8ULP_CLK_SPLL3_PRE_SEL] = imx_clk_hw_mux_flags("spll3_pre_sel", base + 0x610, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
clks[IMX8ULP_CLK_SPLL2] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP, "spll2", "spll2_pre_sel", base + 0x500);
clks[IMX8ULP_CLK_SPLL2] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP_1GHZ, "spll2", "spll2_pre_sel", base + 0x500);
clks[IMX8ULP_CLK_SPLL3] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP, "spll3", "spll3_pre_sel", base + 0x600);
clks[IMX8ULP_CLK_SPLL3_VCODIV] = imx_clk_hw_divider("spll3_vcodiv", "spll3", base + 0x604, 0, 6);

4
drivers/clk/imx/clk-imx93.c
View File

@ -32,6 +32,7 @@ static u32 share_count_sai1;
static u32 share_count_sai2;
static u32 share_count_sai3;
static u32 share_count_mub;
static u32 share_count_pdm;
static const char * const a55_core_sels[] = {"a55_alt", "arm_pll"};
static const char *parent_names[MAX_SEL][4] = {
@ -236,7 +237,8 @@ static const struct imx93_clk_ccgr {
{ IMX93_CLK_USB_CONTROLLER_GATE, "usb_controller", "hsio_root", 0x9a00, },
{ IMX93_CLK_USB_TEST_60M_GATE, "usb_test_60m", "hsio_usb_test_60m_root", 0x9a40, },
{ IMX93_CLK_HSIO_TROUT_24M_GATE, "hsio_trout_24m", "osc_24m", 0x9a80, },
{ IMX93_CLK_PDM_GATE, "pdm", "pdm_root", 0x9ac0, },
{ IMX93_CLK_PDM_GATE, "pdm", "pdm_root", 0x9ac0, 0, &share_count_pdm},
{ IMX93_CLK_PDM_IPG, "pdm_ipg_clk", "bus_aon_root", 0x9ac0, 0, &share_count_pdm},
{ IMX93_CLK_MQS1_GATE, "mqs1", "sai1_root", 0x9b00, },
{ IMX93_CLK_MQS2_GATE, "mqs2", "sai3_root", 0x9b40, },
{ IMX93_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, },

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