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Merge branch 'dma_complete' into next
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f8d9f628e1
@ -404,7 +404,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
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BIT(slot));
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if (edma_cc[ctlr]->intr_data[channel].callback)
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edma_cc[ctlr]->intr_data[channel].callback(
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channel, DMA_COMPLETE,
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channel, EDMA_DMA_COMPLETE,
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edma_cc[ctlr]->intr_data[channel].data);
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}
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} while (sh_ipr);
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@ -459,7 +459,7 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
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callback) {
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edma_cc[ctlr]->intr_data[k].
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callback(k,
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DMA_CC_ERROR,
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EDMA_DMA_CC_ERROR,
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edma_cc[ctlr]->intr_data
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[k].data);
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}
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@ -471,7 +471,7 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
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edma_pause(echan->ch_num);
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switch (ch_status) {
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case DMA_COMPLETE:
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case EDMA_DMA_COMPLETE:
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spin_lock_irqsave(&echan->vchan.lock, flags);
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edesc = echan->edesc;
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@ -490,7 +490,7 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
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spin_unlock_irqrestore(&echan->vchan.lock, flags);
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break;
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case DMA_CC_ERROR:
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case EDMA_DMA_CC_ERROR:
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spin_lock_irqsave(&echan->vchan.lock, flags);
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edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p);
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@ -67,10 +67,10 @@ struct edmacc_param {
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#define ITCCHEN BIT(23)
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/*ch_status paramater of callback function possible values*/
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#define DMA_COMPLETE 1
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#define DMA_CC_ERROR 2
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#define DMA_TC1_ERROR 3
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#define DMA_TC2_ERROR 4
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#define EDMA_DMA_COMPLETE 1
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#define EDMA_DMA_CC_ERROR 2
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#define EDMA_DMA_TC1_ERROR 3
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#define EDMA_DMA_TC2_ERROR 4
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enum address_mode {
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INCR = 0,
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