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https://github.com/torvalds/linux.git
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Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
This commit is contained in:
Linus Torvalds
commit
f8cc5756de
@ -49,12 +49,6 @@ static void __iommu_flushall(struct pci_iommu *iommu)
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/* Ensure completion of previous PIO writes. */
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(void) pci_iommu_read(iommu->write_complete_reg);
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/* Now update everyone's flush point. */
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for (entry = 0; entry < PBM_NCLUSTERS; entry++) {
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iommu->alloc_info[entry].flush =
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iommu->alloc_info[entry].next;
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}
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}
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#define IOPTE_CONSISTENT(CTX) \
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@ -80,120 +74,117 @@ static void inline iopte_make_dummy(struct pci_iommu *iommu, iopte_t *iopte)
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iopte_val(*iopte) = val;
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}
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void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize)
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/* Based largely upon the ppc64 iommu allocator. */
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static long pci_arena_alloc(struct pci_iommu *iommu, unsigned long npages)
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{
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int i;
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struct pci_iommu_arena *arena = &iommu->arena;
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unsigned long n, i, start, end, limit;
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int pass;
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tsbsize /= sizeof(iopte_t);
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limit = arena->limit;
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start = arena->hint;
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pass = 0;
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for (i = 0; i < tsbsize; i++)
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again:
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n = find_next_zero_bit(arena->map, limit, start);
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end = n + npages;
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if (unlikely(end >= limit)) {
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if (likely(pass < 1)) {
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limit = start;
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start = 0;
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__iommu_flushall(iommu);
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pass++;
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goto again;
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} else {
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/* Scanned the whole thing, give up. */
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return -1;
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}
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}
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for (i = n; i < end; i++) {
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if (test_bit(i, arena->map)) {
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start = i + 1;
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goto again;
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}
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}
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for (i = n; i < end; i++)
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__set_bit(i, arena->map);
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arena->hint = end;
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return n;
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}
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static void pci_arena_free(struct pci_iommu_arena *arena, unsigned long base, unsigned long npages)
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{
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unsigned long i;
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for (i = base; i < (base + npages); i++)
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__clear_bit(i, arena->map);
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}
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void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask)
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{
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unsigned long i, tsbbase, order, sz, num_tsb_entries;
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num_tsb_entries = tsbsize / sizeof(iopte_t);
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/* Setup initial software IOMMU state. */
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spin_lock_init(&iommu->lock);
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iommu->ctx_lowest_free = 1;
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iommu->page_table_map_base = dma_offset;
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iommu->dma_addr_mask = dma_addr_mask;
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/* Allocate and initialize the free area map. */
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sz = num_tsb_entries / 8;
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sz = (sz + 7UL) & ~7UL;
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iommu->arena.map = kmalloc(sz, GFP_KERNEL);
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if (!iommu->arena.map) {
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prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n");
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prom_halt();
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}
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memset(iommu->arena.map, 0, sz);
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iommu->arena.limit = num_tsb_entries;
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/* Allocate and initialize the dummy page which we
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* set inactive IO PTEs to point to.
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*/
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iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0);
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if (!iommu->dummy_page) {
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prom_printf("PCI_IOMMU: Error, gfp(dummy_page) failed.\n");
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prom_halt();
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}
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memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
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iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
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/* Now allocate and setup the IOMMU page table itself. */
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order = get_order(tsbsize);
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tsbbase = __get_free_pages(GFP_KERNEL, order);
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if (!tsbbase) {
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prom_printf("PCI_IOMMU: Error, gfp(tsb) failed.\n");
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prom_halt();
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}
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iommu->page_table = (iopte_t *)tsbbase;
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for (i = 0; i < num_tsb_entries; i++)
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iopte_make_dummy(iommu, &iommu->page_table[i]);
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}
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static iopte_t *alloc_streaming_cluster(struct pci_iommu *iommu, unsigned long npages)
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static inline iopte_t *alloc_npages(struct pci_iommu *iommu, unsigned long npages)
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{
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iopte_t *iopte, *limit, *first;
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unsigned long cnum, ent, flush_point;
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long entry;
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cnum = 0;
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while ((1UL << cnum) < npages)
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cnum++;
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iopte = (iommu->page_table +
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(cnum << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
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entry = pci_arena_alloc(iommu, npages);
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if (unlikely(entry < 0))
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return NULL;
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if (cnum == 0)
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limit = (iommu->page_table +
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iommu->lowest_consistent_map);
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else
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limit = (iopte +
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(1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
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iopte += ((ent = iommu->alloc_info[cnum].next) << cnum);
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flush_point = iommu->alloc_info[cnum].flush;
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first = iopte;
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for (;;) {
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if (IOPTE_IS_DUMMY(iommu, iopte)) {
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if ((iopte + (1 << cnum)) >= limit)
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ent = 0;
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else
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ent = ent + 1;
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iommu->alloc_info[cnum].next = ent;
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if (ent == flush_point)
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__iommu_flushall(iommu);
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break;
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}
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iopte += (1 << cnum);
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ent++;
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if (iopte >= limit) {
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iopte = (iommu->page_table +
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(cnum <<
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(iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
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ent = 0;
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}
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if (ent == flush_point)
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__iommu_flushall(iommu);
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if (iopte == first)
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goto bad;
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}
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/* I've got your streaming cluster right here buddy boy... */
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return iopte;
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bad:
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printk(KERN_EMERG "pci_iommu: alloc_streaming_cluster of npages(%ld) failed!\n",
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npages);
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return NULL;
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return iommu->page_table + entry;
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}
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static void free_streaming_cluster(struct pci_iommu *iommu, dma_addr_t base,
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unsigned long npages, unsigned long ctx)
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static inline void free_npages(struct pci_iommu *iommu, dma_addr_t base, unsigned long npages)
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{
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unsigned long cnum, ent;
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cnum = 0;
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while ((1UL << cnum) < npages)
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cnum++;
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ent = (base << (32 - IO_PAGE_SHIFT + PBM_LOGCLUSTERS - iommu->page_table_sz_bits))
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>> (32 + PBM_LOGCLUSTERS + cnum - iommu->page_table_sz_bits);
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/* If the global flush might not have caught this entry,
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* adjust the flush point such that we will flush before
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* ever trying to reuse it.
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*/
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#define between(X,Y,Z) (((Z) - (Y)) >= ((X) - (Y)))
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if (between(ent, iommu->alloc_info[cnum].next, iommu->alloc_info[cnum].flush))
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iommu->alloc_info[cnum].flush = ent;
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#undef between
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}
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/* We allocate consistent mappings from the end of cluster zero. */
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static iopte_t *alloc_consistent_cluster(struct pci_iommu *iommu, unsigned long npages)
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{
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iopte_t *iopte;
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iopte = iommu->page_table + (1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS));
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while (iopte > iommu->page_table) {
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iopte--;
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if (IOPTE_IS_DUMMY(iommu, iopte)) {
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unsigned long tmp = npages;
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while (--tmp) {
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iopte--;
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if (!IOPTE_IS_DUMMY(iommu, iopte))
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break;
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}
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if (tmp == 0) {
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u32 entry = (iopte - iommu->page_table);
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if (entry < iommu->lowest_consistent_map)
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iommu->lowest_consistent_map = entry;
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return iopte;
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}
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}
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}
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return NULL;
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pci_arena_free(&iommu->arena, base >> IO_PAGE_SHIFT, npages);
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}
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static int iommu_alloc_ctx(struct pci_iommu *iommu)
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@ -233,7 +224,7 @@ void *pci_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_ad
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struct pcidev_cookie *pcp;
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struct pci_iommu *iommu;
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iopte_t *iopte;
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unsigned long flags, order, first_page, ctx;
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unsigned long flags, order, first_page;
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void *ret;
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int npages;
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@ -251,9 +242,10 @@ void *pci_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_ad
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iommu = pcp->pbm->iommu;
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spin_lock_irqsave(&iommu->lock, flags);
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iopte = alloc_consistent_cluster(iommu, size >> IO_PAGE_SHIFT);
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if (iopte == NULL) {
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spin_unlock_irqrestore(&iommu->lock, flags);
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iopte = alloc_npages(iommu, size >> IO_PAGE_SHIFT);
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (unlikely(iopte == NULL)) {
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free_pages(first_page, order);
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return NULL;
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}
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@ -262,31 +254,15 @@ void *pci_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_ad
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((iopte - iommu->page_table) << IO_PAGE_SHIFT));
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ret = (void *) first_page;
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npages = size >> IO_PAGE_SHIFT;
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ctx = 0;
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if (iommu->iommu_ctxflush)
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ctx = iommu_alloc_ctx(iommu);
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first_page = __pa(first_page);
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while (npages--) {
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iopte_val(*iopte) = (IOPTE_CONSISTENT(ctx) |
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iopte_val(*iopte) = (IOPTE_CONSISTENT(0UL) |
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IOPTE_WRITE |
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(first_page & IOPTE_PAGE));
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iopte++;
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first_page += IO_PAGE_SIZE;
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}
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{
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int i;
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u32 daddr = *dma_addrp;
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npages = size >> IO_PAGE_SHIFT;
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for (i = 0; i < npages; i++) {
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pci_iommu_write(iommu->iommu_flush, daddr);
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daddr += IO_PAGE_SIZE;
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}
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}
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spin_unlock_irqrestore(&iommu->lock, flags);
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return ret;
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}
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@ -296,7 +272,7 @@ void pci_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_
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struct pcidev_cookie *pcp;
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struct pci_iommu *iommu;
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iopte_t *iopte;
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unsigned long flags, order, npages, i, ctx;
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unsigned long flags, order, npages;
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npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
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pcp = pdev->sysdata;
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@ -306,46 +282,7 @@ void pci_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_
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spin_lock_irqsave(&iommu->lock, flags);
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if ((iopte - iommu->page_table) ==
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iommu->lowest_consistent_map) {
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iopte_t *walk = iopte + npages;
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iopte_t *limit;
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limit = (iommu->page_table +
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(1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
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while (walk < limit) {
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if (!IOPTE_IS_DUMMY(iommu, walk))
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break;
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walk++;
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}
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iommu->lowest_consistent_map =
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(walk - iommu->page_table);
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}
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/* Data for consistent mappings cannot enter the streaming
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* buffers, so we only need to update the TSB. We flush
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* the IOMMU here as well to prevent conflicts with the
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* streaming mapping deferred tlb flush scheme.
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*/
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ctx = 0;
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if (iommu->iommu_ctxflush)
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ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
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for (i = 0; i < npages; i++, iopte++)
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iopte_make_dummy(iommu, iopte);
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if (iommu->iommu_ctxflush) {
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pci_iommu_write(iommu->iommu_ctxflush, ctx);
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} else {
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for (i = 0; i < npages; i++) {
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u32 daddr = dvma + (i << IO_PAGE_SHIFT);
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pci_iommu_write(iommu->iommu_flush, daddr);
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}
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}
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iommu_free_ctx(iommu, ctx);
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free_npages(iommu, dvma, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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@ -372,25 +309,27 @@ dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direct
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iommu = pcp->pbm->iommu;
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strbuf = &pcp->pbm->stc;
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if (direction == PCI_DMA_NONE)
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BUG();
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if (unlikely(direction == PCI_DMA_NONE))
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goto bad_no_ctx;
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oaddr = (unsigned long)ptr;
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npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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spin_lock_irqsave(&iommu->lock, flags);
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base = alloc_npages(iommu, npages);
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ctx = 0;
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if (iommu->iommu_ctxflush)
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ctx = iommu_alloc_ctx(iommu);
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spin_unlock_irqrestore(&iommu->lock, flags);
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base = alloc_streaming_cluster(iommu, npages);
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if (base == NULL)
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if (unlikely(!base))
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goto bad;
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bus_addr = (iommu->page_table_map_base +
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((base - iommu->page_table) << IO_PAGE_SHIFT));
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ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
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base_paddr = __pa(oaddr & IO_PAGE_MASK);
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ctx = 0;
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if (iommu->iommu_ctxflush)
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ctx = iommu_alloc_ctx(iommu);
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if (strbuf->strbuf_enabled)
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iopte_protection = IOPTE_STREAMING(ctx);
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else
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@ -401,12 +340,13 @@ dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direct
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for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE)
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iopte_val(*base) = iopte_protection | base_paddr;
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spin_unlock_irqrestore(&iommu->lock, flags);
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return ret;
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bad:
|
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spin_unlock_irqrestore(&iommu->lock, flags);
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iommu_free_ctx(iommu, ctx);
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bad_no_ctx:
|
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if (printk_ratelimit())
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WARN_ON(1);
|
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return PCI_DMA_ERROR_CODE;
|
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}
|
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|
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@ -481,10 +421,13 @@ void pci_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int
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struct pci_iommu *iommu;
|
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struct pci_strbuf *strbuf;
|
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iopte_t *base;
|
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unsigned long flags, npages, ctx;
|
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unsigned long flags, npages, ctx, i;
|
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|
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if (direction == PCI_DMA_NONE)
|
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BUG();
|
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if (unlikely(direction == PCI_DMA_NONE)) {
|
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if (printk_ratelimit())
|
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WARN_ON(1);
|
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return;
|
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}
|
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|
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pcp = pdev->sysdata;
|
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iommu = pcp->pbm->iommu;
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@ -510,13 +453,14 @@ void pci_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int
|
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|
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/* Step 1: Kick data out of streaming buffers if necessary. */
|
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if (strbuf->strbuf_enabled)
|
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pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
|
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pci_strbuf_flush(strbuf, iommu, bus_addr, ctx,
|
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npages, direction);
|
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|
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/* Step 2: Clear out first TSB entry. */
|
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iopte_make_dummy(iommu, base);
|
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/* Step 2: Clear out TSB entries. */
|
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for (i = 0; i < npages; i++)
|
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iopte_make_dummy(iommu, base + i);
|
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|
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free_streaming_cluster(iommu, bus_addr - iommu->page_table_map_base,
|
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npages, ctx);
|
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free_npages(iommu, bus_addr - iommu->page_table_map_base, npages);
|
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|
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iommu_free_ctx(iommu, ctx);
|
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|
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@ -621,6 +565,8 @@ int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int
|
||||
pci_map_single(pdev,
|
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(page_address(sglist->page) + sglist->offset),
|
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sglist->length, direction);
|
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if (unlikely(sglist->dma_address == PCI_DMA_ERROR_CODE))
|
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return 0;
|
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sglist->dma_length = sglist->length;
|
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return 1;
|
||||
}
|
||||
@ -629,21 +575,29 @@ int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int
|
||||
iommu = pcp->pbm->iommu;
|
||||
strbuf = &pcp->pbm->stc;
|
||||
|
||||
if (direction == PCI_DMA_NONE)
|
||||
BUG();
|
||||
if (unlikely(direction == PCI_DMA_NONE))
|
||||
goto bad_no_ctx;
|
||||
|
||||
/* Step 1: Prepare scatter list. */
|
||||
|
||||
npages = prepare_sg(sglist, nelems);
|
||||
|
||||
/* Step 2: Allocate a cluster. */
|
||||
/* Step 2: Allocate a cluster and context, if necessary. */
|
||||
|
||||
spin_lock_irqsave(&iommu->lock, flags);
|
||||
|
||||
base = alloc_streaming_cluster(iommu, npages);
|
||||
base = alloc_npages(iommu, npages);
|
||||
ctx = 0;
|
||||
if (iommu->iommu_ctxflush)
|
||||
ctx = iommu_alloc_ctx(iommu);
|
||||
|
||||
spin_unlock_irqrestore(&iommu->lock, flags);
|
||||
|
||||
if (base == NULL)
|
||||
goto bad;
|
||||
dma_base = iommu->page_table_map_base + ((base - iommu->page_table) << IO_PAGE_SHIFT);
|
||||
|
||||
dma_base = iommu->page_table_map_base +
|
||||
((base - iommu->page_table) << IO_PAGE_SHIFT);
|
||||
|
||||
/* Step 3: Normalize DMA addresses. */
|
||||
used = nelems;
|
||||
@ -656,30 +610,28 @@ int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int
|
||||
}
|
||||
used = nelems - used;
|
||||
|
||||
/* Step 4: Choose a context if necessary. */
|
||||
ctx = 0;
|
||||
if (iommu->iommu_ctxflush)
|
||||
ctx = iommu_alloc_ctx(iommu);
|
||||
|
||||
/* Step 5: Create the mappings. */
|
||||
/* Step 4: Create the mappings. */
|
||||
if (strbuf->strbuf_enabled)
|
||||
iopte_protection = IOPTE_STREAMING(ctx);
|
||||
else
|
||||
iopte_protection = IOPTE_CONSISTENT(ctx);
|
||||
if (direction != PCI_DMA_TODEVICE)
|
||||
iopte_protection |= IOPTE_WRITE;
|
||||
fill_sg (base, sglist, used, nelems, iopte_protection);
|
||||
|
||||
fill_sg(base, sglist, used, nelems, iopte_protection);
|
||||
|
||||
#ifdef VERIFY_SG
|
||||
verify_sglist(sglist, nelems, base, npages);
|
||||
#endif
|
||||
|
||||
spin_unlock_irqrestore(&iommu->lock, flags);
|
||||
|
||||
return used;
|
||||
|
||||
bad:
|
||||
spin_unlock_irqrestore(&iommu->lock, flags);
|
||||
return PCI_DMA_ERROR_CODE;
|
||||
iommu_free_ctx(iommu, ctx);
|
||||
bad_no_ctx:
|
||||
if (printk_ratelimit())
|
||||
WARN_ON(1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Unmap a set of streaming mode DMA translations. */
|
||||
@ -692,8 +644,10 @@ void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems,
|
||||
unsigned long flags, ctx, i, npages;
|
||||
u32 bus_addr;
|
||||
|
||||
if (direction == PCI_DMA_NONE)
|
||||
BUG();
|
||||
if (unlikely(direction == PCI_DMA_NONE)) {
|
||||
if (printk_ratelimit())
|
||||
WARN_ON(1);
|
||||
}
|
||||
|
||||
pcp = pdev->sysdata;
|
||||
iommu = pcp->pbm->iommu;
|
||||
@ -705,7 +659,8 @@ void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems,
|
||||
if (sglist[i].dma_length == 0)
|
||||
break;
|
||||
i--;
|
||||
npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) - bus_addr) >> IO_PAGE_SHIFT;
|
||||
npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) -
|
||||
bus_addr) >> IO_PAGE_SHIFT;
|
||||
|
||||
base = iommu->page_table +
|
||||
((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
|
||||
@ -726,11 +681,11 @@ void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems,
|
||||
if (strbuf->strbuf_enabled)
|
||||
pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
|
||||
|
||||
/* Step 2: Clear out first TSB entry. */
|
||||
iopte_make_dummy(iommu, base);
|
||||
/* Step 2: Clear out the TSB entries. */
|
||||
for (i = 0; i < npages; i++)
|
||||
iopte_make_dummy(iommu, base + i);
|
||||
|
||||
free_streaming_cluster(iommu, bus_addr - iommu->page_table_map_base,
|
||||
npages, ctx);
|
||||
free_npages(iommu, bus_addr - iommu->page_table_map_base, npages);
|
||||
|
||||
iommu_free_ctx(iommu, ctx);
|
||||
|
||||
|
||||
@ -1207,13 +1207,9 @@ static void psycho_scan_bus(struct pci_controller_info *p)
|
||||
static void psycho_iommu_init(struct pci_controller_info *p)
|
||||
{
|
||||
struct pci_iommu *iommu = p->pbm_A.iommu;
|
||||
unsigned long tsbbase, i;
|
||||
unsigned long i;
|
||||
u64 control;
|
||||
|
||||
/* Setup initial software IOMMU state. */
|
||||
spin_lock_init(&iommu->lock);
|
||||
iommu->ctx_lowest_free = 1;
|
||||
|
||||
/* Register addresses. */
|
||||
iommu->iommu_control = p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL;
|
||||
iommu->iommu_tsbbase = p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE;
|
||||
@ -1240,40 +1236,10 @@ static void psycho_iommu_init(struct pci_controller_info *p)
|
||||
/* Leave diag mode enabled for full-flushing done
|
||||
* in pci_iommu.c
|
||||
*/
|
||||
pci_iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff);
|
||||
|
||||
iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0);
|
||||
if (!iommu->dummy_page) {
|
||||
prom_printf("PSYCHO_IOMMU: Error, gfp(dummy_page) failed.\n");
|
||||
prom_halt();
|
||||
}
|
||||
memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
|
||||
iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
|
||||
|
||||
/* Using assumed page size 8K with 128K entries we need 1MB iommu page
|
||||
* table (128K ioptes * 8 bytes per iopte). This is
|
||||
* page order 7 on UltraSparc.
|
||||
*/
|
||||
tsbbase = __get_free_pages(GFP_KERNEL, get_order(IO_TSB_SIZE));
|
||||
if (!tsbbase) {
|
||||
prom_printf("PSYCHO_IOMMU: Error, gfp(tsb) failed.\n");
|
||||
prom_halt();
|
||||
}
|
||||
iommu->page_table = (iopte_t *)tsbbase;
|
||||
iommu->page_table_sz_bits = 17;
|
||||
iommu->page_table_map_base = 0xc0000000;
|
||||
iommu->dma_addr_mask = 0xffffffff;
|
||||
pci_iommu_table_init(iommu, IO_TSB_SIZE);
|
||||
|
||||
/* We start with no consistent mappings. */
|
||||
iommu->lowest_consistent_map =
|
||||
1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS);
|
||||
|
||||
for (i = 0; i < PBM_NCLUSTERS; i++) {
|
||||
iommu->alloc_info[i].flush = 0;
|
||||
iommu->alloc_info[i].next = 0;
|
||||
}
|
||||
|
||||
psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE, __pa(tsbbase));
|
||||
psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE,
|
||||
__pa(iommu->page_table));
|
||||
|
||||
control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
|
||||
control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);
|
||||
@ -1281,7 +1247,7 @@ static void psycho_iommu_init(struct pci_controller_info *p)
|
||||
psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
|
||||
|
||||
/* If necessary, hook us up for starfire IRQ translations. */
|
||||
if(this_is_starfire)
|
||||
if (this_is_starfire)
|
||||
p->starfire_cookie = starfire_hookup(p->pbm_A.portid);
|
||||
else
|
||||
p->starfire_cookie = NULL;
|
||||
|
||||
@ -1267,13 +1267,9 @@ static void sabre_iommu_init(struct pci_controller_info *p,
|
||||
u32 dma_mask)
|
||||
{
|
||||
struct pci_iommu *iommu = p->pbm_A.iommu;
|
||||
unsigned long tsbbase, i, order;
|
||||
unsigned long i;
|
||||
u64 control;
|
||||
|
||||
/* Setup initial software IOMMU state. */
|
||||
spin_lock_init(&iommu->lock);
|
||||
iommu->ctx_lowest_free = 1;
|
||||
|
||||
/* Register addresses. */
|
||||
iommu->iommu_control = p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL;
|
||||
iommu->iommu_tsbbase = p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE;
|
||||
@ -1295,26 +1291,10 @@ static void sabre_iommu_init(struct pci_controller_info *p,
|
||||
/* Leave diag mode enabled for full-flushing done
|
||||
* in pci_iommu.c
|
||||
*/
|
||||
pci_iommu_table_init(iommu, tsbsize * 1024 * 8, dvma_offset, dma_mask);
|
||||
|
||||
iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0);
|
||||
if (!iommu->dummy_page) {
|
||||
prom_printf("PSYCHO_IOMMU: Error, gfp(dummy_page) failed.\n");
|
||||
prom_halt();
|
||||
}
|
||||
memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
|
||||
iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
|
||||
|
||||
tsbbase = __get_free_pages(GFP_KERNEL, order = get_order(tsbsize * 1024 * 8));
|
||||
if (!tsbbase) {
|
||||
prom_printf("SABRE_IOMMU: Error, gfp(tsb) failed.\n");
|
||||
prom_halt();
|
||||
}
|
||||
iommu->page_table = (iopte_t *)tsbbase;
|
||||
iommu->page_table_map_base = dvma_offset;
|
||||
iommu->dma_addr_mask = dma_mask;
|
||||
pci_iommu_table_init(iommu, PAGE_SIZE << order);
|
||||
|
||||
sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE, __pa(tsbbase));
|
||||
sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE,
|
||||
__pa(iommu->page_table));
|
||||
|
||||
control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);
|
||||
control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ);
|
||||
@ -1322,11 +1302,9 @@ static void sabre_iommu_init(struct pci_controller_info *p,
|
||||
switch(tsbsize) {
|
||||
case 64:
|
||||
control |= SABRE_IOMMU_TSBSZ_64K;
|
||||
iommu->page_table_sz_bits = 16;
|
||||
break;
|
||||
case 128:
|
||||
control |= SABRE_IOMMU_TSBSZ_128K;
|
||||
iommu->page_table_sz_bits = 17;
|
||||
break;
|
||||
default:
|
||||
prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize);
|
||||
@ -1334,15 +1312,6 @@ static void sabre_iommu_init(struct pci_controller_info *p,
|
||||
break;
|
||||
}
|
||||
sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
|
||||
|
||||
/* We start with no consistent mappings. */
|
||||
iommu->lowest_consistent_map =
|
||||
1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS);
|
||||
|
||||
for (i = 0; i < PBM_NCLUSTERS; i++) {
|
||||
iommu->alloc_info[i].flush = 0;
|
||||
iommu->alloc_info[i].next = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static void pbm_register_toplevel_resources(struct pci_controller_info *p,
|
||||
|
||||
@ -1765,7 +1765,7 @@ static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
|
||||
static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
|
||||
{
|
||||
struct pci_iommu *iommu = pbm->iommu;
|
||||
unsigned long tsbbase, i, tagbase, database, order;
|
||||
unsigned long i, tagbase, database;
|
||||
u32 vdma[2], dma_mask;
|
||||
u64 control;
|
||||
int err, tsbsize;
|
||||
@ -1800,10 +1800,6 @@ static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
|
||||
prom_halt();
|
||||
};
|
||||
|
||||
/* Setup initial software IOMMU state. */
|
||||
spin_lock_init(&iommu->lock);
|
||||
iommu->ctx_lowest_free = 1;
|
||||
|
||||
/* Register addresses, SCHIZO has iommu ctx flushing. */
|
||||
iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL;
|
||||
iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE;
|
||||
@ -1832,56 +1828,9 @@ static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
|
||||
/* Leave diag mode enabled for full-flushing done
|
||||
* in pci_iommu.c
|
||||
*/
|
||||
pci_iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask);
|
||||
|
||||
iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0);
|
||||
if (!iommu->dummy_page) {
|
||||
prom_printf("PSYCHO_IOMMU: Error, gfp(dummy_page) failed.\n");
|
||||
prom_halt();
|
||||
}
|
||||
memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
|
||||
iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
|
||||
|
||||
/* Using assumed page size 8K with 128K entries we need 1MB iommu page
|
||||
* table (128K ioptes * 8 bytes per iopte). This is
|
||||
* page order 7 on UltraSparc.
|
||||
*/
|
||||
order = get_order(tsbsize * 8 * 1024);
|
||||
tsbbase = __get_free_pages(GFP_KERNEL, order);
|
||||
if (!tsbbase) {
|
||||
prom_printf("%s: Error, gfp(tsb) failed.\n", pbm->name);
|
||||
prom_halt();
|
||||
}
|
||||
|
||||
iommu->page_table = (iopte_t *)tsbbase;
|
||||
iommu->page_table_map_base = vdma[0];
|
||||
iommu->dma_addr_mask = dma_mask;
|
||||
pci_iommu_table_init(iommu, PAGE_SIZE << order);
|
||||
|
||||
switch (tsbsize) {
|
||||
case 64:
|
||||
iommu->page_table_sz_bits = 16;
|
||||
break;
|
||||
|
||||
case 128:
|
||||
iommu->page_table_sz_bits = 17;
|
||||
break;
|
||||
|
||||
default:
|
||||
prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize);
|
||||
prom_halt();
|
||||
break;
|
||||
};
|
||||
|
||||
/* We start with no consistent mappings. */
|
||||
iommu->lowest_consistent_map =
|
||||
1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS);
|
||||
|
||||
for (i = 0; i < PBM_NCLUSTERS; i++) {
|
||||
iommu->alloc_info[i].flush = 0;
|
||||
iommu->alloc_info[i].next = 0;
|
||||
}
|
||||
|
||||
schizo_write(iommu->iommu_tsbbase, __pa(tsbbase));
|
||||
schizo_write(iommu->iommu_tsbbase, __pa(iommu->page_table));
|
||||
|
||||
control = schizo_read(iommu->iommu_control);
|
||||
control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);
|
||||
|
||||
@ -1001,13 +1001,6 @@ void smp_penguin_jailcell(int irq, struct pt_regs *regs)
|
||||
preempt_enable();
|
||||
}
|
||||
|
||||
extern unsigned long xcall_promstop;
|
||||
|
||||
void smp_promstop_others(void)
|
||||
{
|
||||
smp_cross_call(&xcall_promstop, 0, 0, 0);
|
||||
}
|
||||
|
||||
#define prof_multiplier(__cpu) cpu_data(__cpu).multiplier
|
||||
#define prof_counter(__cpu) cpu_data(__cpu).counter
|
||||
|
||||
|
||||
@ -453,22 +453,6 @@ xcall_flush_dcache_page_spitfire: /* %g1 == physical page address
|
||||
nop
|
||||
nop
|
||||
|
||||
.globl xcall_promstop
|
||||
xcall_promstop:
|
||||
rdpr %pstate, %g2
|
||||
wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
|
||||
rdpr %pil, %g2
|
||||
wrpr %g0, 15, %pil
|
||||
sethi %hi(109f), %g7
|
||||
b,pt %xcc, etrap_irq
|
||||
109: or %g7, %lo(109b), %g7
|
||||
flushw
|
||||
call prom_stopself
|
||||
nop
|
||||
/* We should not return, just spin if we do... */
|
||||
1: b,a,pt %xcc, 1b
|
||||
nop
|
||||
|
||||
.data
|
||||
|
||||
errata32_hwbug:
|
||||
|
||||
@ -68,19 +68,11 @@ void prom_cmdline(void)
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
extern void smp_promstop_others(void);
|
||||
#endif
|
||||
|
||||
/* Drop into the prom, but completely terminate the program.
|
||||
* No chance of continuing.
|
||||
*/
|
||||
void prom_halt(void)
|
||||
{
|
||||
#ifdef CONFIG_SMP
|
||||
smp_promstop_others();
|
||||
udelay(8000);
|
||||
#endif
|
||||
again:
|
||||
p1275_cmd("exit", P1275_INOUT(0, 0));
|
||||
goto again; /* PROM is out to get me -DaveM */
|
||||
@ -88,10 +80,6 @@ again:
|
||||
|
||||
void prom_halt_power_off(void)
|
||||
{
|
||||
#ifdef CONFIG_SMP
|
||||
smp_promstop_others();
|
||||
udelay(8000);
|
||||
#endif
|
||||
p1275_cmd("SUNW,power-off", P1275_INOUT(0, 0));
|
||||
|
||||
/* if nothing else helps, we just halt */
|
||||
|
||||
@ -1119,6 +1119,36 @@ static inline void update_can_queue(struct Scsi_Host *host, u_int in_ptr, u_int
|
||||
host->sg_tablesize = QLOGICPTI_MAX_SG(num_free);
|
||||
}
|
||||
|
||||
static unsigned int scsi_rbuf_get(struct scsi_cmnd *cmd, unsigned char **buf_out)
|
||||
{
|
||||
unsigned char *buf;
|
||||
unsigned int buflen;
|
||||
|
||||
if (cmd->use_sg) {
|
||||
struct scatterlist *sg;
|
||||
|
||||
sg = (struct scatterlist *) cmd->request_buffer;
|
||||
buf = kmap_atomic(sg->page, KM_IRQ0) + sg->offset;
|
||||
buflen = sg->length;
|
||||
} else {
|
||||
buf = cmd->request_buffer;
|
||||
buflen = cmd->request_bufflen;
|
||||
}
|
||||
|
||||
*buf_out = buf;
|
||||
return buflen;
|
||||
}
|
||||
|
||||
static void scsi_rbuf_put(struct scsi_cmnd *cmd, unsigned char *buf)
|
||||
{
|
||||
if (cmd->use_sg) {
|
||||
struct scatterlist *sg;
|
||||
|
||||
sg = (struct scatterlist *) cmd->request_buffer;
|
||||
kunmap_atomic(buf - sg->offset, KM_IRQ0);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Until we scan the entire bus with inquiries, go throught this fella...
|
||||
*/
|
||||
@ -1145,11 +1175,9 @@ static void ourdone(struct scsi_cmnd *Cmnd)
|
||||
int ok = host_byte(Cmnd->result) == DID_OK;
|
||||
if (Cmnd->cmnd[0] == 0x12 && ok) {
|
||||
unsigned char *iqd;
|
||||
unsigned int iqd_len;
|
||||
|
||||
if (Cmnd->use_sg != 0)
|
||||
BUG();
|
||||
|
||||
iqd = ((unsigned char *)Cmnd->buffer);
|
||||
iqd_len = scsi_rbuf_get(Cmnd, &iqd);
|
||||
|
||||
/* tags handled in midlayer */
|
||||
/* enable sync mode? */
|
||||
@ -1163,6 +1191,9 @@ static void ourdone(struct scsi_cmnd *Cmnd)
|
||||
if (iqd[7] & 0x20) {
|
||||
qpti->dev_param[tgt].device_flags |= 0x20;
|
||||
}
|
||||
|
||||
scsi_rbuf_put(Cmnd, iqd);
|
||||
|
||||
qpti->sbits |= (1 << tgt);
|
||||
} else if (!ok) {
|
||||
qpti->sbits |= (1 << tgt);
|
||||
|
||||
@ -27,23 +27,27 @@
|
||||
* PCI bus.
|
||||
*/
|
||||
|
||||
#define PBM_LOGCLUSTERS 3
|
||||
#define PBM_NCLUSTERS (1 << PBM_LOGCLUSTERS)
|
||||
|
||||
struct pci_controller_info;
|
||||
|
||||
/* This contains the software state necessary to drive a PCI
|
||||
* controller's IOMMU.
|
||||
*/
|
||||
struct pci_iommu_arena {
|
||||
unsigned long *map;
|
||||
unsigned int hint;
|
||||
unsigned int limit;
|
||||
};
|
||||
|
||||
struct pci_iommu {
|
||||
/* This protects the controller's IOMMU and all
|
||||
* streaming buffers underneath.
|
||||
*/
|
||||
spinlock_t lock;
|
||||
|
||||
struct pci_iommu_arena arena;
|
||||
|
||||
/* IOMMU page table, a linear array of ioptes. */
|
||||
iopte_t *page_table; /* The page table itself. */
|
||||
int page_table_sz_bits; /* log2 of ow many pages does it map? */
|
||||
|
||||
/* Base PCI memory space address where IOMMU mappings
|
||||
* begin.
|
||||
@ -62,12 +66,6 @@ struct pci_iommu {
|
||||
*/
|
||||
unsigned long write_complete_reg;
|
||||
|
||||
/* The lowest used consistent mapping entry. Since
|
||||
* we allocate consistent maps out of cluster 0 this
|
||||
* is relative to the beginning of closter 0.
|
||||
*/
|
||||
u32 lowest_consistent_map;
|
||||
|
||||
/* In order to deal with some buggy third-party PCI bridges that
|
||||
* do wrong prefetching, we never mark valid mappings as invalid.
|
||||
* Instead we point them at this dummy page.
|
||||
@ -75,16 +73,6 @@ struct pci_iommu {
|
||||
unsigned long dummy_page;
|
||||
unsigned long dummy_page_pa;
|
||||
|
||||
/* If PBM_NCLUSTERS is ever decreased to 4 or lower,
|
||||
* or if largest supported page_table_sz * 8K goes above
|
||||
* 2GB, you must increase the size of the type of
|
||||
* these counters. You have been duly warned. -DaveM
|
||||
*/
|
||||
struct {
|
||||
u16 next;
|
||||
u16 flush;
|
||||
} alloc_info[PBM_NCLUSTERS];
|
||||
|
||||
/* CTX allocation. */
|
||||
unsigned long ctx_lowest_free;
|
||||
unsigned long ctx_bitmap[IOMMU_NUM_CTXS / (sizeof(unsigned long) * 8)];
|
||||
@ -102,7 +90,7 @@ struct pci_iommu {
|
||||
u32 dma_addr_mask;
|
||||
};
|
||||
|
||||
extern void pci_iommu_table_init(struct pci_iommu *, int);
|
||||
extern void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask);
|
||||
|
||||
/* This describes a PCI bus module's streaming buffer. */
|
||||
struct pci_strbuf {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user