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ARC: [clockevent] simplify timer ISR
* Remove one liner IRQ ACK accessor, it was coming in the way of readability. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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@ -155,22 +155,6 @@ static void arc_timer_event_setup(unsigned int limit)
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write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
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}
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/*
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* Acknowledge the interrupt (oneshot) and optionally re-arm it (periodic)
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* -Any write to CTRL Reg will ack the intr (NH bit: Count when not halted)
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* -Rearming is done by setting the IE bit
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*
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* Small optimisation: Normal code would have been
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* if (irq_reenable)
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* CTRL_REG = (IE | NH);
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* else
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* CTRL_REG = NH;
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* However since IE is BIT0 we can fold the branch
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*/
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static void arc_timer_event_ack(unsigned int irq_reenable)
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{
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write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
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}
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static int arc_clkevent_set_next_event(unsigned long delta,
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struct clock_event_device *dev)
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@ -207,10 +191,22 @@ static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
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static irqreturn_t timer_irq_handler(int irq, void *dev_id)
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{
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struct clock_event_device *clk = this_cpu_ptr(&arc_clockevent_device);
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/*
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* Note that generic IRQ core could have passed @evt for @dev_id if
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* irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
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*/
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struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
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int irq_reenable = evt->mode == CLOCK_EVT_MODE_PERIODIC;
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/*
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* Any write to CTRL reg ACks the interrupt, we rewrite the
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* Count when [N]ot [H]alted bit.
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* And re-arm it if perioid by [I]nterrupt [E]nable bit
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*/
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write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
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evt->event_handler(evt);
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arc_timer_event_ack(clk->mode == CLOCK_EVT_MODE_PERIODIC);
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clk->event_handler(clk);
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return IRQ_HANDLED;
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}
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