mirror of
https://github.com/torvalds/linux.git
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Samsung DTS ARM64 changes for v6.10, part two
Few changes exclusively for Google GS101:
1. Add HSI0 and HSI2 clock controllers (CMUs).
2. Add USB 3.1 Dual Role Device (DRD) support.
3. Add UFS (Universal Flash Storage) support.
4. Document bus clocks in pin controllers necessary for accessing
registers.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmY2JecQHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD11XtD/0Z1kko4kh5yhPR5k9PlqWtvRIdkJl/VVPT
WwqH2WlrNk6b4k9VQ81LDpgmvdZMFkYOiZ9c+pqtAIIdy1EHOrJS3hKEcC3+Nf84
iR1frVnlg8mROj2Iw8awVjzgJOgvL2sxkNcfV+316/akswmGuVKrDW8qfJ0BZYxn
riEjgIfYyaLUgjK98pokATQfpjwd3rnfifIG8hAEc7SAXrdNVKGiWNIa55bIgWJv
kJlRgXY47RaR+Ooznz9HNwa0NlI3LnMS1God0hHiM4typNqWvmAVtTlcfawyIzqQ
2dX9VsK4f/CEnTuFW+cXtSO8eGA2lTNIEfoXOTff5KebvaXZW5EY+5VQ2CHekFpF
ERumG47znXfuBLeXrbCVfw7NPvljgAh0LQN+g1IFH2Lw+QimqZA5H80eaZ3HZuXc
3z2vEQwshg3ct6l2wWnfK9XMSXrpKE4CoXfTemYpkJf7FSZxp33/glI690ttXC6X
+/Qgu21VmsNNPY+5H5xHAtCrGFkBfcLn7CrT1C+TJHO3PI65tkE4tOIkkCs3Q7+z
kz1JVLLj5Ee85HtSiO3h2sc1Q9ZAjpxlfaaZ+esE4GaJ557ouM/ZUTzRPYLiGDFx
XVGgJGhDQtvqnGO/UWAEM4K/Qz4mgeZpjyyWtMA1nYjcCYVqL4C0BHz3AL+fa1Ck
8e8QA8KxjQ==
=xbpt
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmY56qgACgkQYKtH/8kJ
UieBdRAAiMcVqW91TtSv0URuqkrzMDzADI4VVGGNhhL3gTGvp1RGAP1FTL6q1pUu
INssEtgEK6v5kPJAYLUMNiYsCz9jeeOzfoR5D++Qq8PPv4w54CUN62jXOjf9vG9D
CymEywEgaJAnFjb1XgNROuLjatm2GgbCZvUT0tLqFW9D1TA8mjmGYf24kHmzCQsf
leTRCY70kCmUvnfnwli36Gsx6sPP5niyeWl0UAdDuFlpfUqokBWGQ+lWx5zAkfBZ
zT4rDeyr1lxfRBUkXDwQlaAuf+mr7L+N+3C/VIZNW2V14zYCwCrPVJWtZgCBOv7V
99itbRQMfjpApkcY2q5agad6zJfLMeyruw6MCoAwwxErhLXq8S3QYZAdhgKIrfR5
yrIPtvMelvZJqYxTk9/24ecIGZlFJaxQsGVmgJjyt3MQFPus4sQkMifcYXVDSJlK
w7jqcUFmhn8KwmJU0YkmvFjYG/GJ7VDn55lC0E7pBLv2UuIbWqMGzDmlLNkxtLKM
h44PAEnoS2rdDQvFp8ijC7V15PpWG8vQOyIwGoIglcyVcg6xtN7ZAoB62DRl18iS
2OH28C4TNidP1CwwJgVSuL/0HQfG5BqRte6Zx7psVqOUxSx4CzhL+xsdwRSELKBL
c4q8nK2mhJ9UY83xSbN0FcORjUE1+Z4bznmRU5vRE4Oda3QPMu0=
=3I13
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt64-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM64 changes for v6.10, part two
Few changes exclusively for Google GS101:
1. Add HSI0 and HSI2 clock controllers (CMUs).
2. Add USB 3.1 Dual Role Device (DRD) support.
3. Add UFS (Universal Flash Storage) support.
4. Document bus clocks in pin controllers necessary for accessing
registers.
* tag 'samsung-dt64-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: gs101: specify empty clocks for remaining pinctrl
arm64: dts: exynos: gs101: specify bus clock for pinctrl_hsi2
arm64: dts: exynos: gs101: specify bus clock for pinctrl_peric[01]
arm64: dts: exynos: gs101: specify bus clock for pinctrl (far) alive
arm64: dts: exynos: gs101: enable ufs, phy on oriole & define ufs regulator
arm64: dts: exynos: gs101: Add ufs and ufs-phy dt nodes
arm64: dts: exynos: gs101: Add the hsi2 sysreg node
dt-bindings: soc: google: exynos-sysreg: add dedicated hsi2 sysreg compatible
arm64: dts: exynos: gs101-oriole: enable USB on this board
arm64: dts: exynos: gs101: add USB & USB-phy nodes
arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller
arm64: dts: exynos: gs101: enable cmu-hsi0 clock controller
dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit
dt-bindings: clock: google,gs101-clock: add HSI0 clock management unit
Link: https://lore.kernel.org/r/20240504121233.7589-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
f89d22439f
@ -30,16 +30,18 @@ properties:
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||||
- google,gs101-cmu-top
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||||
- google,gs101-cmu-apm
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- google,gs101-cmu-misc
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- google,gs101-cmu-hsi0
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- google,gs101-cmu-hsi2
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- google,gs101-cmu-peric0
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- google,gs101-cmu-peric1
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clocks:
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minItems: 1
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maxItems: 3
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maxItems: 5
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clock-names:
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minItems: 1
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maxItems: 3
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maxItems: 5
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"#clock-cells":
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const: 1
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@ -72,6 +74,55 @@ allOf:
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items:
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- const: oscclk
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- if:
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properties:
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compatible:
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contains:
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const: google,gs101-cmu-hsi0
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (24.576 MHz)
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- description: HSI0 bus clock (from CMU_TOP)
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- description: DPGTC (from CMU_TOP)
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- description: USB DRD controller clock (from CMU_TOP)
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- description: USB Display Port debug clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: bus
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- const: dpgtc
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- const: usb31drd
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- const: usbdpdbg
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- if:
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properties:
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compatible:
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contains:
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enum:
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- google,gs101-cmu-hsi2
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (24.576 MHz)
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- description: High Speed Interface bus clock (from CMU_TOP)
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- description: High Speed Interface pcie clock (from CMU_TOP)
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- description: High Speed Interface ufs clock (from CMU_TOP)
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- description: High Speed Interface mmc clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: bus
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- const: pcie
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- const: ufs
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- const: mmc
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- if:
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properties:
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compatible:
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@ -15,6 +15,7 @@ properties:
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- items:
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- enum:
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- google,gs101-apm-sysreg
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- google,gs101-hsi2-sysreg
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- google,gs101-peric0-sysreg
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- google,gs101-peric1-sysreg
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- samsung,exynos3-sysreg
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@ -72,6 +73,7 @@ allOf:
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compatible:
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contains:
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enum:
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- google,gs101-hsi2-sysreg
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- google,gs101-peric0-sysreg
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- google,gs101-peric1-sysreg
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- samsung,exynos850-cmgp-sysreg
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@ -53,6 +53,21 @@
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wakeup-source;
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};
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};
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/* TODO: Remove this once PMIC is implemented */
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reg_placeholder: regulator-0 {
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compatible = "regulator-fixed";
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regulator-name = "placeholder_reg";
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};
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/* TODO: Remove this once S2MPG11 slave PMIC is implemented */
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ufs_0_fixed_vcc_reg: regulator-1 {
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compatible = "regulator-fixed";
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regulator-name = "ufs-vcc";
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gpio = <&gpp0 1 GPIO_ACTIVE_HIGH>;
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regulator-boot-on;
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enable-active-high;
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};
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};
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&ext_24_5m {
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@ -106,6 +121,33 @@
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status = "okay";
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};
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&ufs_0 {
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status = "okay";
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vcc-supply = <&ufs_0_fixed_vcc_reg>;
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};
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&ufs_0_phy {
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status = "okay";
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};
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&usbdrd31 {
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status = "okay";
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vdd10-supply = <®_placeholder>;
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vdd33-supply = <®_placeholder>;
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};
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&usbdrd31_dwc3 {
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dr_mode = "otg";
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usb-role-switch;
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role-switch-default-mode = "peripheral";
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maximum-speed = "super-speed-plus";
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status = "okay";
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};
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&usbdrd31_phy {
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status = "okay";
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};
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&usi_uart {
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samsung,clkreq-on; /* needed for UART mode */
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status = "okay";
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@ -370,6 +370,8 @@
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pinctrl_peric0: pinctrl@10840000 {
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compatible = "google,gs101-pinctrl";
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reg = <0x10840000 0x00001000>;
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clocks = <&cmu_peric0 CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK>;
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clock-names = "pclk";
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interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>;
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};
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@ -914,6 +916,8 @@
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pinctrl_peric1: pinctrl@10c40000 {
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compatible = "google,gs101-pinctrl";
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reg = <0x10c40000 0x00001000>;
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clocks = <&cmu_peric1 CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK>;
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clock-names = "pclk";
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interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
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};
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@ -1247,18 +1251,132 @@
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};
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};
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cmu_hsi0: clock-controller@11000000 {
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compatible = "google,gs101-cmu-hsi0";
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reg = <0x11000000 0x4000>;
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#clock-cells = <1>;
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clocks = <&ext_24_5m>,
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<&cmu_top CLK_DOUT_CMU_HSI0_BUS>,
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<&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>,
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<&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>,
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<&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>;
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clock-names = "oscclk", "bus", "dpgtc", "usb31drd",
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"usbdpdbg";
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};
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usbdrd31_phy: phy@11100000 {
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compatible = "google,gs101-usb31drd-phy";
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reg = <0x11100000 0x0100>,
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<0x110f0000 0x0800>,
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<0x110e0000 0x2800>;
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reg-names = "phy", "pcs", "pma";
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clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL>,
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<&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26>,
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<&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK>,
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<&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK>,
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<&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK>;
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clock-names = "phy", "ref", "ctrl_aclk", "ctrl_pclk", "scl_pclk";
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samsung,pmu-syscon = <&pmu_system_controller>;
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#phy-cells = <1>;
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status = "disabled";
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};
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usbdrd31: usb@11110000 {
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compatible = "google,gs101-dwusb3";
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clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>,
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<&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26>,
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<&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK>,
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<&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK>;
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clock-names = "bus_early", "susp_clk", "link_aclk", "link_pclk";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x11110000 0x10000>;
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status = "disabled";
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usbdrd31_dwc3: usb@0 {
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compatible = "snps,dwc3";
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clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40>;
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clock-names = "ref";
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reg = <0x0 0x10000>;
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interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>;
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phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>;
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phy-names = "usb2-phy", "usb3-phy";
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status = "disabled";
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};
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};
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pinctrl_hsi1: pinctrl@11840000 {
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compatible = "google,gs101-pinctrl";
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reg = <0x11840000 0x00001000>;
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/* TODO: update once support for this CMU exists */
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clocks = <0>;
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clock-names = "pclk";
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interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
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};
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cmu_hsi2: clock-controller@14400000 {
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compatible = "google,gs101-cmu-hsi2";
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reg = <0x14400000 0x4000>;
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#clock-cells = <1>;
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clocks = <&ext_24_5m>,
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<&cmu_top CLK_DOUT_CMU_HSI2_BUS>,
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<&cmu_top CLK_DOUT_CMU_HSI2_PCIE>,
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<&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>,
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<&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>;
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clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";
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};
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sysreg_hsi2: syscon@14420000 {
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compatible = "google,gs101-hsi2-sysreg", "syscon";
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reg = <0x14420000 0x10000>;
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clocks = <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>;
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};
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pinctrl_hsi2: pinctrl@14440000 {
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compatible = "google,gs101-pinctrl";
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reg = <0x14440000 0x00001000>;
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clocks = <&cmu_hsi2 CLK_GOUT_HSI2_GPIO_HSI2_PCLK>;
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clock-names = "pclk";
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interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
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};
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ufs_0: ufs@14700000 {
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compatible = "google,gs101-ufs";
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reg = <0x14700000 0x200>,
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<0x14701100 0x200>,
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<0x14780000 0xa000>,
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<0x14600000 0x100>;
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reg-names = "hci", "vs_hci", "unipro", "ufsp";
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interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>,
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<&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>,
|
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<&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>,
|
||||
<&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>,
|
||||
<&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>,
|
||||
<&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>;
|
||||
clock-names = "core_clk", "sclk_unipro_main", "fmp",
|
||||
"aclk", "pclk", "sysreg";
|
||||
freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>;
|
||||
pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
|
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pinctrl-names = "default";
|
||||
phys = <&ufs_0_phy>;
|
||||
phy-names = "ufs-phy";
|
||||
samsung,sysreg = <&sysreg_hsi2 0x710>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ufs_0_phy: phy@14704000 {
|
||||
compatible = "google,gs101-ufs-phy";
|
||||
reg = <0x14704000 0x3000>;
|
||||
reg-names = "phy-pma";
|
||||
samsung,pmu-syscon = <&pmu_system_controller>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&ext_24_5m>;
|
||||
clock-names = "ref_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cmu_apm: clock-controller@17400000 {
|
||||
compatible = "google,gs101-cmu-apm";
|
||||
reg = <0x17400000 0x8000>;
|
||||
@ -1281,6 +1399,8 @@
|
||||
pinctrl_gpio_alive: pinctrl@174d0000 {
|
||||
compatible = "google,gs101-pinctrl";
|
||||
reg = <0x174d0000 0x00001000>;
|
||||
clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK>;
|
||||
clock-names = "pclk";
|
||||
|
||||
wakeup-interrupt-controller {
|
||||
compatible = "google,gs101-wakeup-eint",
|
||||
@ -1292,6 +1412,8 @@
|
||||
pinctrl_far_alive: pinctrl@174e0000 {
|
||||
compatible = "google,gs101-pinctrl";
|
||||
reg = <0x174e0000 0x00001000>;
|
||||
clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK>;
|
||||
clock-names = "pclk";
|
||||
|
||||
wakeup-interrupt-controller {
|
||||
compatible = "google,gs101-wakeup-eint",
|
||||
@ -1303,11 +1425,17 @@
|
||||
pinctrl_gsactrl: pinctrl@17940000 {
|
||||
compatible = "google,gs101-pinctrl";
|
||||
reg = <0x17940000 0x00001000>;
|
||||
/* TODO: update once support for this CMU exists */
|
||||
clocks = <0>;
|
||||
clock-names = "pclk";
|
||||
};
|
||||
|
||||
pinctrl_gsacore: pinctrl@17a80000 {
|
||||
compatible = "google,gs101-pinctrl";
|
||||
reg = <0x17a80000 0x00001000>;
|
||||
/* TODO: update once support for this CMU exists */
|
||||
clocks = <0>;
|
||||
clock-names = "pclk";
|
||||
};
|
||||
|
||||
cmu_top: clock-controller@1e080000 {
|
||||
|
||||
@ -313,6 +313,122 @@
|
||||
#define CLK_APM_PLL_DIV4_APM 70
|
||||
#define CLK_APM_PLL_DIV16_APM 71
|
||||
|
||||
/* CMU_HSI0 */
|
||||
#define CLK_FOUT_USB_PLL 1
|
||||
#define CLK_MOUT_PLL_USB 2
|
||||
#define CLK_MOUT_HSI0_ALT_USER 3
|
||||
#define CLK_MOUT_HSI0_BUS_USER 4
|
||||
#define CLK_MOUT_HSI0_DPGTC_USER 5
|
||||
#define CLK_MOUT_HSI0_TCXO_USER 6
|
||||
#define CLK_MOUT_HSI0_USB20_USER 7
|
||||
#define CLK_MOUT_HSI0_USB31DRD_USER 8
|
||||
#define CLK_MOUT_HSI0_USBDPDBG_USER 9
|
||||
#define CLK_MOUT_HSI0_BUS 10
|
||||
#define CLK_MOUT_HSI0_USB20_REF 11
|
||||
#define CLK_MOUT_HSI0_USB31DRD 12
|
||||
#define CLK_DOUT_HSI0_USB31DRD 13
|
||||
#define CLK_GOUT_HSI0_PCLK 14
|
||||
#define CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26 15
|
||||
#define CLK_GOUT_HSI0_CLK_HSI0_ALT 16
|
||||
#define CLK_GOUT_HSI0_DP_LINK_I_DP_GTC_CLK 17
|
||||
#define CLK_GOUT_HSI0_DP_LINK_I_PCLK 18
|
||||
#define CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK 19
|
||||
#define CLK_GOUT_HSI0_ETR_MIU_I_ACLK 20
|
||||
#define CLK_GOUT_HSI0_ETR_MIU_I_PCLK 21
|
||||
#define CLK_GOUT_HSI0_GPC_HSI0_PCLK 22
|
||||
#define CLK_GOUT_HSI0_LHM_AXI_G_ETR_HSI0_I_CLK 23
|
||||
#define CLK_GOUT_HSI0_LHM_AXI_P_AOCHSI0_I_CLK 24
|
||||
#define CLK_GOUT_HSI0_LHM_AXI_P_HSI0_I_CLK 25
|
||||
#define CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_I_CLK 26
|
||||
#define CLK_GOUT_HSI0_LHS_AXI_D_HSI0AOC_I_CLK 27
|
||||
#define CLK_GOUT_HSI0_PPMU_HSI0_AOC_ACLK 28
|
||||
#define CLK_GOUT_HSI0_PPMU_HSI0_AOC_PCLK 29
|
||||
#define CLK_GOUT_HSI0_PPMU_HSI0_BUS0_ACLK 30
|
||||
#define CLK_GOUT_HSI0_PPMU_HSI0_BUS0_PCLK 31
|
||||
#define CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK 32
|
||||
#define CLK_GOUT_HSI0_SSMT_USB_ACLK 33
|
||||
#define CLK_GOUT_HSI0_SSMT_USB_PCLK 34
|
||||
#define CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2 35
|
||||
#define CLK_GOUT_HSI0_SYSREG_HSI0_PCLK 36
|
||||
#define CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK 37
|
||||
#define CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK 38
|
||||
#define CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK 39
|
||||
#define CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK 40
|
||||
#define CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL 41
|
||||
#define CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY 42
|
||||
#define CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26 43
|
||||
#define CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40 44
|
||||
#define CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_REF_SOC_PLL 45
|
||||
#define CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK 46
|
||||
#define CLK_GOUT_HSI0_USB31DRD_I_USBPCS_APB_CLK 47
|
||||
#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_I_ACLK 48
|
||||
#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_UDBG_I_APB_PCLK 49
|
||||
#define CLK_GOUT_HSI0_XIU_D0_HSI0_ACLK 50
|
||||
#define CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK 51
|
||||
#define CLK_GOUT_HSI0_XIU_P_HSI0_ACLK 52
|
||||
|
||||
/* CMU_HSI2 */
|
||||
#define CLK_MOUT_HSI2_BUS_USER 1
|
||||
#define CLK_MOUT_HSI2_MMC_CARD_USER 2
|
||||
#define CLK_MOUT_HSI2_PCIE_USER 3
|
||||
#define CLK_MOUT_HSI2_UFS_EMBD_USER 4
|
||||
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_PHY_REFCLK_IN 5
|
||||
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_PHY_REFCLK_IN 6
|
||||
#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_ACLK 7
|
||||
#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_PCLK 8
|
||||
#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_ACLK 9
|
||||
#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_PCLK 10
|
||||
#define CLK_GOUT_HSI2_D_TZPC_HSI2_PCLK 11
|
||||
#define CLK_GOUT_HSI2_GPC_HSI2_PCLK 12
|
||||
#define CLK_GOUT_HSI2_GPIO_HSI2_PCLK 13
|
||||
#define CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK 14
|
||||
#define CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK 15
|
||||
#define CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK 16
|
||||
#define CLK_GOUT_HSI2_MMC_CARD_I_ACLK 17
|
||||
#define CLK_GOUT_HSI2_MMC_CARD_SDCLKIN 18
|
||||
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_DBI_ACLK_UG 19
|
||||
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_MSTR_ACLK_UG 20
|
||||
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_SLV_ACLK_UG 21
|
||||
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_I_DRIVER_APB_CLK 22
|
||||
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_DBI_ACLK_UG 23
|
||||
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_MSTR_ACLK_UG 24
|
||||
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_SLV_ACLK_UG 25
|
||||
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_I_DRIVER_APB_CLK 26
|
||||
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PHY_UDBG_I_APB_PCLK 27
|
||||
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PIPE_PAL_PCIE_I_APB_PCLK 28
|
||||
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PCIEPHY210X2_QCH_I_APB_PCLK 29
|
||||
#define CLK_GOUT_HSI2_PCIE_IA_GEN4A_1_I_CLK 30
|
||||
#define CLK_GOUT_HSI2_PCIE_IA_GEN4B_1_I_CLK 31
|
||||
#define CLK_GOUT_HSI2_PPMU_HSI2_ACLK 32
|
||||
#define CLK_GOUT_HSI2_PPMU_HSI2_PCLK 33
|
||||
#define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_ACLK 34
|
||||
#define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_PCLK 35
|
||||
#define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_ACLK 36
|
||||
#define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_PCLK 37
|
||||
#define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_ACLK 38
|
||||
#define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_PCLK 39
|
||||
#define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK 40
|
||||
#define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK 41
|
||||
#define CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK 42
|
||||
#define CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK 43
|
||||
#define CLK_GOUT_HSI2_SSMT_HSI2_ACLK 44
|
||||
#define CLK_GOUT_HSI2_SSMT_HSI2_PCLK 45
|
||||
#define CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2 46
|
||||
#define CLK_GOUT_HSI2_SYSREG_HSI2_PCLK 47
|
||||
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK 48
|
||||
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_PCLK 49
|
||||
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_ACLK 50
|
||||
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_PCLK 51
|
||||
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_ACLK 52
|
||||
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_PCLK 53
|
||||
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_ACLK 54
|
||||
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_PCLK 55
|
||||
#define CLK_GOUT_HSI2_UFS_EMBD_I_ACLK 56
|
||||
#define CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO 57
|
||||
#define CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK 58
|
||||
#define CLK_GOUT_HSI2_XIU_D_HSI2_ACLK 59
|
||||
#define CLK_GOUT_HSI2_XIU_P_HSI2_ACLK 60
|
||||
|
||||
/* CMU_MISC */
|
||||
#define CLK_MOUT_MISC_BUS_USER 1
|
||||
#define CLK_MOUT_MISC_SSS_USER 2
|
||||
|
||||
Loading…
Reference in New Issue
Block a user