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msm: irq: rename existing entry-macro to entry-macro-vic
The existing MSM irq entry macro is specific to a VIC implementation. Renaming this makes room for irq support based on other interrupt controllers. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
This commit is contained in:
Steve Muckle
Daniel Walker
parent
a55df6edcf
commit
f880c5649e
88
arch/arm/mach-msm/include/mach/entry-macro-qgic.S
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88
arch/arm/mach-msm/include/mach/entry-macro-qgic.S
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@ -0,0 +1,88 @@
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/*
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* Low-level IRQ helper macros
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*
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* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/hardware.h>
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#include <asm/hardware/gic.h>
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =gic_cpu_base_addr
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ldr \base, [\base]
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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/*
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* The interrupt numbering scheme is defined in the
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* interrupt controller spec. To wit:
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*
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* Migrated the code from ARM MP port to be more consistant
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* with interrupt processing , the following still holds true
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* however, all interrupts are treated the same regardless of
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* if they are local IPI or PPI
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*
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* Interrupts 0-15 are IPI
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* 16-31 are PPI
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* (16-18 are the timers)
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* 32-1020 are global
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* 1021-1022 are reserved
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* 1023 is "spurious" (no interrupt)
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*
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* A simple read from the controller will tell us the number of the
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* highest priority enabled interrupt. We then just need to check
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* whether it is in the valid range for an IRQ (0-1020 inclusive).
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*
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* Base ARM code assumes that the local (private) peripheral interrupts
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* are not valid, we treat them differently, in that the privates are
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* handled like normal shared interrupts with the exception that only
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* one processor can register the interrupt and the handler must be
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* the same for all processors.
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*/
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 =srcCPU,
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9-0 =int # */
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bic \irqnr, \irqstat, #0x1c00 @mask src
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cmp \irqnr, #15
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ldr \tmp, =1021
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cmpcc \irqnr, \irqnr
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cmpne \irqnr, \tmp
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cmpcs \irqnr, \irqnr
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.endm
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/* We assume that irqstat (the raw value of the IRQ acknowledge
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* register) is preserved from the macro above.
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* If there is an IPI, we immediately signal end of interrupt on the
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* controller, since this requires the original irqstat value which
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* we won't easily be able to recreate later.
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*/
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.macro test_for_ipi, irqnr, irqstat, base, tmp
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bic \irqnr, \irqstat, #0x1c00
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cmp \irqnr, #16
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strcc \irqstat, [\base, #GIC_CPU_EOI]
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cmpcs \irqnr, \irqnr
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.endm
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/* As above, this assumes that irqstat and base are preserved.. */
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.macro test_for_ltirq, irqnr, irqstat, base, tmp
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bic \irqnr, \irqstat, #0x1c00
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mov \tmp, #0
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cmp \irqnr, #16
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moveq \tmp, #1
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streq \irqstat, [\base, #GIC_CPU_EOI]
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cmp \tmp, #0
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.endm
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37
arch/arm/mach-msm/include/mach/entry-macro-vic.S
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37
arch/arm/mach-msm/include/mach/entry-macro-vic.S
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@ -0,0 +1,37 @@
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/*
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* Copyright (C) 2007 Google, Inc.
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* Author: Brian Swetland <swetland@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <mach/msm_iomap.h>
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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@ enable imprecise aborts
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cpsie a
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mov \base, #MSM_VIC_BASE
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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@ 0xD0 has irq# or old irq# if the irq has been handled
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@ 0xD4 has irq# or -1 if none pending *but* if you just
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@ read 0xD4 you never get the first irq for some reason
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ldr \irqnr, [\base, #0xD0]
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ldr \irqnr, [\base, #0xD4]
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cmp \irqnr, #0xffffffff
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.endm
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@ -1,38 +1,23 @@
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/* arch/arm/mach-msm7200/include/mach/entry-macro.S
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/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
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*
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* Copyright (C) 2007 Google, Inc.
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* Author: Brian Swetland <swetland@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*
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*/
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#include <mach/msm_iomap.h>
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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@ enable imprecise aborts
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cpsie a
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mov \base, #MSM_VIC_BASE
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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@ 0xD0 has irq# or old irq# if the irq has been handled
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@ 0xD4 has irq# or -1 if none pending *but* if you just
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@ read 0xD4 you never get the first irq for some reason
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ldr \irqnr, [\base, #0xD0]
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ldr \irqnr, [\base, #0xD4]
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cmp \irqnr, #0xffffffff
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.endm
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#if defined(CONFIG_ARM_GIC)
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#include <mach/entry-macro-qgic.S>
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#else
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#include <mach/entry-macro-vic.S>
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#endif
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39
arch/arm/mach-msm/include/mach/smp.h
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39
arch/arm/mach-msm/include/mach/smp.h
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/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Code Aurora nor
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* the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef __ASM_ARCH_MSM_SMP_H
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#define __ASM_ARCH_MSM_SMP_H
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#include <asm/hardware/gic.h>
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static inline void smp_cross_call(const struct cpumask *mask)
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{
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gic_raise_softirq(mask, 1);
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}
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#endif
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