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Renesas ARM Based SoC Drivers Updates for v4.14
Add R-Car D3 (r8a77995) support to the Renesas-specific SoC drivers - SoC identification - System controller - Reset controller -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJZf0DrAAoJENfPZGlqN0++LacP/jcymVeUMDpkkPTcoM6b37Qq ADSDdiR+1Szu29wtfNDTFUoAlh4UvlpAN93GGJLZ/iYsMDyZYIhcUhnE4l119fdy 6iMwDhctXHlQ8VNhY0Z9MUXZyyN2Fu/9L2ZDJ2briM2xoNiMgdUYvMlsZI8ZaN1/ JRmfP+lzCM25Rkdi9sLYolj8szaxbW9RgLBgvXD7ERJ5bsJRKGs6aDrJ2AXMZpwn BVOeughlPTxvv+NVFA1qZXWh63/7RjW5t6OMgHw3eNOABKv+o5YfdqOZAa8PHgn9 LhNAkR90Il9hsGesWwHMKPuCgGHE0R/2nQppWM0xBWO/HfMRnpx8DEt+em/Kjpep uxex+bqMOJB0GksVWPM73ci1CQmQxKS6xrTXeTE9kiN+6WD+b0Fsntoz2XN62uJO df0z46N6T3I4jFc00vOBnXxCdgDCBCJLxtU8NFg8jzmGP+NkKxxYiwCEs1auKlLF CUVX+o8H4V9FKnD3h0/mNsNyw/gCw6TWXlyr/Ba6AjBuZ8TghhMjQ+zbY+xCN9sb IFONbr69pVBJ9N2ssGWdf2iLfa+JNcaJdEPZUkumgUlZ9M5RgS+yg3YoTFtlAO6R JN2uP1E20qBLlrvAu7pv9HQEim80RyDT2DU2a1qFNx32vhqfl6g3sccJJvGpzodj 7y7per6KkpvUGrck0kAI =AO// -----END PGP SIGNATURE----- Merge tag 'renesas-drivers-for-v4.14' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers Pull "Renesas ARM Based SoC Drivers Updates for v4.14" from Simon Horman: Add R-Car D3 (r8a77995) support to the Renesas-specific SoC drivers - SoC identification - System controller - Reset controller * tag 'renesas-drivers-for-v4.14' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: soc: renesas: rcar-rst: Add support for R-Car D3 soc: renesas: rcar-sysc: Add support for R-Car D3 power areas soc: renesas: Add r8a77995 SYSC PM Domain Binding Definitions soc: renesas: Identify R-Car D3
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commit
f822e60085
@ -17,6 +17,7 @@ Required properties:
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- "renesas,r8a7794-sysc" (R-Car E2)
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- "renesas,r8a7795-sysc" (R-Car H3)
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- "renesas,r8a7796-sysc" (R-Car M3-W)
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- "renesas,r8a77995-sysc" (R-Car D3)
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- reg: Address start and address range for the device.
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- #power-domain-cells: Must be 1.
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@ -26,6 +26,7 @@ Required properties:
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- "renesas,r8a7794-rst" (R-Car E2)
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- "renesas,r8a7795-rst" (R-Car H3)
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- "renesas,r8a7796-rst" (R-Car M3-W)
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- "renesas,r8a77995-rst" (R-Car D3)
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- reg: Address start and address range for the device.
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@ -3,7 +3,7 @@ config SOC_RENESAS
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default y if ARCH_RENESAS
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select SOC_BUS
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select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \
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ARCH_R8A7795 || ARCH_R8A7796
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ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A77995
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select SYSC_R8A7743 if ARCH_R8A7743
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select SYSC_R8A7745 if ARCH_R8A7745
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select SYSC_R8A7779 if ARCH_R8A7779
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@ -13,6 +13,7 @@ config SOC_RENESAS
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select SYSC_R8A7794 if ARCH_R8A7794
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select SYSC_R8A7795 if ARCH_R8A7795
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select SYSC_R8A7796 if ARCH_R8A7796
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select SYSC_R8A77995 if ARCH_R8A77995
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if SOC_RENESAS
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@ -53,6 +54,10 @@ config SYSC_R8A7796
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bool "R-Car M3-W System Controller support" if COMPILE_TEST
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select SYSC_RCAR
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config SYSC_R8A77995
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bool "R-Car D3 System Controller support" if COMPILE_TEST
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select SYSC_RCAR
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# Family
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config RST_RCAR
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bool "R-Car Reset Controller support" if COMPILE_TEST
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@ -11,6 +11,7 @@ obj-$(CONFIG_SYSC_R8A7792) += r8a7792-sysc.o
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obj-$(CONFIG_SYSC_R8A7794) += r8a7794-sysc.o
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obj-$(CONFIG_SYSC_R8A7795) += r8a7795-sysc.o
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obj-$(CONFIG_SYSC_R8A7796) += r8a7796-sysc.o
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obj-$(CONFIG_SYSC_R8A77995) += r8a77995-sysc.o
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# Family
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obj-$(CONFIG_RST_RCAR) += rcar-rst.o
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31
drivers/soc/renesas/r8a77995-sysc.c
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31
drivers/soc/renesas/r8a77995-sysc.c
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@ -0,0 +1,31 @@
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/*
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* Renesas R-Car D3 System Controller
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*
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* Copyright (C) 2017 Glider bvba
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#include <linux/bug.h>
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#include <linux/kernel.h>
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#include <linux/sys_soc.h>
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#include <dt-bindings/power/r8a77995-sysc.h>
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#include "rcar-sysc.h"
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static struct rcar_sysc_area r8a77995_areas[] __initdata = {
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{ "always-on", 0, 0, R8A77995_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
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{ "ca53-scu", 0x140, 0, R8A77995_PD_CA53_SCU, R8A77995_PD_ALWAYS_ON,
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PD_SCU },
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{ "ca53-cpu0", 0x200, 0, R8A77995_PD_CA53_CPU0, R8A77995_PD_CA53_SCU,
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PD_CPU_NOCR },
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};
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const struct rcar_sysc_info r8a77995_sysc_info __initconst = {
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.areas = r8a77995_areas,
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.num_areas = ARRAY_SIZE(r8a77995_areas),
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};
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@ -41,6 +41,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
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/* R-Car Gen3 is handled like R-Car Gen2 */
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{ .compatible = "renesas,r8a7795-rst", .data = &rcar_rst_gen2 },
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{ .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen2 },
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{ .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen2 },
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{ /* sentinel */ }
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};
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@ -283,6 +283,9 @@ static const struct of_device_id rcar_sysc_matches[] = {
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#endif
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#ifdef CONFIG_SYSC_R8A7796
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{ .compatible = "renesas,r8a7796-sysc", .data = &r8a7796_sysc_info },
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#endif
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#ifdef CONFIG_SYSC_R8A77995
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{ .compatible = "renesas,r8a77995-sysc", .data = &r8a77995_sysc_info },
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#endif
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{ /* sentinel */ }
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};
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@ -58,6 +58,7 @@ extern const struct rcar_sysc_info r8a7792_sysc_info;
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extern const struct rcar_sysc_info r8a7794_sysc_info;
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extern const struct rcar_sysc_info r8a7795_sysc_info;
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extern const struct rcar_sysc_info r8a7796_sysc_info;
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extern const struct rcar_sysc_info r8a77995_sysc_info;
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/*
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@ -144,6 +144,11 @@ static const struct renesas_soc soc_rcar_m3_w __initconst __maybe_unused = {
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.id = 0x52,
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};
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static const struct renesas_soc soc_rcar_d3 __initconst __maybe_unused = {
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.family = &fam_rcar_gen3,
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.id = 0x58,
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};
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static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = {
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.family = &fam_shmobile,
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.id = 0x37,
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@ -199,6 +204,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
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#ifdef CONFIG_ARCH_R8A7796
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{ .compatible = "renesas,r8a7796", .data = &soc_rcar_m3_w },
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#endif
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#ifdef CONFIG_ARCH_R8A77995
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{ .compatible = "renesas,r8a77995", .data = &soc_rcar_d3 },
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#endif
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#ifdef CONFIG_ARCH_SH73A0
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{ .compatible = "renesas,sh73a0", .data = &soc_shmobile_ag5 },
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#endif
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include/dt-bindings/power/r8a77995-sysc.h
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23
include/dt-bindings/power/r8a77995-sysc.h
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@ -0,0 +1,23 @@
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/*
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* Copyright (C) 2017 Glider bvba
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__
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#define __DT_BINDINGS_POWER_R8A77995_SYSC_H__
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/*
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* These power domain indices match the numbers of the interrupt bits
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* representing the power areas in the various Interrupt Registers
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* (e.g. SYSCISR, Interrupt Status Register)
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*/
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#define R8A77995_PD_CA53_CPU0 5
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#define R8A77995_PD_CA53_SCU 21
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/* Always-on power area */
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#define R8A77995_PD_ALWAYS_ON 32
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#endif /* __DT_BINDINGS_POWER_R8A77995_SYSC_H__ */
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