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drm/i915: access VLV regs through read/write switch
Since the offsets have all moved around. v2: switch IS_DISPLAYREG and IS_VALLEYVIEW checks around since the latter is cheaper (Daniel) bail out early in IS_DISPLAYREG if the reg is in the new range (Daniel) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [danvet: Fixup if cascading fail that broke HAS_FORCEWAKE machines.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1146,6 +1146,84 @@ MODULE_LICENSE("GPL and additional rights");
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((reg) != FORCEWAKE)) && \
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(!IS_VALLEYVIEW((dev_priv)->dev))
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static bool IS_DISPLAYREG(u32 reg)
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{
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/*
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* This should make it easier to transition modules over to the
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* new register block scheme, since we can do it incrementally.
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*/
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if (reg >= 0x180000)
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return false;
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if (reg >= RENDER_RING_BASE &&
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reg < RENDER_RING_BASE + 0xff)
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return false;
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if (reg >= GEN6_BSD_RING_BASE &&
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reg < GEN6_BSD_RING_BASE + 0xff)
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return false;
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if (reg >= BLT_RING_BASE &&
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reg < BLT_RING_BASE + 0xff)
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return false;
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if (reg == PGTBL_ER)
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return false;
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if (reg >= IPEIR_I965 &&
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reg < HWSTAM)
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return false;
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if (reg == MI_MODE)
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return false;
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if (reg == GFX_MODE_GEN7)
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return false;
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if (reg == RENDER_HWS_PGA_GEN7 ||
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reg == BSD_HWS_PGA_GEN7 ||
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reg == BLT_HWS_PGA_GEN7)
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return false;
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if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
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reg == GEN6_BSD_RNCID)
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return false;
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if (reg == GEN6_BLITTER_ECOSKPD)
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return false;
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if (reg >= 0x4000c &&
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reg <= 0x4002c)
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return false;
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if (reg >= 0x4f000 &&
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reg <= 0x4f08f)
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return false;
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if (reg >= 0x4f100 &&
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reg <= 0x4f11f)
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return false;
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if (reg >= VLV_MASTER_IER &&
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reg <= GEN6_PMIER)
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return false;
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if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
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reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
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return false;
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if (reg >= VLV_IIR_RW &&
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reg <= VLV_ISR)
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return false;
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if (reg == FORCEWAKE_VLV ||
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reg == FORCEWAKE_ACK_VLV)
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return false;
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if (reg == GEN6_GDRST)
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return false;
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return true;
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}
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#define __i915_read(x, y) \
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u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
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u##x val = 0; \
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@ -1158,6 +1236,8 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
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if (dev_priv->forcewake_count == 0) \
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dev_priv->display.force_wake_put(dev_priv); \
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spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
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} else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
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val = read##y(dev_priv->regs + reg + 0x180000); \
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} else { \
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val = read##y(dev_priv->regs + reg); \
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} \
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@ -1178,7 +1258,11 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
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if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
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__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
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} \
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write##y(val, dev_priv->regs + reg); \
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if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
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write##y(val, dev_priv->regs + reg + 0x180000); \
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} else { \
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write##y(val, dev_priv->regs + reg); \
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} \
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if (unlikely(__fifo_ret)) { \
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gen6_gt_check_fifodbg(dev_priv); \
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} \
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