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ASoC: Intel: Add Intel Baytrail SST DSP support
This adds basic functionality for Baytrail SST DSP initialization and firmware loading. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Acked-by: Liam Girdwood <liam.r.girdwood@intel.com> Signed-off-by: Mark Brown <broonie@linaro.org>
This commit is contained in:
Jarkko Nikula
Mark Brown
parent
6ef20de726
commit
f746966377
372
sound/soc/intel/sst-baytrail-dsp.c
Normal file
372
sound/soc/intel/sst-baytrail-dsp.c
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@ -0,0 +1,372 @@
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/*
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* Intel Baytrail SST DSP driver
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* Copyright (c) 2014, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/delay.h>
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#include <linux/fs.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/firmware.h>
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#include "sst-dsp.h"
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#include "sst-dsp-priv.h"
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#include "sst-baytrail-ipc.h"
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#define SST_BYT_FW_SIGNATURE_SIZE 4
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#define SST_BYT_FW_SIGN "$SST"
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#define SST_BYT_IRAM_OFFSET 0xC0000
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#define SST_BYT_DRAM_OFFSET 0x100000
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#define SST_BYT_SHIM_OFFSET 0x140000
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enum sst_ram_type {
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SST_BYT_IRAM = 1,
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SST_BYT_DRAM = 2,
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SST_BYT_CACHE = 3,
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};
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struct dma_block_info {
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enum sst_ram_type type; /* IRAM/DRAM */
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u32 size; /* Bytes */
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u32 ram_offset; /* Offset in I/DRAM */
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u32 rsvd; /* Reserved field */
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};
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struct fw_header {
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unsigned char signature[SST_BYT_FW_SIGNATURE_SIZE];
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u32 file_size; /* size of fw minus this header */
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u32 modules; /* # of modules */
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u32 file_format; /* version of header format */
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u32 reserved[4];
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};
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struct sst_byt_fw_module_header {
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unsigned char signature[SST_BYT_FW_SIGNATURE_SIZE];
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u32 mod_size; /* size of module */
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u32 blocks; /* # of blocks */
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u32 type; /* codec type, pp lib */
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u32 entry_point;
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};
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static int sst_byt_parse_module(struct sst_dsp *dsp, struct sst_fw *fw,
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struct sst_byt_fw_module_header *module)
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{
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struct dma_block_info *block;
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struct sst_module *mod;
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struct sst_module_data block_data;
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struct sst_module_template template;
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int count;
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memset(&template, 0, sizeof(template));
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template.id = module->type;
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template.entry = module->entry_point;
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template.p.type = SST_MEM_DRAM;
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template.p.data_type = SST_DATA_P;
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template.s.type = SST_MEM_DRAM;
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template.s.data_type = SST_DATA_S;
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mod = sst_module_new(fw, &template, NULL);
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if (mod == NULL)
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return -ENOMEM;
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block = (void *)module + sizeof(*module);
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for (count = 0; count < module->blocks; count++) {
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if (block->size <= 0) {
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dev_err(dsp->dev, "block %d size invalid\n", count);
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return -EINVAL;
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}
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switch (block->type) {
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case SST_BYT_IRAM:
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block_data.offset = block->ram_offset +
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dsp->addr.iram_offset;
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block_data.type = SST_MEM_IRAM;
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break;
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case SST_BYT_DRAM:
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block_data.offset = block->ram_offset +
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dsp->addr.dram_offset;
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block_data.type = SST_MEM_DRAM;
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break;
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case SST_BYT_CACHE:
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block_data.offset = block->ram_offset +
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(dsp->addr.fw_ext - dsp->addr.lpe);
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block_data.type = SST_MEM_CACHE;
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break;
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default:
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dev_err(dsp->dev, "wrong ram type 0x%x in block0x%x\n",
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block->type, count);
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return -EINVAL;
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}
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block_data.size = block->size;
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block_data.data_type = SST_DATA_M;
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block_data.data = (void *)block + sizeof(*block);
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sst_module_insert_fixed_block(mod, &block_data);
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block = (void *)block + sizeof(*block) + block->size;
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}
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return 0;
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}
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static int sst_byt_parse_fw_image(struct sst_fw *sst_fw)
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{
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struct fw_header *header;
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struct sst_byt_fw_module_header *module;
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struct sst_dsp *dsp = sst_fw->dsp;
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int ret, count;
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/* Read the header information from the data pointer */
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header = (struct fw_header *)sst_fw->dma_buf;
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/* verify FW */
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if ((strncmp(header->signature, SST_BYT_FW_SIGN, 4) != 0) ||
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(sst_fw->size != header->file_size + sizeof(*header))) {
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/* Invalid FW signature */
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dev_err(dsp->dev, "Invalid FW sign/filesize mismatch\n");
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return -EINVAL;
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}
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dev_dbg(dsp->dev,
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"header sign=%4s size=0x%x modules=0x%x fmt=0x%x size=%zu\n",
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header->signature, header->file_size, header->modules,
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header->file_format, sizeof(*header));
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module = (void *)sst_fw->dma_buf + sizeof(*header);
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for (count = 0; count < header->modules; count++) {
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/* module */
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ret = sst_byt_parse_module(dsp, sst_fw, module);
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if (ret < 0) {
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dev_err(dsp->dev, "invalid module %d\n", count);
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return ret;
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}
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module = (void *)module + sizeof(*module) + module->mod_size;
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}
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return 0;
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}
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static void sst_byt_dump_shim(struct sst_dsp *sst)
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{
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int i;
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u64 reg;
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for (i = 0; i <= 0xF0; i += 8) {
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reg = sst_dsp_shim_read64_unlocked(sst, i);
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if (reg)
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dev_dbg(sst->dev, "shim 0x%2.2x value 0x%16.16llx\n",
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i, reg);
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}
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for (i = 0x00; i <= 0xff; i += 4) {
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reg = readl(sst->addr.pci_cfg + i);
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if (reg)
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dev_dbg(sst->dev, "pci 0x%2.2x value 0x%8.8x\n",
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i, (u32)reg);
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}
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}
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static irqreturn_t sst_byt_irq(int irq, void *context)
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{
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struct sst_dsp *sst = (struct sst_dsp *) context;
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u64 isrx;
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irqreturn_t ret = IRQ_NONE;
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spin_lock(&sst->spinlock);
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isrx = sst_dsp_shim_read64_unlocked(sst, SST_ISRX);
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if (isrx & SST_ISRX_DONE) {
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/* ADSP has processed the message request from IA */
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sst_dsp_shim_update_bits64_unlocked(sst, SST_IPCX,
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SST_BYT_IPCX_DONE, 0);
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ret = IRQ_WAKE_THREAD;
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}
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if (isrx & SST_BYT_ISRX_REQUEST) {
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/* mask message request from ADSP and do processing later */
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sst_dsp_shim_update_bits64_unlocked(sst, SST_IMRX,
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SST_BYT_IMRX_REQUEST,
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SST_BYT_IMRX_REQUEST);
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ret = IRQ_WAKE_THREAD;
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}
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spin_unlock(&sst->spinlock);
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return ret;
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}
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static void sst_byt_boot(struct sst_dsp *sst)
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{
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int tries = 10;
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/* release stall and wait to unstall */
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sst_dsp_shim_update_bits64(sst, SST_CSR, SST_BYT_CSR_STALL, 0x0);
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while (tries--) {
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if (!(sst_dsp_shim_read64(sst, SST_CSR) &
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SST_BYT_CSR_PWAITMODE))
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break;
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msleep(100);
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}
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if (tries < 0) {
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dev_err(sst->dev, "unable to start DSP\n");
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sst_byt_dump_shim(sst);
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}
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}
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static void sst_byt_reset(struct sst_dsp *sst)
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{
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/* put DSP into reset, set reset vector and stall */
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sst_dsp_shim_update_bits64(sst, SST_CSR,
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SST_BYT_CSR_RST | SST_BYT_CSR_VECTOR_SEL | SST_BYT_CSR_STALL,
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SST_BYT_CSR_RST | SST_BYT_CSR_VECTOR_SEL | SST_BYT_CSR_STALL);
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udelay(10);
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/* take DSP out of reset and keep stalled for FW loading */
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sst_dsp_shim_update_bits64(sst, SST_CSR, SST_BYT_CSR_RST, 0);
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}
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struct sst_adsp_memregion {
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u32 start;
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u32 end;
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int blocks;
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enum sst_mem_type type;
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};
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/* BYT test stuff */
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static const struct sst_adsp_memregion byt_region[] = {
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{0xC0000, 0x100000, 8, SST_MEM_IRAM}, /* I-SRAM - 8 * 32kB */
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{0x100000, 0x140000, 8, SST_MEM_DRAM}, /* D-SRAM0 - 8 * 32kB */
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};
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static int sst_byt_resource_map(struct sst_dsp *sst, struct sst_pdata *pdata)
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{
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sst->addr.lpe_base = pdata->lpe_base;
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sst->addr.lpe = ioremap(pdata->lpe_base, pdata->lpe_size);
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if (!sst->addr.lpe)
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return -ENODEV;
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/* ADSP PCI MMIO config space */
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sst->addr.pci_cfg = ioremap(pdata->pcicfg_base, pdata->pcicfg_size);
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if (!sst->addr.pci_cfg) {
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iounmap(sst->addr.lpe);
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return -ENODEV;
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}
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/* SST Extended FW allocation */
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sst->addr.fw_ext = ioremap(pdata->fw_base, pdata->fw_size);
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if (!sst->addr.fw_ext) {
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iounmap(sst->addr.pci_cfg);
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iounmap(sst->addr.lpe);
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return -ENODEV;
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}
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/* SST Shim */
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sst->addr.shim = sst->addr.lpe + sst->addr.shim_offset;
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sst_dsp_mailbox_init(sst, SST_BYT_MAILBOX_OFFSET + 0x204,
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SST_BYT_IPC_MAX_PAYLOAD_SIZE,
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SST_BYT_MAILBOX_OFFSET,
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SST_BYT_IPC_MAX_PAYLOAD_SIZE);
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sst->irq = pdata->irq;
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return 0;
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}
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static int sst_byt_init(struct sst_dsp *sst, struct sst_pdata *pdata)
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{
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const struct sst_adsp_memregion *region;
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struct device *dev;
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int ret = -ENODEV, i, j, region_count;
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u32 offset, size;
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dev = sst->dev;
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switch (sst->id) {
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case SST_DEV_ID_BYT:
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region = byt_region;
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region_count = ARRAY_SIZE(byt_region);
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sst->addr.iram_offset = SST_BYT_IRAM_OFFSET;
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sst->addr.dram_offset = SST_BYT_DRAM_OFFSET;
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sst->addr.shim_offset = SST_BYT_SHIM_OFFSET;
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break;
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default:
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dev_err(dev, "failed to get mem resources\n");
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return ret;
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}
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ret = sst_byt_resource_map(sst, pdata);
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if (ret < 0) {
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dev_err(dev, "failed to map resources\n");
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return ret;
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}
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/*
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* save the physical address of extended firmware block in the first
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* 4 bytes of the mailbox
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*/
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memcpy_toio(sst->addr.lpe + SST_BYT_MAILBOX_OFFSET,
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&pdata->fw_base, sizeof(u32));
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ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
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if (ret)
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return ret;
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/* enable Interrupt from both sides */
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sst_dsp_shim_update_bits64(sst, SST_IMRX, 0x3, 0x0);
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sst_dsp_shim_update_bits64(sst, SST_IMRD, 0x3, 0x0);
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/* register DSP memory blocks - ideally we should get this from ACPI */
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for (i = 0; i < region_count; i++) {
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offset = region[i].start;
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size = (region[i].end - region[i].start) / region[i].blocks;
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/* register individual memory blocks */
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for (j = 0; j < region[i].blocks; j++) {
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sst_mem_block_register(sst, offset, size,
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region[i].type, NULL, j, sst);
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offset += size;
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}
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}
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return 0;
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}
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static void sst_byt_free(struct sst_dsp *sst)
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{
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sst_mem_block_unregister_all(sst);
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iounmap(sst->addr.lpe);
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iounmap(sst->addr.pci_cfg);
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iounmap(sst->addr.fw_ext);
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}
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struct sst_ops sst_byt_ops = {
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.reset = sst_byt_reset,
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.boot = sst_byt_boot,
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.write = sst_shim32_write,
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.read = sst_shim32_read,
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.write64 = sst_shim32_write64,
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.read64 = sst_shim32_read64,
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.ram_read = sst_memcpy_fromio_32,
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.ram_write = sst_memcpy_toio_32,
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.irq_handler = sst_byt_irq,
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.init = sst_byt_init,
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.free = sst_byt_free,
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.parse_fw = sst_byt_parse_fw_image,
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};
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@ -66,6 +66,7 @@ struct sst_addr {
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u32 lpe_base;
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u32 shim_offset;
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u32 iram_offset;
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u32 dram_offset;
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void __iomem *lpe;
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void __iomem *shim;
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void __iomem *pci_cfg;
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