A few fixes for irqchip drivers:

- Allocate interrupt descriptors correctly on Mainstone PXA when
    SPARSE_IRQ is enabled; otherwise the interrupt association fails.
 
  - Make the APPLE AIC chip driver depend on APPLE.
 
  - Remove redundant error output on devm_ioremap_resource() failure.
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Merge tag 'irq-urgent-2021-05-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq fixes from Thomas Gleixner:
 "A few fixes for irqchip drivers:

   - Allocate interrupt descriptors correctly on Mainstone PXA when
     SPARSE_IRQ is enabled; otherwise the interrupt association fails

   - Make the APPLE AIC chip driver depend on APPLE

   - Remove redundant error output on devm_ioremap_resource() failure"

* tag 'irq-urgent-2021-05-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip: Remove redundant error printing
  irqchip/apple-aic: APPLE_AIC should depend on ARCH_APPLE
  ARM: PXA: Fix cplds irqdesc allocation when using legacy mode
This commit is contained in:
Linus Torvalds 2021-05-23 06:28:20 -10:00
commit f73d2a4293
5 changed files with 10 additions and 11 deletions

View File

@ -121,8 +121,13 @@ static int cplds_probe(struct platform_device *pdev)
return fpga->irq;
base_irq = platform_get_irq(pdev, 1);
if (base_irq < 0)
if (base_irq < 0) {
base_irq = 0;
} else {
ret = devm_irq_alloc_descs(&pdev->dev, base_irq, base_irq, CPLDS_NB_IRQ, 0);
if (ret < 0)
return ret;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
fpga->base = devm_ioremap_resource(&pdev->dev, res);

View File

@ -596,7 +596,7 @@ config IRQ_IDT3243X
config APPLE_AIC
bool "Apple Interrupt Controller (AIC)"
depends on ARM64
default ARCH_APPLE
depends on ARCH_APPLE || COMPILE_TEST
help
Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
such as the M1.

View File

@ -359,10 +359,8 @@ static int mvebu_icu_probe(struct platform_device *pdev)
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
icu->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(icu->base)) {
dev_err(&pdev->dev, "Failed to map icu base address.\n");
if (IS_ERR(icu->base))
return PTR_ERR(icu->base);
}
/*
* Legacy bindings: ICU is one node with one MSI parent: force manually

View File

@ -384,10 +384,8 @@ static int mvebu_sei_probe(struct platform_device *pdev)
sei->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
sei->base = devm_ioremap_resource(sei->dev, sei->res);
if (IS_ERR(sei->base)) {
dev_err(sei->dev, "Failed to remap SEI resource\n");
if (IS_ERR(sei->base))
return PTR_ERR(sei->base);
}
/* Retrieve the SEI capabilities with the interrupt ranges */
sei->caps = of_device_get_match_data(&pdev->dev);

View File

@ -892,10 +892,8 @@ static int stm32_exti_probe(struct platform_device *pdev)
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
host_data->base = devm_ioremap_resource(dev, res);
if (IS_ERR(host_data->base)) {
dev_err(dev, "Unable to map registers\n");
if (IS_ERR(host_data->base))
return PTR_ERR(host_data->base);
}
for (i = 0; i < drv_data->bank_nr; i++)
stm32_exti_chip_init(host_data, i, np);