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net: mvpp2: ptp: add support for transmit timestamping
Add support for timestamping transmit packets. We allocate SYNC messages to queue 1, every other message to queue 0. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
ce3497e207
commit
f5015a594c
@ -12,6 +12,7 @@
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/netdevice.h>
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#include <linux/net_tstamp.h>
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#include <linux/phy.h>
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#include <linux/phylink.h>
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#include <net/flow_offload.h>
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@ -463,8 +464,10 @@
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#define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7)
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#define MVPP22_GMAC_INT_SUM_STAT 0xa0
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#define MVPP22_GMAC_INT_SUM_STAT_INTERNAL BIT(1)
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#define MVPP22_GMAC_INT_SUM_STAT_PTP BIT(2)
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#define MVPP22_GMAC_INT_SUM_MASK 0xa4
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#define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1)
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#define MVPP22_GMAC_INT_SUM_MASK_PTP BIT(2)
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/* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
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* relative to port->base.
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@ -492,9 +495,11 @@
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#define MVPP22_XLG_CTRL3_MACMODESELECT_10G (1 << 13)
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#define MVPP22_XLG_EXT_INT_STAT 0x158
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#define MVPP22_XLG_EXT_INT_STAT_XLG BIT(1)
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#define MVPP22_XLG_EXT_INT_STAT_PTP BIT(7)
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#define MVPP22_XLG_EXT_INT_MASK 0x15c
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#define MVPP22_XLG_EXT_INT_MASK_XLG BIT(1)
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#define MVPP22_XLG_EXT_INT_MASK_GIG BIT(2)
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#define MVPP22_XLG_EXT_INT_MASK_PTP BIT(7)
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#define MVPP22_XLG_CTRL4_REG 0x184
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#define MVPP22_XLG_CTRL4_FWD_FC BIT(5)
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#define MVPP22_XLG_CTRL4_FWD_PFC BIT(6)
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@ -598,7 +603,11 @@
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/* PTP registers. PPv2.2 only */
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#define MVPP22_PTP_BASE(port) (0x7800 + (port * 0x1000))
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#define MVPP22_PTP_INT_CAUSE 0x00
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#define MVPP22_PTP_INT_CAUSE_QUEUE1 BIT(6)
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#define MVPP22_PTP_INT_CAUSE_QUEUE0 BIT(5)
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#define MVPP22_PTP_INT_MASK 0x04
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#define MVPP22_PTP_INT_MASK_QUEUE1 BIT(6)
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#define MVPP22_PTP_INT_MASK_QUEUE0 BIT(5)
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#define MVPP22_PTP_GCR 0x08
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#define MVPP22_PTP_GCR_RX_RESET BIT(13)
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#define MVPP22_PTP_GCR_TX_RESET BIT(1)
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@ -796,6 +805,43 @@ enum mvpp2_prs_l3_cast {
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MVPP2_PRS_L3_BROAD_CAST
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};
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/* PTP descriptor constants. The low bits of the descriptor are stored
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* separately from the high bits.
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*/
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#define MVPP22_PTP_DESC_MASK_LOW 0xfff
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/* PTPAction */
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enum mvpp22_ptp_action {
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MVPP22_PTP_ACTION_NONE = 0,
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MVPP22_PTP_ACTION_FORWARD = 1,
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MVPP22_PTP_ACTION_CAPTURE = 3,
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/* The following have not been verified */
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MVPP22_PTP_ACTION_ADDTIME = 4,
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MVPP22_PTP_ACTION_ADDCORRECTEDTIME = 5,
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MVPP22_PTP_ACTION_CAPTUREADDTIME = 6,
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MVPP22_PTP_ACTION_CAPTUREADDCORRECTEDTIME = 7,
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MVPP22_PTP_ACTION_ADDINGRESSTIME = 8,
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MVPP22_PTP_ACTION_CAPTUREADDINGRESSTIME = 9,
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MVPP22_PTP_ACTION_CAPTUREINGRESSTIME = 10,
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};
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/* PTPPacketFormat */
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enum mvpp22_ptp_packet_format {
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MVPP22_PTP_PKT_FMT_PTPV2 = 0,
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MVPP22_PTP_PKT_FMT_PTPV1 = 1,
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MVPP22_PTP_PKT_FMT_Y1731 = 2,
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MVPP22_PTP_PKT_FMT_NTPTS = 3,
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MVPP22_PTP_PKT_FMT_NTPRX = 4,
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MVPP22_PTP_PKT_FMT_NTPTX = 5,
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MVPP22_PTP_PKT_FMT_TWAMP = 6,
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};
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#define MVPP22_PTP_ACTION(x) (((x) & 15) << 0)
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#define MVPP22_PTP_PACKETFORMAT(x) (((x) & 7) << 4)
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#define MVPP22_PTP_MACTIMESTAMPINGEN BIT(11)
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#define MVPP22_PTP_TIMESTAMPENTRYID(x) (((x) & 31) << 12)
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#define MVPP22_PTP_TIMESTAMPQUEUESELECT BIT(18)
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/* BM constants */
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#define MVPP2_BM_JUMBO_BUF_NUM 512
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#define MVPP2_BM_LONG_BUF_NUM 1024
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@ -1014,6 +1060,11 @@ struct mvpp2_ethtool_fs {
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struct ethtool_rxnfc rxnfc;
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};
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struct mvpp2_hwtstamp_queue {
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struct sk_buff *skb[32];
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u8 next;
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};
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struct mvpp2_port {
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u8 id;
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@ -1100,6 +1151,8 @@ struct mvpp2_port {
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bool hwtstamp;
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bool rx_hwtstamp;
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enum hwtstamp_tx_types tx_hwtstamp_type;
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struct mvpp2_hwtstamp_queue tx_hwtstamp_queue[2];
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};
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/* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
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@ -1168,7 +1221,8 @@ struct mvpp22_tx_desc {
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u8 packet_offset;
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u8 phys_txq;
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__le16 data_size;
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__le64 reserved1;
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__le32 ptp_descriptor;
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__le32 reserved2;
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__le64 buf_dma_addr_ptp;
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__le64 buf_cookie_misc;
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};
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@ -28,6 +28,7 @@
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#include <linux/phy.h>
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#include <linux/phylink.h>
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#include <linux/phy/phy.h>
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#include <linux/ptp_classify.h>
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#include <linux/clk.h>
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#include <linux/hrtimer.h>
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#include <linux/ktime.h>
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@ -1379,6 +1380,10 @@ static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
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{
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u32 val;
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mvpp2_modify(port->base + MVPP22_GMAC_INT_SUM_MASK,
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MVPP22_GMAC_INT_SUM_MASK_PTP,
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MVPP22_GMAC_INT_SUM_MASK_PTP);
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if (port->phylink ||
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phy_interface_mode_is_rgmii(port->phy_interface) ||
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phy_interface_mode_is_8023z(port->phy_interface) ||
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@ -1392,6 +1397,10 @@ static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
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val = readl(port->base + MVPP22_XLG_INT_MASK);
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val |= MVPP22_XLG_INT_MASK_LINK;
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writel(val, port->base + MVPP22_XLG_INT_MASK);
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mvpp2_modify(port->base + MVPP22_XLG_EXT_INT_MASK,
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MVPP22_XLG_EXT_INT_MASK_PTP,
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MVPP22_XLG_EXT_INT_MASK_PTP);
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}
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mvpp22_gop_unmask_irq(port);
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@ -2974,6 +2983,56 @@ static irqreturn_t mvpp2_isr(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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static void mvpp2_isr_handle_ptp_queue(struct mvpp2_port *port, int nq)
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{
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struct skb_shared_hwtstamps shhwtstamps;
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struct mvpp2_hwtstamp_queue *queue;
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struct sk_buff *skb;
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void __iomem *ptp_q;
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unsigned int id;
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u32 r0, r1, r2;
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ptp_q = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id);
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if (nq)
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ptp_q += MVPP22_PTP_TX_Q1_R0 - MVPP22_PTP_TX_Q0_R0;
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queue = &port->tx_hwtstamp_queue[nq];
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while (1) {
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r0 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R0) & 0xffff;
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if (!r0)
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break;
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r1 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R1) & 0xffff;
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r2 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R2) & 0xffff;
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id = (r0 >> 1) & 31;
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skb = queue->skb[id];
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queue->skb[id] = NULL;
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if (skb) {
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u32 ts = r2 << 19 | r1 << 3 | r0 >> 13;
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mvpp22_tai_tstamp(port->priv->tai, ts, &shhwtstamps);
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skb_tstamp_tx(skb, &shhwtstamps);
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dev_kfree_skb_any(skb);
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}
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}
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}
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static void mvpp2_isr_handle_ptp(struct mvpp2_port *port)
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{
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void __iomem *ptp;
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u32 val;
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ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id);
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val = readl(ptp + MVPP22_PTP_INT_CAUSE);
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if (val & MVPP22_PTP_INT_CAUSE_QUEUE0)
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mvpp2_isr_handle_ptp_queue(port, 0);
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if (val & MVPP22_PTP_INT_CAUSE_QUEUE1)
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mvpp2_isr_handle_ptp_queue(port, 1);
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}
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static void mvpp2_isr_handle_link(struct mvpp2_port *port, bool link)
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{
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struct net_device *dev = port->dev;
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@ -3049,6 +3108,8 @@ static irqreturn_t mvpp2_port_isr(int irq, void *dev_id)
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val = readl(port->base + MVPP22_XLG_EXT_INT_STAT);
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if (val & MVPP22_XLG_EXT_INT_STAT_XLG)
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mvpp2_isr_handle_xlg(port);
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if (val & MVPP22_XLG_EXT_INT_STAT_PTP)
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mvpp2_isr_handle_ptp(port);
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} else {
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/* If it's not the XLG, we must be using the GMAC.
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* Check the summary status.
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@ -3056,6 +3117,8 @@ static irqreturn_t mvpp2_port_isr(int irq, void *dev_id)
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val = readl(port->base + MVPP22_GMAC_INT_SUM_STAT);
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if (val & MVPP22_GMAC_INT_SUM_STAT_INTERNAL)
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mvpp2_isr_handle_gmac_internal(port);
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if (val & MVPP22_GMAC_INT_SUM_STAT_PTP)
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mvpp2_isr_handle_ptp(port);
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}
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mvpp22_gop_unmask_irq(port);
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@ -3610,6 +3673,92 @@ tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
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mvpp2_txq_desc_put(txq);
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}
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static void mvpp2_txdesc_clear_ptp(struct mvpp2_port *port,
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struct mvpp2_tx_desc *desc)
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{
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/* We only need to clear the low bits */
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if (port->priv->hw_version != MVPP21)
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desc->pp22.ptp_descriptor &=
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cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW);
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}
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static bool mvpp2_tx_hw_tstamp(struct mvpp2_port *port,
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struct mvpp2_tx_desc *tx_desc,
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struct sk_buff *skb)
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{
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struct mvpp2_hwtstamp_queue *queue;
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unsigned int mtype, type, i;
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struct ptp_header *hdr;
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u64 ptpdesc;
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if (port->priv->hw_version == MVPP21 ||
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port->tx_hwtstamp_type == HWTSTAMP_TX_OFF)
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return false;
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type = ptp_classify_raw(skb);
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if (!type)
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return false;
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hdr = ptp_parse_header(skb, type);
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if (!hdr)
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return false;
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ptpdesc = MVPP22_PTP_MACTIMESTAMPINGEN |
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MVPP22_PTP_ACTION_CAPTURE;
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queue = &port->tx_hwtstamp_queue[0];
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switch (type & PTP_CLASS_VMASK) {
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case PTP_CLASS_V1:
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ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV1);
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break;
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case PTP_CLASS_V2:
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ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV2);
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mtype = hdr->tsmt & 15;
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/* Direct PTP Sync messages to queue 1 */
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if (mtype == 0) {
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ptpdesc |= MVPP22_PTP_TIMESTAMPQUEUESELECT;
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queue = &port->tx_hwtstamp_queue[1];
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}
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break;
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}
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/* Take a reference on the skb and insert into our queue */
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i = queue->next;
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queue->next = (i + 1) & 31;
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if (queue->skb[i])
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dev_kfree_skb_any(queue->skb[i]);
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queue->skb[i] = skb_get(skb);
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ptpdesc |= MVPP22_PTP_TIMESTAMPENTRYID(i);
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/*
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* 3:0 - PTPAction
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* 6:4 - PTPPacketFormat
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* 7 - PTP_CF_WraparoundCheckEn
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* 9:8 - IngressTimestampSeconds[1:0]
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* 10 - Reserved
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* 11 - MACTimestampingEn
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* 17:12 - PTP_TimestampQueueEntryID[5:0]
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* 18 - PTPTimestampQueueSelect
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* 19 - UDPChecksumUpdateEn
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* 27:20 - TimestampOffset
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* PTP, NTPTransmit, OWAMP/TWAMP - L3 to PTP header
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* NTPTs, Y.1731 - L3 to timestamp entry
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* 35:28 - UDP Checksum Offset
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*
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* stored in tx descriptor bits 75:64 (11:0) and 191:168 (35:12)
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*/
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tx_desc->pp22.ptp_descriptor &=
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cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW);
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tx_desc->pp22.ptp_descriptor |=
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cpu_to_le32(ptpdesc & MVPP22_PTP_DESC_MASK_LOW);
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tx_desc->pp22.buf_dma_addr_ptp &= cpu_to_le64(~0xffffff0000000000ULL);
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tx_desc->pp22.buf_dma_addr_ptp |= cpu_to_le64((ptpdesc >> 12) << 40);
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return true;
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}
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/* Handle tx fragmentation processing */
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static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
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struct mvpp2_tx_queue *aggr_txq,
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@ -3626,6 +3775,7 @@ static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
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void *addr = skb_frag_address(frag);
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tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
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mvpp2_txdesc_clear_ptp(port, tx_desc);
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mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
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mvpp2_txdesc_size_set(port, tx_desc, skb_frag_size(frag));
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@ -3675,6 +3825,7 @@ static inline void mvpp2_tso_put_hdr(struct sk_buff *skb,
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struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
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dma_addr_t addr;
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mvpp2_txdesc_clear_ptp(port, tx_desc);
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mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
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mvpp2_txdesc_size_set(port, tx_desc, hdr_sz);
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@ -3699,6 +3850,7 @@ static inline int mvpp2_tso_put_data(struct sk_buff *skb,
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struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
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dma_addr_t buf_dma_addr;
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mvpp2_txdesc_clear_ptp(port, tx_desc);
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mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
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mvpp2_txdesc_size_set(port, tx_desc, sz);
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@ -3815,6 +3967,9 @@ static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
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/* Get a descriptor for the first part of the packet */
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tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
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if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ||
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!mvpp2_tx_hw_tstamp(port, tx_desc, skb))
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mvpp2_txdesc_clear_ptp(port, tx_desc);
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mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
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mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb));
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@ -4574,6 +4729,7 @@ static int mvpp2_set_ts_config(struct mvpp2_port *port, struct ifreq *ifr)
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{
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struct hwtstamp_config config;
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void __iomem *ptp;
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u32 gcr, int_mask;
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if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
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return -EFAULT;
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@ -4581,30 +4737,51 @@ static int mvpp2_set_ts_config(struct mvpp2_port *port, struct ifreq *ifr)
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if (config.flags)
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return -EINVAL;
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if (config.tx_type != HWTSTAMP_TX_OFF)
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if (config.tx_type != HWTSTAMP_TX_OFF &&
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config.tx_type != HWTSTAMP_TX_ON)
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return -ERANGE;
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ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id);
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int_mask = gcr = 0;
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if (config.tx_type != HWTSTAMP_TX_OFF) {
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gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_TX_RESET;
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int_mask |= MVPP22_PTP_INT_MASK_QUEUE1 |
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MVPP22_PTP_INT_MASK_QUEUE0;
|
||||
}
|
||||
|
||||
/* It seems we must also release the TX reset when enabling the TSU */
|
||||
if (config.rx_filter != HWTSTAMP_FILTER_NONE)
|
||||
gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_RX_RESET |
|
||||
MVPP22_PTP_GCR_TX_RESET;
|
||||
|
||||
if (gcr & MVPP22_PTP_GCR_TSU_ENABLE)
|
||||
mvpp22_tai_start(port->priv->tai);
|
||||
|
||||
if (config.rx_filter != HWTSTAMP_FILTER_NONE) {
|
||||
config.rx_filter = HWTSTAMP_FILTER_ALL;
|
||||
mvpp22_tai_start(port->priv->tai);
|
||||
mvpp2_modify(ptp + MVPP22_PTP_GCR,
|
||||
MVPP22_PTP_GCR_RX_RESET |
|
||||
MVPP22_PTP_GCR_TX_RESET |
|
||||
MVPP22_PTP_GCR_TSU_ENABLE,
|
||||
MVPP22_PTP_GCR_RX_RESET |
|
||||
MVPP22_PTP_GCR_TX_RESET |
|
||||
MVPP22_PTP_GCR_TSU_ENABLE);
|
||||
MVPP22_PTP_GCR_TSU_ENABLE, gcr);
|
||||
port->rx_hwtstamp = true;
|
||||
} else {
|
||||
port->rx_hwtstamp = false;
|
||||
mvpp2_modify(ptp + MVPP22_PTP_GCR,
|
||||
MVPP22_PTP_GCR_RX_RESET |
|
||||
MVPP22_PTP_GCR_TX_RESET |
|
||||
MVPP22_PTP_GCR_TSU_ENABLE, 0);
|
||||
mvpp22_tai_stop(port->priv->tai);
|
||||
MVPP22_PTP_GCR_TSU_ENABLE, gcr);
|
||||
}
|
||||
|
||||
mvpp2_modify(ptp + MVPP22_PTP_INT_MASK,
|
||||
MVPP22_PTP_INT_MASK_QUEUE1 |
|
||||
MVPP22_PTP_INT_MASK_QUEUE0, int_mask);
|
||||
|
||||
if (!(gcr & MVPP22_PTP_GCR_TSU_ENABLE))
|
||||
mvpp22_tai_stop(port->priv->tai);
|
||||
|
||||
port->tx_hwtstamp_type = config.tx_type;
|
||||
|
||||
if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
|
||||
return -EFAULT;
|
||||
|
||||
@ -4617,7 +4794,7 @@ static int mvpp2_get_ts_config(struct mvpp2_port *port, struct ifreq *ifr)
|
||||
|
||||
memset(&config, 0, sizeof(config));
|
||||
|
||||
config.tx_type = HWTSTAMP_TX_OFF;
|
||||
config.tx_type = port->tx_hwtstamp_type;
|
||||
config.rx_filter = port->rx_hwtstamp ?
|
||||
HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE;
|
||||
|
||||
@ -4639,9 +4816,11 @@ static int mvpp2_ethtool_get_ts_info(struct net_device *dev,
|
||||
info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
|
||||
SOF_TIMESTAMPING_RX_SOFTWARE |
|
||||
SOF_TIMESTAMPING_SOFTWARE |
|
||||
SOF_TIMESTAMPING_TX_HARDWARE |
|
||||
SOF_TIMESTAMPING_RX_HARDWARE |
|
||||
SOF_TIMESTAMPING_RAW_HARDWARE;
|
||||
info->tx_types = BIT(HWTSTAMP_TX_OFF);
|
||||
info->tx_types = BIT(HWTSTAMP_TX_OFF) |
|
||||
BIT(HWTSTAMP_TX_ON);
|
||||
info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
|
||||
BIT(HWTSTAMP_FILTER_ALL);
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user