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drm/gf100-/gr: unhardcode pagepool config

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2014-08-10 04:10:29 +10:00
parent aa2d58c33a
commit f331a15f84
13 changed files with 75 additions and 41 deletions
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2
drivers/gpu/drm/nouveau/core/engine/graph/ctxgk110b.c
View File

@ -95,4 +95,6 @@ gk110b_grctx_oclass = &(struct nvc0_grctx_oclass) {
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x600,
.pagepool = nve4_grctx_generate_pagepool,
.pagepool_size = 0x8000,
}.base;

2
drivers/gpu/drm/nouveau/core/engine/graph/ctxgk20a.c
View File

@ -54,4 +54,6 @@ gk20a_grctx_oclass = &(struct nvc0_grctx_oclass) {
.bundle_size = 0x1800,
.bundle_min_gpm_fifo_depth = 0x62,
.bundle_token_limit = 0x100,
.pagepool = nve4_grctx_generate_pagepool,
.pagepool_size = 0x8000,
}.base;

26
drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c
View File

@ -875,19 +875,26 @@ gm107_grctx_generate_bundle(struct nvc0_grctx *info)
mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit);
}
static void
gm107_grctx_generate_pagepool(struct nvc0_grctx *info)
{
const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);
mmio_refn(info, 0x40800c, 0x00000000, s, b);
mmio_wr32(info, 0x408010, 0x80000000);
mmio_refn(info, 0x419004, 0x00000000, s, b);
mmio_wr32(info, 0x419008, 0x00000000);
mmio_wr32(info, 0x4064cc, 0x80000000);
mmio_wr32(info, 0x418e30, 0x80000000); /* guess at it being related */
}
static void
gm107_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
{
mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x200000, 0x1000, NV_MEM_ACCESS_RW);
mmio_list(0x40800c, 0x00000000, 8, 1);
mmio_list(0x408010, 0x80000000, 0, 0);
mmio_list(0x419004, 0x00000000, 8, 1);
mmio_list(0x419008, 0x00000000, 0, 0);
mmio_list(0x4064cc, 0x80000000, 0, 0);
mmio_list(0x418e30, 0x80000000, 0, 0);
mmio_list(0x418810, 0x80000000, 12, 2);
mmio_list(0x419848, 0x10000000, 12, 2);
mmio_list(0x419c2c, 0x10000000, 12, 2);
@ -944,6 +951,7 @@ gm107_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
nv_wr32(priv, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->pagepool(info);
oclass->mods(priv, info);
oclass->unkn(priv);
@ -1002,4 +1010,6 @@ gm107_grctx_oclass = &(struct nvc0_grctx_oclass) {
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x2c0,
.pagepool = gm107_grctx_generate_pagepool,
.pagepool_size = 0x8000,
}.base;

8
drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c
View File

@ -538,13 +538,7 @@ nv108_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
u32 offset;
int gpc;
mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
mmio_list(0x40800c, 0x00000000, 8, 1);
mmio_list(0x408010, 0x80000000, 0, 0);
mmio_list(0x419004, 0x00000000, 8, 1);
mmio_list(0x419008, 0x00000000, 0, 0);
mmio_list(0x4064cc, 0x80000000, 0, 0);
mmio_list(0x418810, 0x80000000, 12, 2);
mmio_list(0x419848, 0x10000000, 12, 2);
@ -594,4 +588,6 @@ nv108_grctx_oclass = &(struct nvc0_grctx_oclass) {
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0xc2,
.bundle_token_limit = 0x200,
.pagepool = nve4_grctx_generate_pagepool,
.pagepool_size = 0x8000,
}.base;

21
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
View File

@ -1033,21 +1033,29 @@ nvc0_grctx_generate_bundle(struct nvc0_grctx *info)
mmio_refn(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s), 0, b);
}
void
nvc0_grctx_generate_pagepool(struct nvc0_grctx *info)
{
const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);
mmio_refn(info, 0x40800c, 0x00000000, s, b);
mmio_wr32(info, 0x408010, 0x80000000);
mmio_refn(info, 0x419004, 0x00000000, s, b);
mmio_wr32(info, 0x419008, 0x00000000);
}
void
nvc0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
{
int gpc, tpc;
u32 offset;
mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
mmio_list(0x40800c, 0x00000000, 8, 1);
mmio_list(0x408010, 0x80000000, 0, 0);
mmio_list(0x418810, 0x80000000, 12, 2);
mmio_list(0x419848, 0x10000000, 12, 2);
mmio_list(0x419004, 0x00000000, 8, 1);
mmio_list(0x419008, 0x00000000, 0, 0);
mmio_list(0x405830, 0x02180000, 0, 0);
@ -1227,6 +1235,7 @@ nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
nv_wr32(priv, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->pagepool(info);
oclass->mods(priv, info);
oclass->unkn(priv);
@ -1365,4 +1374,6 @@ nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) {
.mthd = nvc0_grctx_pack_mthd,
.bundle = nvc0_grctx_generate_bundle,
.bundle_size = 0x1800,
.pagepool = nvc0_grctx_generate_pagepool,
.pagepool_size = 0x8000,
}.base;

5
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h
View File

@ -44,6 +44,9 @@ struct nvc0_grctx_oclass {
u32 bundle_size;
u32 bundle_min_gpm_fifo_depth;
u32 bundle_token_limit;
/* pagepool */
void (*pagepool)(struct nvc0_grctx *);
u32 pagepool_size;
};
static inline const struct nvc0_grctx_oclass *
@ -56,6 +59,7 @@ extern struct nouveau_oclass *nvc0_grctx_oclass;
int nvc0_grctx_generate(struct nvc0_graph_priv *);
void nvc0_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nvc0_grctx_generate_bundle(struct nvc0_grctx *);
void nvc0_grctx_generate_pagepool(struct nvc0_grctx *);
void nvc0_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nvc0_grctx_generate_unkn(struct nvc0_graph_priv *);
void nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *);
@ -77,6 +81,7 @@ extern struct nouveau_oclass *nve4_grctx_oclass;
extern struct nouveau_oclass *gk20a_grctx_oclass;
void nve4_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nve4_grctx_generate_bundle(struct nvc0_grctx *);
void nve4_grctx_generate_pagepool(struct nvc0_grctx *);
void nve4_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nve4_grctx_generate_unkn(struct nvc0_graph_priv *);
void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *);

7
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c
View File

@ -732,14 +732,9 @@ nvc1_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
int gpc, tpc;
u32 offset;
mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
mmio_list(0x40800c, 0x00000000, 8, 1);
mmio_list(0x408010, 0x80000000, 0, 0);
mmio_list(0x418810, 0x80000000, 12, 2);
mmio_list(0x419848, 0x10000000, 12, 2);
mmio_list(0x419004, 0x00000000, 8, 1);
mmio_list(0x419008, 0x00000000, 0, 0);
mmio_list(0x405830, 0x02180218, 0, 0);
mmio_list(0x4064c4, 0x0086ffff, 0, 0);
@ -791,4 +786,6 @@ nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) {
.mthd = nvc1_grctx_pack_mthd,
.bundle = nvc0_grctx_generate_bundle,
.bundle_size = 0x1800,
.pagepool = nvc0_grctx_generate_pagepool,
.pagepool_size = 0x8000,
}.base;

2
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc4.c
View File

@ -102,4 +102,6 @@ nvc4_grctx_oclass = &(struct nvc0_grctx_oclass) {
.mthd = nvc0_grctx_pack_mthd,
.bundle = nvc0_grctx_generate_bundle,
.bundle_size = 0x1800,
.pagepool = nvc0_grctx_generate_pagepool,
.pagepool_size = 0x8000,
}.base;

2
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c
View File

@ -353,4 +353,6 @@ nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) {
.mthd = nvc8_grctx_pack_mthd,
.bundle = nvc0_grctx_generate_bundle,
.bundle_size = 0x1800,
.pagepool = nvc0_grctx_generate_pagepool,
.pagepool_size = 0x8000,
}.base;

8
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c
View File

@ -184,12 +184,7 @@ nvd7_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
u32 offset;
int gpc;
mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
mmio_list(0x40800c, 0x00000000, 8, 1);
mmio_list(0x408010, 0x80000000, 0, 0);
mmio_list(0x419004, 0x00000000, 8, 1);
mmio_list(0x419008, 0x00000000, 0, 0);
mmio_list(0x418810, 0x80000000, 12, 2);
mmio_list(0x419848, 0x10000000, 12, 2);
@ -229,6 +224,7 @@ nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
nv_wr32(priv, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->pagepool(info);
oclass->mods(priv, info);
oclass->unkn(priv);
@ -270,4 +266,6 @@ nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) {
.mthd = nvd9_grctx_pack_mthd,
.bundle = nvc0_grctx_generate_bundle,
.bundle_size = 0x1800,
.pagepool = nvc0_grctx_generate_pagepool,
.pagepool_size = 0x8000,
}.base;

2
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c
View File

@ -521,4 +521,6 @@ nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) {
.mthd = nvd9_grctx_pack_mthd,
.bundle = nvc0_grctx_generate_bundle,
.bundle_size = 0x1800,
.pagepool = nvc0_grctx_generate_pagepool,
.pagepool_size = 0x8000,
}.base;

23
drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
View File

@ -855,6 +855,20 @@ nve4_grctx_generate_bundle(struct nvc0_grctx *info)
mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit);
}
void
nve4_grctx_generate_pagepool(struct nvc0_grctx *info)
{
const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);
mmio_refn(info, 0x40800c, 0x00000000, s, b);
mmio_wr32(info, 0x408010, 0x80000000);
mmio_refn(info, 0x419004, 0x00000000, s, b);
mmio_wr32(info, 0x419008, 0x00000000);
mmio_wr32(info, 0x4064cc, 0x80000000);
}
void
nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
{
@ -862,13 +876,7 @@ nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
u32 offset;
int gpc;
mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
mmio_list(0x40800c, 0x00000000, 8, 1);
mmio_list(0x408010, 0x80000000, 0, 0);
mmio_list(0x419004, 0x00000000, 8, 1);
mmio_list(0x419008, 0x00000000, 0, 0);
mmio_list(0x4064cc, 0x80000000, 0, 0);
mmio_list(0x418810, 0x80000000, 12, 2);
mmio_list(0x419848, 0x10000000, 12, 2);
@ -979,6 +987,7 @@ nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
nv_wr32(priv, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->pagepool(info);
oclass->mods(priv, info);
oclass->unkn(priv);
@ -1034,4 +1043,6 @@ nve4_grctx_oclass = &(struct nvc0_grctx_oclass) {
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x600,
.pagepool = nve4_grctx_generate_pagepool,
.pagepool_size = 0x8000,
}.base;

8
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c
View File

@ -816,13 +816,7 @@ nvf0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
u32 offset;
int gpc;
mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
mmio_list(0x40800c, 0x00000000, 8, 1);
mmio_list(0x408010, 0x80000000, 0, 0);
mmio_list(0x419004, 0x00000000, 8, 1);
mmio_list(0x419008, 0x00000000, 0, 0);
mmio_list(0x4064cc, 0x80000000, 0, 0);
mmio_list(0x418810, 0x80000000, 12, 2);
mmio_list(0x419848, 0x10000000, 12, 2);
@ -880,4 +874,6 @@ nvf0_grctx_oclass = &(struct nvc0_grctx_oclass) {
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x7c0,
.pagepool = nve4_grctx_generate_pagepool,
.pagepool_size = 0x8000,
}.base;