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powerpc/tm: update comment about interrupt re-entrancy
Since the system reset interrupt began to use its own stack, and machine check interrupts have done so for some time, r1 can be changed without clearing MSR[RI], provided no other interrupts (including SLB misses) are taken. MSR[RI] does have to be cleared when using SCRATCH0, however. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -148,7 +148,7 @@ _GLOBAL(tm_reclaim)
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/* Stash the stack pointer away for use after reclaim */
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/* Stash the stack pointer away for use after reclaim */
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std r1, PACAR1(r13)
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std r1, PACAR1(r13)
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/* Clear MSR RI since we are about to change r1, EE is already off. */
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/* Clear MSR RI since we are about to use SCRATCH0, EE is already off */
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li r5, 0
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li r5, 0
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mtmsrd r5, 1
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mtmsrd r5, 1
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@ -474,7 +474,7 @@ restore_gprs:
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REST_GPR(7, r7)
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REST_GPR(7, r7)
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/* Clear MSR RI since we are about to change r1. EE is already off */
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/* Clear MSR RI since we are about to use SCRATCH0. EE is already off */
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li r5, 0
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li r5, 0
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mtmsrd r5, 1
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mtmsrd r5, 1
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