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ath9k: Handle MCI_STATE_AIC_START
This patch adds a function to handle the MCI message MCI_STATE_AIC_START. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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@ -18,6 +18,7 @@
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#include "hw-ops.h"
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#include "ar9003_mci.h"
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#include "ar9003_aic.h"
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#include "ar9003_phy.h"
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#include "reg_aic.h"
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static const u8 com_att_db_table[ATH_AIC_MAX_COM_ATT_DB_TABLE] = {
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@ -512,6 +513,38 @@ exit:
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}
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u8 ar9003_aic_start_normal(struct ath_hw *ah)
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{
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struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;
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int16_t i;
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if (aic->aic_cal_state != AIC_CAL_STATE_DONE)
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return 1;
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ar9003_aic_gain_table(ah);
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REG_WRITE(ah, AR_PHY_AIC_SRAM_ADDR_B1, ATH_AIC_SRAM_AUTO_INCREMENT);
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for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) {
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REG_WRITE(ah, AR_PHY_AIC_SRAM_DATA_B1, aic->aic_sram[i]);
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}
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/* FIXME: Replace these with proper register names */
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REG_WRITE(ah, 0xa6b0, 0x80);
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REG_WRITE(ah, 0xa6b4, 0x5b2df0);
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REG_WRITE(ah, 0xa6b8, 0x10762cc8);
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REG_WRITE(ah, 0xa6bc, 0x1219a4b);
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REG_WRITE(ah, 0xa6c0, 0x1e01);
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REG_WRITE(ah, 0xb6b4, 0xf0);
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REG_WRITE(ah, 0xb6c0, 0x1e01);
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REG_WRITE(ah, 0xb6b0, 0x81);
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REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX4, 0x40000000);
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aic->aic_enabled = true;
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return 0;
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}
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u8 ar9003_aic_cal_reset(struct ath_hw *ah)
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{
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struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;
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@ -53,6 +53,7 @@ struct ath_aic_out_info {
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struct ath_aic_sram_info sram;
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};
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u8 ar9003_aic_start_normal(struct ath_hw *ah);
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u8 ar9003_aic_cal_reset(struct ath_hw *ah);
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u8 ar9003_aic_calibration_single(struct ath_hw *ah);
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@ -1363,6 +1363,10 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type)
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value = (!mci->unhalt_bt_gpm && mci->need_flush_btinfo) ? 1 : 0;
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mci->need_flush_btinfo = false;
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break;
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case MCI_STATE_AIC_START:
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if (ath9k_hw_is_aic_enabled(ah))
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ar9003_aic_start_normal(ah);
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break;
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case MCI_STATE_AIC_CAL_RESET:
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if (ath9k_hw_is_aic_enabled(ah))
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value = ar9003_aic_cal_reset(ah);
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