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[PATCH] Add SMP support on x86_64 to reservation framework
This patch includes the changes to make the nmi watchdog on x86_64 SMP aware. A bunch of code was moved around to make it simpler to read. In addition, it is now possible to determine if a particular NMI was the result of the watchdog or not. This feature allows the kernel to filter out unknown NMIs easier. Signed-off-by: Don Zickus <dzickus@redhat.com> Signed-off-by: Andi Kleen <ak@suse.de>
This commit is contained in:
Don Zickus
Andi Kleen
parent
cb9c448c66
commit
f2802e7f57
@ -479,8 +479,7 @@ void __cpuinit setup_local_APIC (void)
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}
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nmi_watchdog_default();
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if (nmi_watchdog == NMI_LOCAL_APIC)
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setup_apic_nmi_watchdog();
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setup_apic_nmi_watchdog(NULL);
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apic_pm_activate();
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}
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@ -56,53 +56,29 @@ static unsigned int lapic_nmi_owner;
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#define LAPIC_NMI_RESERVED (1<<1)
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/* nmi_active:
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* +1: the lapic NMI watchdog is active, but can be disabled
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* 0: the lapic NMI watchdog has not been set up, and cannot
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* >0: the lapic NMI watchdog is active, but can be disabled
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* <0: the lapic NMI watchdog has not been set up, and cannot
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* be enabled
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* -1: the lapic NMI watchdog is disabled, but can be enabled
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* 0: the lapic NMI watchdog is disabled, but can be enabled
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*/
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int nmi_active; /* oprofile uses this */
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atomic_t nmi_active = ATOMIC_INIT(0); /* oprofile uses this */
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int panic_on_timeout;
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unsigned int nmi_watchdog = NMI_DEFAULT;
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static unsigned int nmi_hz = HZ;
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static unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */
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static unsigned int nmi_p4_cccr_val;
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/* Note that these events don't tick when the CPU idles. This means
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the frequency varies with CPU load. */
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struct nmi_watchdog_ctlblk {
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int enabled;
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u64 check_bit;
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unsigned int cccr_msr;
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unsigned int perfctr_msr; /* the MSR to reset in NMI handler */
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unsigned int evntsel_msr; /* the MSR to select the events to handle */
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};
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static DEFINE_PER_CPU(struct nmi_watchdog_ctlblk, nmi_watchdog_ctlblk);
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#define K7_EVNTSEL_ENABLE (1 << 22)
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#define K7_EVNTSEL_INT (1 << 20)
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#define K7_EVNTSEL_OS (1 << 17)
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#define K7_EVNTSEL_USR (1 << 16)
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#define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
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#define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
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#define MSR_P4_MISC_ENABLE 0x1A0
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#define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
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#define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
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#define MSR_P4_PERFCTR0 0x300
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#define MSR_P4_CCCR0 0x360
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#define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
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#define P4_ESCR_OS (1<<3)
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#define P4_ESCR_USR (1<<2)
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#define P4_CCCR_OVF_PMI0 (1<<26)
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#define P4_CCCR_OVF_PMI1 (1<<27)
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#define P4_CCCR_THRESHOLD(N) ((N)<<20)
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#define P4_CCCR_COMPLEMENT (1<<19)
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#define P4_CCCR_COMPARE (1<<18)
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#define P4_CCCR_REQUIRED (3<<16)
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#define P4_CCCR_ESCR_SELECT(N) ((N)<<13)
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#define P4_CCCR_ENABLE (1<<12)
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/* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
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CRU_ESCR0 (with any non-null event selector) through a complemented
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max threshold. [IA32-Vol3, Section 14.9.9] */
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#define MSR_P4_IQ_COUNTER0 0x30C
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#define P4_NMI_CRU_ESCR0 (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
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#define P4_NMI_IQ_CCCR0 \
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(P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \
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P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
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/* local prototypes */
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static void stop_apic_nmi_watchdog(void *unused);
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static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu);
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/* converts an msr to an appropriate reservation bit */
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static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
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@ -241,6 +217,12 @@ int __init check_nmi_watchdog (void)
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int *counts;
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int cpu;
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if ((nmi_watchdog == NMI_NONE) || (nmi_watchdog == NMI_DEFAULT))
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return 0;
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if (!atomic_read(&nmi_active))
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return 0;
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counts = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
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if (!counts)
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return -1;
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@ -258,19 +240,22 @@ int __init check_nmi_watchdog (void)
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mdelay((10*1000)/nmi_hz); // wait 10 ticks
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for_each_online_cpu(cpu) {
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if (!per_cpu(nmi_watchdog_ctlblk, cpu).enabled)
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continue;
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if (cpu_pda(cpu)->__nmi_count - counts[cpu] <= 5) {
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endflag = 1;
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printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
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cpu,
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counts[cpu],
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cpu_pda(cpu)->__nmi_count);
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nmi_active = 0;
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lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG;
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nmi_perfctr_msr = 0;
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kfree(counts);
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return -1;
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per_cpu(nmi_watchdog_ctlblk, cpu).enabled = 0;
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atomic_dec(&nmi_active);
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}
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}
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if (!atomic_read(&nmi_active)) {
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kfree(counts);
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atomic_set(&nmi_active, -1);
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return -1;
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}
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endflag = 1;
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printk("OK.\n");
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@ -297,8 +282,11 @@ int __init setup_nmi_watchdog(char *str)
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get_option(&str, &nmi);
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if (nmi >= NMI_INVALID)
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if ((nmi >= NMI_INVALID) || (nmi < NMI_NONE))
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return 0;
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if ((nmi == NMI_LOCAL_APIC) && (nmi_known_cpu() == 0))
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return 0; /* no lapic support */
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nmi_watchdog = nmi;
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return 1;
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}
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@ -307,31 +295,30 @@ __setup("nmi_watchdog=", setup_nmi_watchdog);
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static void disable_lapic_nmi_watchdog(void)
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{
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if (nmi_active <= 0)
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BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
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if (atomic_read(&nmi_active) <= 0)
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return;
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switch (boot_cpu_data.x86_vendor) {
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case X86_VENDOR_AMD:
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wrmsr(MSR_K7_EVNTSEL0, 0, 0);
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break;
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case X86_VENDOR_INTEL:
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if (boot_cpu_data.x86 == 15) {
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wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
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wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
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}
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break;
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}
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nmi_active = -1;
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/* tell do_nmi() and others that we're not active any more */
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nmi_watchdog = 0;
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on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
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BUG_ON(atomic_read(&nmi_active) != 0);
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}
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static void enable_lapic_nmi_watchdog(void)
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{
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if (nmi_active < 0) {
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nmi_watchdog = NMI_LOCAL_APIC;
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BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
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/* are we already enabled */
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if (atomic_read(&nmi_active) != 0)
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return;
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/* are we lapic aware */
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if (nmi_known_cpu() <= 0)
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return;
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on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
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touch_nmi_watchdog();
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setup_apic_nmi_watchdog();
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}
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}
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int reserve_lapic_nmi(void)
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@ -363,21 +350,24 @@ void release_lapic_nmi(void)
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void disable_timer_nmi_watchdog(void)
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{
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if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0))
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BUG_ON(nmi_watchdog != NMI_IO_APIC);
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if (atomic_read(&nmi_active) <= 0)
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return;
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disable_irq(0);
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unset_nmi_callback();
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nmi_active = -1;
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nmi_watchdog = NMI_NONE;
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on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
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BUG_ON(atomic_read(&nmi_active) != 0);
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}
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void enable_timer_nmi_watchdog(void)
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{
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if (nmi_active < 0) {
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nmi_watchdog = NMI_IO_APIC;
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BUG_ON(nmi_watchdog != NMI_IO_APIC);
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if (atomic_read(&nmi_active) == 0) {
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touch_nmi_watchdog();
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nmi_active = 1;
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on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
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enable_irq(0);
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}
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}
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@ -388,7 +378,7 @@ static int nmi_pm_active; /* nmi_active before suspend */
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static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
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{
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nmi_pm_active = nmi_active;
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nmi_pm_active = atomic_read(&nmi_active);
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disable_lapic_nmi_watchdog();
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return 0;
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}
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@ -415,7 +405,13 @@ static int __init init_lapic_nmi_sysfs(void)
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{
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int error;
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if (nmi_active == 0 || nmi_watchdog != NMI_LOCAL_APIC)
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/* should really be a BUG_ON but b/c this is an
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* init call, it just doesn't work. -dcz
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*/
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if (nmi_watchdog != NMI_LOCAL_APIC)
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return 0;
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if ( atomic_read(&nmi_active) < 0 )
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return 0;
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error = sysdev_class_register(&nmi_sysclass);
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@ -428,100 +424,232 @@ late_initcall(init_lapic_nmi_sysfs);
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#endif /* CONFIG_PM */
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/*
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* Activate the NMI watchdog via the local APIC.
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* Original code written by Keith Owens.
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*/
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/* Note that these events don't tick when the CPU idles. This means
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the frequency varies with CPU load. */
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#define K7_EVNTSEL_ENABLE (1 << 22)
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#define K7_EVNTSEL_INT (1 << 20)
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#define K7_EVNTSEL_OS (1 << 17)
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#define K7_EVNTSEL_USR (1 << 16)
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#define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
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#define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
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static int setup_k7_watchdog(void)
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{
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unsigned int perfctr_msr, evntsel_msr;
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unsigned int evntsel;
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struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
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nmi_perfctr_msr = MSR_K7_PERFCTR0;
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if (!reserve_perfctr_nmi(nmi_perfctr_msr))
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perfctr_msr = MSR_K7_PERFCTR0;
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evntsel_msr = MSR_K7_EVNTSEL0;
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if (!reserve_perfctr_nmi(perfctr_msr))
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goto fail;
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if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0))
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if (!reserve_evntsel_nmi(evntsel_msr))
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goto fail1;
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/* Simulator may not support it */
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if (checking_wrmsrl(MSR_K7_EVNTSEL0, 0UL))
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if (checking_wrmsrl(evntsel_msr, 0UL))
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goto fail2;
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wrmsrl(MSR_K7_PERFCTR0, 0UL);
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wrmsrl(perfctr_msr, 0UL);
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evntsel = K7_EVNTSEL_INT
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| K7_EVNTSEL_OS
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| K7_EVNTSEL_USR
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| K7_NMI_EVENT;
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wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
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wrmsrl(MSR_K7_PERFCTR0, -((u64)cpu_khz * 1000 / nmi_hz));
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/* setup the timer */
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wrmsr(evntsel_msr, evntsel, 0);
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wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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evntsel |= K7_EVNTSEL_ENABLE;
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wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
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wrmsr(evntsel_msr, evntsel, 0);
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wd->perfctr_msr = perfctr_msr;
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wd->evntsel_msr = evntsel_msr;
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wd->cccr_msr = 0; //unused
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wd->check_bit = 1ULL<<63;
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return 1;
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fail2:
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release_evntsel_nmi(MSR_K7_EVNTSEL0);
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release_evntsel_nmi(evntsel_msr);
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fail1:
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release_perfctr_nmi(nmi_perfctr_msr);
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release_perfctr_nmi(perfctr_msr);
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fail:
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return 0;
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}
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static void stop_k7_watchdog(void)
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{
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struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
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wrmsr(wd->evntsel_msr, 0, 0);
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release_evntsel_nmi(wd->evntsel_msr);
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release_perfctr_nmi(wd->perfctr_msr);
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}
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/* Note that these events don't tick when the CPU idles. This means
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the frequency varies with CPU load. */
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#define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
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#define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
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#define P4_ESCR_OS (1<<3)
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#define P4_ESCR_USR (1<<2)
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#define P4_CCCR_OVF_PMI0 (1<<26)
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#define P4_CCCR_OVF_PMI1 (1<<27)
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#define P4_CCCR_THRESHOLD(N) ((N)<<20)
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#define P4_CCCR_COMPLEMENT (1<<19)
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#define P4_CCCR_COMPARE (1<<18)
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#define P4_CCCR_REQUIRED (3<<16)
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#define P4_CCCR_ESCR_SELECT(N) ((N)<<13)
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#define P4_CCCR_ENABLE (1<<12)
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#define P4_CCCR_OVF (1<<31)
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/* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
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CRU_ESCR0 (with any non-null event selector) through a complemented
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max threshold. [IA32-Vol3, Section 14.9.9] */
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static int setup_p4_watchdog(void)
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{
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unsigned int perfctr_msr, evntsel_msr, cccr_msr;
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unsigned int evntsel, cccr_val;
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unsigned int misc_enable, dummy;
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unsigned int ht_num;
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struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
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rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
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rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
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if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
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return 0;
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nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
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nmi_p4_cccr_val = P4_NMI_IQ_CCCR0;
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#ifdef CONFIG_SMP
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if (smp_num_siblings == 2)
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nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1;
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#endif
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/* detect which hyperthread we are on */
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if (smp_num_siblings == 2) {
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unsigned int ebx, apicid;
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if (!reserve_perfctr_nmi(nmi_perfctr_msr))
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ebx = cpuid_ebx(1);
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apicid = (ebx >> 24) & 0xff;
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ht_num = apicid & 1;
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} else
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#endif
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ht_num = 0;
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/* performance counters are shared resources
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* assign each hyperthread its own set
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* (re-use the ESCR0 register, seems safe
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* and keeps the cccr_val the same)
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*/
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if (!ht_num) {
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/* logical cpu 0 */
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perfctr_msr = MSR_P4_IQ_PERFCTR0;
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evntsel_msr = MSR_P4_CRU_ESCR0;
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cccr_msr = MSR_P4_IQ_CCCR0;
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cccr_val = P4_CCCR_OVF_PMI0 | P4_CCCR_ESCR_SELECT(4);
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} else {
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/* logical cpu 1 */
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perfctr_msr = MSR_P4_IQ_PERFCTR1;
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evntsel_msr = MSR_P4_CRU_ESCR0;
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cccr_msr = MSR_P4_IQ_CCCR1;
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cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
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}
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if (!reserve_perfctr_nmi(perfctr_msr))
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goto fail;
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if (!reserve_evntsel_nmi(MSR_P4_CRU_ESCR0))
|
||||
if (!reserve_evntsel_nmi(evntsel_msr))
|
||||
goto fail1;
|
||||
|
||||
wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
|
||||
wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
|
||||
Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz * 1000UL / nmi_hz));
|
||||
wrmsrl(MSR_P4_IQ_COUNTER0, -((u64)cpu_khz * 1000 / nmi_hz));
|
||||
evntsel = P4_ESCR_EVENT_SELECT(0x3F)
|
||||
| P4_ESCR_OS
|
||||
| P4_ESCR_USR;
|
||||
|
||||
cccr_val |= P4_CCCR_THRESHOLD(15)
|
||||
| P4_CCCR_COMPLEMENT
|
||||
| P4_CCCR_COMPARE
|
||||
| P4_CCCR_REQUIRED;
|
||||
|
||||
wrmsr(evntsel_msr, evntsel, 0);
|
||||
wrmsr(cccr_msr, cccr_val, 0);
|
||||
wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
|
||||
apic_write(APIC_LVTPC, APIC_DM_NMI);
|
||||
wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
|
||||
cccr_val |= P4_CCCR_ENABLE;
|
||||
wrmsr(cccr_msr, cccr_val, 0);
|
||||
|
||||
wd->perfctr_msr = perfctr_msr;
|
||||
wd->evntsel_msr = evntsel_msr;
|
||||
wd->cccr_msr = cccr_msr;
|
||||
wd->check_bit = 1ULL<<39;
|
||||
return 1;
|
||||
fail1:
|
||||
release_perfctr_nmi(nmi_perfctr_msr);
|
||||
release_perfctr_nmi(perfctr_msr);
|
||||
fail:
|
||||
return 0;
|
||||
}
|
||||
|
||||
void setup_apic_nmi_watchdog(void)
|
||||
static void stop_p4_watchdog(void)
|
||||
{
|
||||
struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
|
||||
|
||||
wrmsr(wd->cccr_msr, 0, 0);
|
||||
wrmsr(wd->evntsel_msr, 0, 0);
|
||||
|
||||
release_evntsel_nmi(wd->evntsel_msr);
|
||||
release_perfctr_nmi(wd->perfctr_msr);
|
||||
}
|
||||
|
||||
void setup_apic_nmi_watchdog(void *unused)
|
||||
{
|
||||
/* only support LOCAL and IO APICs for now */
|
||||
if ((nmi_watchdog != NMI_LOCAL_APIC) &&
|
||||
(nmi_watchdog != NMI_IO_APIC))
|
||||
return;
|
||||
|
||||
if (nmi_watchdog == NMI_LOCAL_APIC) {
|
||||
switch (boot_cpu_data.x86_vendor) {
|
||||
case X86_VENDOR_AMD:
|
||||
if (boot_cpu_data.x86 != 15)
|
||||
return;
|
||||
if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
|
||||
return;
|
||||
if (!setup_k7_watchdog())
|
||||
return;
|
||||
break;
|
||||
case X86_VENDOR_INTEL:
|
||||
if (boot_cpu_data.x86 != 15)
|
||||
return;
|
||||
if (!setup_p4_watchdog())
|
||||
return;
|
||||
break;
|
||||
|
||||
default:
|
||||
return;
|
||||
}
|
||||
lapic_nmi_owner = LAPIC_NMI_WATCHDOG;
|
||||
nmi_active = 1;
|
||||
}
|
||||
__get_cpu_var(nmi_watchdog_ctlblk.enabled) = 1;
|
||||
atomic_inc(&nmi_active);
|
||||
}
|
||||
|
||||
static void stop_apic_nmi_watchdog(void *unused)
|
||||
{
|
||||
/* only support LOCAL and IO APICs for now */
|
||||
if ((nmi_watchdog != NMI_LOCAL_APIC) &&
|
||||
(nmi_watchdog != NMI_IO_APIC))
|
||||
return;
|
||||
|
||||
if (nmi_watchdog == NMI_LOCAL_APIC) {
|
||||
switch (boot_cpu_data.x86_vendor) {
|
||||
case X86_VENDOR_AMD:
|
||||
if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
|
||||
return;
|
||||
stop_k7_watchdog();
|
||||
break;
|
||||
case X86_VENDOR_INTEL:
|
||||
stop_p4_watchdog();
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
}
|
||||
__get_cpu_var(nmi_watchdog_ctlblk.enabled) = 0;
|
||||
atomic_dec(&nmi_active);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -558,38 +686,52 @@ void __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
|
||||
{
|
||||
int sum;
|
||||
int touched = 0;
|
||||
struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
|
||||
u64 dummy;
|
||||
|
||||
/* check for other users first */
|
||||
if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
|
||||
== NOTIFY_STOP) {
|
||||
touched = 1;
|
||||
}
|
||||
|
||||
sum = read_pda(apic_timer_irqs);
|
||||
if (__get_cpu_var(nmi_touch)) {
|
||||
__get_cpu_var(nmi_touch) = 0;
|
||||
touched = 1;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86_MCE
|
||||
/* Could check oops_in_progress here too, but it's safer
|
||||
not too */
|
||||
if (atomic_read(&mce_entry) > 0)
|
||||
touched = 1;
|
||||
#endif
|
||||
/* if the apic timer isn't firing, this cpu isn't doing much */
|
||||
if (!touched && __get_cpu_var(last_irq_sum) == sum) {
|
||||
/*
|
||||
* Ayiee, looks like this CPU is stuck ...
|
||||
* wait a few IRQs (5 seconds) before doing the oops ...
|
||||
*/
|
||||
local_inc(&__get_cpu_var(alert_counter));
|
||||
if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz) {
|
||||
if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
|
||||
== NOTIFY_STOP) {
|
||||
local_set(&__get_cpu_var(alert_counter), 0);
|
||||
return;
|
||||
}
|
||||
if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz)
|
||||
die_nmi("NMI Watchdog detected LOCKUP on CPU %d\n", regs);
|
||||
}
|
||||
} else {
|
||||
__get_cpu_var(last_irq_sum) = sum;
|
||||
local_set(&__get_cpu_var(alert_counter), 0);
|
||||
}
|
||||
if (nmi_perfctr_msr) {
|
||||
if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
|
||||
|
||||
/* see if the nmi watchdog went off */
|
||||
if (wd->enabled) {
|
||||
if (nmi_watchdog == NMI_LOCAL_APIC) {
|
||||
rdmsrl(wd->perfctr_msr, dummy);
|
||||
if (dummy & wd->check_bit){
|
||||
/* this wasn't a watchdog timer interrupt */
|
||||
goto done;
|
||||
}
|
||||
|
||||
/* only Intel uses the cccr msr */
|
||||
if (wd->cccr_msr != 0) {
|
||||
/*
|
||||
* P4 quirks:
|
||||
* - An overflown perfctr will assert its interrupt
|
||||
@ -597,12 +739,18 @@ void __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
|
||||
* - LVTPC is masked on interrupt and must be
|
||||
* unmasked by the LVTPC handler.
|
||||
*/
|
||||
wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
|
||||
rdmsrl(wd->cccr_msr, dummy);
|
||||
dummy &= ~P4_CCCR_OVF;
|
||||
wrmsrl(wd->cccr_msr, dummy);
|
||||
apic_write(APIC_LVTPC, APIC_DM_NMI);
|
||||
}
|
||||
wrmsrl(nmi_perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
|
||||
/* start the cycle over again */
|
||||
wrmsrl(wd->perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
|
||||
}
|
||||
}
|
||||
done:
|
||||
return;
|
||||
}
|
||||
|
||||
static __kprobes int dummy_nmi_callback(struct pt_regs * regs, int cpu)
|
||||
{
|
||||
|
||||
@ -63,7 +63,7 @@ extern void release_perfctr_nmi(unsigned int);
|
||||
extern int reserve_evntsel_nmi(unsigned int);
|
||||
extern void release_evntsel_nmi(unsigned int);
|
||||
|
||||
extern void setup_apic_nmi_watchdog (void);
|
||||
extern void setup_apic_nmi_watchdog (void *);
|
||||
extern int reserve_lapic_nmi(void);
|
||||
extern void release_lapic_nmi(void);
|
||||
extern void disable_timer_nmi_watchdog(void);
|
||||
@ -73,6 +73,7 @@ extern void nmi_watchdog_tick (struct pt_regs * regs, unsigned reason);
|
||||
extern void nmi_watchdog_default(void);
|
||||
extern int setup_nmi_watchdog(char *);
|
||||
|
||||
extern atomic_t nmi_active;
|
||||
extern unsigned int nmi_watchdog;
|
||||
#define NMI_DEFAULT -1
|
||||
#define NMI_NONE 0
|
||||
|
||||
Loading…
Reference in New Issue
Block a user