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arm64: tegra: Device tree changes for v4.10-rc1
This adds initial support for Tegra186, the P3310 processor module as well as the P2771 development board. Not much is functional, but there is enough to boot to an initial ramdisk with debug serial output. -----BEGIN PGP SIGNATURE----- iQIwBAABCAAaBQJYMsltExx0cmVkaW5nQG52aWRpYS5jb20ACgkQ3SOs138+s6HY 8g/7Bf5ieQkhnW4fHAicTnX+5zXJEiQZrlCYfOzNq1nyGi/NBrcAVajQTRhL1g/k cSKESq7OrjmhAlhHUWEaHHicnzax6jLwrUaj/ozcAti5m8iXOz+JnD184fE3CqcJ 5DGp26k0vrPcc47u2SIWjx1u4coUssYxLjsyoR2NJPZkWYMKpPL7rK969PizlAID ajbixuLgd4N6utWPz2o3j+23hXf03rXaPrZ6d9khsAvGQBkQx4QJAIbsKJrBbGR9 UbZbTDPgJGmvpa12IK0tblTKbHahhAkxRj5dX8F4eCwZBVmYp9fx+qLLKKdzoO5R pZmMQiT24j0RNlC4CTPRI7wVBr6x5m1UtcuEq9exipsdocC1/AAm9iD5U09gX41T 7kBcQ/mIl62CSxoaNNjSoHi+hK+HRyqIcR2tjWe+HhkJONCcPi7zUZvtSkM85n7v 8z26KxFJpjpXd+Bg8oC3eIBbYxZOBoa5YzK4zDCA5znrGD0HSxUHtetYFru5LX7u sVLc+wXfAuqKS/uh8FzVtk/tTrjib82OngQkD5ofGn3IkXEuIueLU4o4C8VhNt1n 7bH3MwWoahcUWQiH1/GwXglw1X6J2wE6isvF9u08pYg0nIfZsSPvbRjRriZzgk1v dyBsZxnLpWGJPxly5H+3u9+XUetKPuZZs2EQxzwauoUNIjo= =iXdy -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.10-arm64-dt-numeric-ids' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64 Pull "arm64: tegra: Device tree changes for v4.10-rc1" from Thierry Reding: This adds initial support for Tegra186, the P3310 processor module as well as the P2771 development board. Not much is functional, but there is enough to boot to an initial ramdisk with debug serial output. * tag 'tegra-for-4.10-arm64-dt-numeric-ids' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 arm64: tegra: Add SDHCI controllers on Tegra186 arm64: tegra: Add I2C controllers on Tegra186 arm64: tegra: Add serial ports on Tegra186 arm64: tegra: Add CPU nodes for Tegra186 arm64: tegra: Add Tegra186 support
This commit is contained in:
Arnd Bergmann
commit
f21b65881c
@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb
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dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb
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dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb
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dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb
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dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb
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always := $(dtb-y)
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clean-files := *.dtb
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8
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
Normal file
8
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
Normal file
@ -0,0 +1,8 @@
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/dts-v1/;
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#include "tegra186-p3310.dtsi"
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/ {
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model = "NVIDIA Tegra186 P2771-0000 Development Board";
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compatible = "nvidia,p2771-0000", "nvidia,tegra186";
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};
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64
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
Normal file
64
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
Normal file
@ -0,0 +1,64 @@
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#include "tegra186.dtsi"
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/ {
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model = "NVIDIA Tegra186 P3310 Processor Module";
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compatible = "nvidia,p3310", "nvidia,tegra186";
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aliases {
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serial0 = &uarta;
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};
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chosen {
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bootargs = "earlycon console=ttyS0,115200n8";
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stdout-path = "serial0:115200n8";
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x80000000 0x2 0x00000000>;
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};
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serial@3100000 {
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status = "okay";
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};
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hsp@3c00000 {
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status = "okay";
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};
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cpus {
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cpu@0 {
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enable-method = "psci";
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};
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cpu@1 {
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enable-method = "psci";
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};
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cpu@2 {
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enable-method = "psci";
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};
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cpu@3 {
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enable-method = "psci";
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};
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cpu@4 {
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enable-method = "psci";
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};
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cpu@5 {
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enable-method = "psci";
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};
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};
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bpmp {
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status = "okay";
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};
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psci {
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compatible = "arm,psci-1.0";
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status = "okay";
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method = "smc";
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};
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};
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398
arch/arm64/boot/dts/nvidia/tegra186.dtsi
Normal file
398
arch/arm64/boot/dts/nvidia/tegra186.dtsi
Normal file
@ -0,0 +1,398 @@
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#include <dt-bindings/gpio/tegra186-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "nvidia,tegra186";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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gpio: gpio@2200000 {
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compatible = "nvidia,tegra186-gpio";
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reg-names = "security", "gpio";
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reg = <0x0 0x2200000 0x0 0x10000>,
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<0x0 0x2210000 0x0 0x10000>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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interrupt-controller;
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#gpio-cells = <2>;
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gpio-controller;
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};
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uarta: serial@3100000 {
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compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x03100000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp 55>;
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clock-names = "serial";
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resets = <&bpmp 47>;
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reset-names = "serial";
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status = "disabled";
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};
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uartb: serial@3110000 {
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compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x03110000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp 56>;
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clock-names = "serial";
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resets = <&bpmp 48>;
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reset-names = "serial";
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status = "disabled";
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};
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uartd: serial@3130000 {
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compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x03130000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp 77>;
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clock-names = "serial";
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resets = <&bpmp 50>;
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reset-names = "serial";
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status = "disabled";
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};
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uarte: serial@3140000 {
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compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x03140000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp 194>;
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clock-names = "serial";
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resets = <&bpmp 132>;
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reset-names = "serial";
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status = "disabled";
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};
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uartf: serial@3150000 {
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compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x03150000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp 195>;
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clock-names = "serial";
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resets = <&bpmp 111>;
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reset-names = "serial";
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status = "disabled";
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};
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gen1_i2c: i2c@3160000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x03160000 0x0 0x10000>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp 47>;
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clock-names = "div-clk";
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resets = <&bpmp 19>;
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reset-names = "i2c";
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status = "disabled";
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};
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cam_i2c: i2c@3180000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x03180000 0x0 0x10000>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp 75>;
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clock-names = "div-clk";
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resets = <&bpmp 21>;
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reset-names = "i2c";
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status = "disabled";
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};
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/* shares pads with dpaux1 */
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dp_aux_ch1_i2c: i2c@3190000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x03190000 0x0 0x10000>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp 86>;
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clock-names = "div-clk";
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resets = <&bpmp 22>;
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reset-names = "i2c";
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status = "disabled";
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};
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/* controlled by BPMP, should not be enabled */
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pwr_i2c: i2c@31a0000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x031a0000 0x0 0x10000>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp 48>;
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clock-names = "div-clk";
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resets = <&bpmp 23>;
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reset-names = "i2c";
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status = "disabled";
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};
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/* shares pads with dpaux0 */
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dp_aux_ch0_i2c: i2c@31b0000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x031b0000 0x0 0x10000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp 125>;
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clock-names = "div-clk";
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resets = <&bpmp 24>;
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reset-names = "i2c";
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status = "disabled";
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};
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gen7_i2c: i2c@31c0000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x031c0000 0x0 0x10000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp 182>;
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clock-names = "div-clk";
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resets = <&bpmp 81>;
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reset-names = "i2c";
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status = "disabled";
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};
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gen9_i2c: i2c@31e0000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x031e0000 0x0 0x10000>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp 183>;
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clock-names = "div-clk";
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resets = <&bpmp 83>;
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reset-names = "i2c";
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status = "disabled";
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};
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sdmmc1: sdhci@3400000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x03400000 0x0 0x10000>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp 52>;
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clock-names = "sdhci";
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resets = <&bpmp 33>;
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reset-names = "sdhci";
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status = "disabled";
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};
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sdmmc2: sdhci@3420000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x03420000 0x0 0x10000>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp 53>;
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clock-names = "sdhci";
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resets = <&bpmp 34>;
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reset-names = "sdhci";
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status = "disabled";
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};
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sdmmc3: sdhci@3440000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x03440000 0x0 0x10000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp 76>;
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clock-names = "sdhci";
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resets = <&bpmp 35>;
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reset-names = "sdhci";
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status = "disabled";
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};
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sdmmc4: sdhci@3460000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x03460000 0x0 0x10000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp 54>;
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clock-names = "sdhci";
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resets = <&bpmp 36>;
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reset-names = "sdhci";
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status = "disabled";
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};
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gic: interrupt-controller@3881000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x03881000 0x0 0x1000>,
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<0x0 0x03882000 0x0 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-parent = <&gic>;
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};
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hsp_top0: hsp@3c00000 {
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compatible = "nvidia,tegra186-hsp";
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reg = <0x0 0x03c00000 0x0 0xa0000>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "doorbell";
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#mbox-cells = <2>;
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status = "disabled";
|
||||
};
|
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gen2_i2c: i2c@c240000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x0c240000 0x0 0x10000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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||||
#size-cells = <0>;
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clocks = <&bpmp 218>;
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clock-names = "div-clk";
|
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resets = <&bpmp 20>;
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reset-names = "i2c";
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status = "disabled";
|
||||
};
|
||||
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gen8_i2c: i2c@c250000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x0c250000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&bpmp 219>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&bpmp 82>;
|
||||
reset-names = "i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartc: serial@c280000 {
|
||||
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x0c280000 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp 215>;
|
||||
clock-names = "serial";
|
||||
resets = <&bpmp 49>;
|
||||
reset-names = "serial";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uartg: serial@c290000 {
|
||||
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x0c290000 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp 216>;
|
||||
clock-names = "serial";
|
||||
resets = <&bpmp 112>;
|
||||
reset-names = "serial";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio_aon: gpio@c2f0000 {
|
||||
compatible = "nvidia,tegra186-gpio-aon";
|
||||
reg-names = "security", "gpio";
|
||||
reg = <0x0 0xc2f0000 0x0 0x1000>,
|
||||
<0x0 0xc2f1000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
sysram@30000000 {
|
||||
compatible = "nvidia,tegra186-sysram", "mmio-sram";
|
||||
reg = <0x0 0x30000000 0x0 0x50000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
|
||||
|
||||
cpu_bpmp_tx: shmem@4e000 {
|
||||
compatible = "nvidia,tegra186-bpmp-shmem";
|
||||
reg = <0x0 0x4e000 0x0 0x1000>;
|
||||
label = "cpu-bpmp-tx";
|
||||
pool;
|
||||
};
|
||||
|
||||
cpu_bpmp_rx: shmem@4f000 {
|
||||
compatible = "nvidia,tegra186-bpmp-shmem";
|
||||
reg = <0x0 0x4f000 0x0 0x1000>;
|
||||
label = "cpu-bpmp-rx";
|
||||
pool;
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "nvidia,tegra186-denver", "arm,armv8";
|
||||
device_type = "cpu";
|
||||
reg = <0x000>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "nvidia,tegra186-denver", "arm,armv8";
|
||||
device_type = "cpu";
|
||||
reg = <0x001>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
device_type = "cpu";
|
||||
reg = <0x100>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
device_type = "cpu";
|
||||
reg = <0x101>;
|
||||
};
|
||||
|
||||
cpu@4 {
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
device_type = "cpu";
|
||||
reg = <0x102>;
|
||||
};
|
||||
|
||||
cpu@5 {
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
device_type = "cpu";
|
||||
reg = <0x103>;
|
||||
};
|
||||
};
|
||||
|
||||
bpmp: bpmp {
|
||||
compatible = "nvidia,tegra186-bpmp";
|
||||
mboxes = <&hsp_top0 0 19>;
|
||||
shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
bpmp_i2c: i2c {
|
||||
compatible = "nvidia,tegra186-bpmp-i2c";
|
||||
nvidia,bpmp-bus-id = <5>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user