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net: axienet: Move reset before 64-bit DMA detection
64-bit DMA detection will fail if axienet was started before (by boot
loader, boot ROM, etc). In this state axienet will not start properly.
XAXIDMA_TX_CDESC_OFFSET + 4 register (MM2S_CURDESC_MSB) is used to detect
64-bit DMA capability here. But datasheet says: When DMACR.RS is 1
(axienet is in enabled state), CURDESC_PTR becomes Read Only (RO) and
is used to fetch the first descriptor. So iowrite32()/ioread32() trick
to this register to detect 64-bit DMA will not work.
So move axienet reset before 64-bit DMA detection.
Fixes: f735c40ed9
("net: axienet: Autodetect 64-bit DMA capability")
Signed-off-by: Maxim Kochetkov <fido_max@inbox.ru>
Reviewed-by: Robert Hancock <robert.hancock@calian.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Link: https://lore.kernel.org/r/20230622192245.116864-1-fido_max@inbox.ru
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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@ -2042,6 +2042,11 @@ static int axienet_probe(struct platform_device *pdev)
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goto cleanup_clk;
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}
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/* Reset core now that clocks are enabled, prior to accessing MDIO */
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ret = __axienet_device_reset(lp);
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if (ret)
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goto cleanup_clk;
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/* Autodetect the need for 64-bit DMA pointers.
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* When the IP is configured for a bus width bigger than 32 bits,
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* writing the MSB registers is mandatory, even if they are all 0.
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@ -2096,11 +2101,6 @@ static int axienet_probe(struct platform_device *pdev)
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lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
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lp->coalesce_usec_tx = XAXIDMA_DFT_TX_USEC;
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/* Reset core now that clocks are enabled, prior to accessing MDIO */
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ret = __axienet_device_reset(lp);
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if (ret)
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goto cleanup_clk;
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ret = axienet_mdio_setup(lp);
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if (ret)
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dev_warn(&pdev->dev,
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