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staging: tidspbridge: remove driver

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The driver has been broken and disabled for several kernel versions now.
It doesn't have a maintainer anymore, and most of the people who've
worked on it have moved on. There's also still a long list of issues in
the TODO file before it can be moved out of staging. Until someone can
put in the work to make the driver work again and move it out of
staging, remove it from the kernel.

Signed-off-by: Kristina Martšenko <kristina.martsenko@gmail.com>
Cc: Omar Ramirez Luna <omar.ramirez@copitl.com>
Cc: Suman Anna <s-anna@ti.com>
Cc: Felipe Contreras <felipe.contreras@gmail.com>
Cc: Ohad Ben-Cohen <ohad@wizery.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Kristina Martšenko 2014-07-16 02:30:18 +03:00 committed by Greg Kroah-Hartman
parent cb3aadaec8
commit f190be7f39
127 changed files with 0 additions and 44757 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
MAINTAINERS
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@ -8624,11 +8624,6 @@ W: http://www.linux-speakup.org/
S: Odd Fixes
F: drivers/staging/speakup/
STAGING - TI DSP BRIDGE DRIVERS
M: Omar Ramirez Luna <omar.ramirez@copitl.com>
S: Odd Fixes
F: drivers/staging/tidspbridge/
STAGING - USB ENE SM/MS CARD READER DRIVER
M: Al Cho <acho@novell.com>
S: Odd Fixes

2
drivers/staging/Kconfig
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@ -74,8 +74,6 @@ source "drivers/staging/iio/Kconfig"
source "drivers/staging/xgifb/Kconfig"
source "drivers/staging/tidspbridge/Kconfig"
source "drivers/staging/quickstart/Kconfig"
source "drivers/staging/emxx_udc/Kconfig"

1
drivers/staging/Makefile
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@ -31,7 +31,6 @@ obj-$(CONFIG_VME_BUS) += vme/
obj-$(CONFIG_DX_SEP) += sep/
obj-$(CONFIG_IIO) += iio/
obj-$(CONFIG_FB_XGI) += xgifb/
obj-$(CONFIG_TIDSPBRIDGE) += tidspbridge/
obj-$(CONFIG_ACPI_QUICKSTART) += quickstart/
obj-$(CONFIG_USB_EMXX) += emxx_udc/
obj-$(CONFIG_USB_ENESTORAGE) += keucr/

45
drivers/staging/tidspbridge/Documentation/CONTRIBUTORS
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@ -1,45 +0,0 @@
TI DSP/Bridge Driver - Contributors File
The DSP/Bridge project wish to thank all of its contributors, current bridge
driver is the result of the work of all of them. If any name is accidentally
omitted, let us know by sending a mail to omar.ramirez@ti.com or
x095840@ti.com.
Please keep the following list in alphabetical order.
Suman Anna
Sripal Bagadia
Felipe Balbi
Ohad Ben-Cohen
Phil Carmody
Deepak Chitriki
Felipe Contreras
Hiroshi Doyu
Seth Forshee
Ivan Gomez Castellanos
Mark Grosen
Ramesh Gupta G
Fernando Guzman Lugo
Axel Haslam
Janet Head
Shivananda Hebbar
Hari Kanigeri
Tony Lindgren
Antonio Luna
Hari Nagalla
Nishanth Menon
Ameya Palande
Vijay Pasam
Gilbert Pitney
Omar Ramirez Luna
Ernesto Ramos
Chris Ring
Larry Schiefer
Rebecca Schultz Zavin
Bhavin Shah
Andy Shevchenko
Jeff Taylor
Roman Tereshonkov
Armando Uribe de Leon
Nischal Varide
Wenbiao Wang

70
drivers/staging/tidspbridge/Documentation/README
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@ -1,70 +0,0 @@
Linux DSP/BIOS Bridge release
DSP/BIOS Bridge overview
========================
DSP/BIOS Bridge is designed for platforms that contain a GPP and one or more
attached DSPs. The GPP is considered the master or "host" processor, and the
attached DSPs are processing resources that can be utilized by applications
and drivers running on the GPP.
The abstraction that DSP/BIOS Bridge supplies, is a direct link between a GPP
program and a DSP task. This communication link is partitioned into two
types of sub-links: messaging (short, fixed-length packets) and data
streaming (multiple, large buffers). Each sub-link operates independently,
and features in-order delivery of data, meaning that messages are delivered
in the order they were submitted to the message link, and stream buffers are
delivered in the order they were submitted to the stream link.
In addition, a GPP client can specify what inputs and outputs a DSP task
uses. DSP tasks typically use message objects for passing control and status
information and stream objects for efficient streaming of real-time data.
GPP Software Architecture
=========================
A GPP application communicates with its associated DSP task running on the
DSP subsystem using the DSP/BIOS Bridge API. For example, a GPP audio
application can use the API to pass messages to a DSP task that is managing
data flowing from analog-to-digital converters (ADCs) to digital-to-analog
converters (DACs).
From the perspective of the GPP OS, the DSP is treated as just another
peripheral device. Most high level GPP OS typically support a device driver
model, whereby applications can safely access and share a hardware peripheral
through standard driver interfaces. Therefore, to allow multiple GPP
applications to share access to the DSP, the GPP side of DSP/BIOS Bridge
implements a device driver for the DSP.
Since driver interfaces are not always standard across GPP OS, and to provide
some level of interoperability of application code using DSP/BIOS Bridge
between GPP OS, DSP/BIOS Bridge provides a standard library of APIs which
wrap calls into the device driver. So, rather than calling GPP OS specific
driver interfaces, applications (and even other device drivers) can use the
standard API library directly.
DSP Software Architecture
=========================
For DSP/BIOS, DSP/BIOS Bridge adds a device-independent streaming I/O (STRM)
interface, a messaging interface (NODE), and a Resource Manager (RM) Server.
The RM Server runs as a task of DSP/BIOS and is subservient to commands
and queries from the GPP. It executes commands to start and stop DSP signal
processing nodes in response to GPP programs making requests through the
(GPP-side) API.
DSP tasks started by the RM Server are similar to any other DSP task with two
important differences: they must follow a specific task model consisting of
three C-callable functions (node create, execute, and delete), with specific
sets of arguments, and they have a pre-defined task environment established
by the RM Server.
Tasks started by the RM Server communicate using the STRM and NODE interfaces
and act as servers for their corresponding GPP clients, performing signal
processing functions as requested by messages sent by their GPP client.
Typically, a DSP task moves data from source devices to sink devices using
device independent I/O streams, performing application-specific processing
and transformations on the data while it is moved. For example, an audio
task might perform audio decompression (ADPCM, MPEG, CELP) on data received
from a GPP audio driver and then send the decompressed linear samples to a
digital-to-analog converter.

157
drivers/staging/tidspbridge/Documentation/error-codes
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@ -1,157 +0,0 @@
DSP/Bridge Error Code Guide
Success code is always taken as 0, except for one case where a success status
different than 0 can be possible, this is when enumerating a series of dsp
objects, if the enumeration doesn't have any more objects it is considered as a
successful case. In this case a positive ENODATA is returned (TODO: Change to
avoid this case).
Error codes are returned as a negative 1, if an specific code is expected, it
can be propagated to user space by reading errno symbol defined in errno.h, for
specific details on the implementation a copy of the standard used should be
read first.
The error codes used by this driver are:
[EPERM]
General driver failure.
According to the use case the following might apply:
- Device is in 'sleep/suspend' mode due to DPM.
- User cannot mark end of stream on an input channel.
- Requested operation is invalid for the node type.
- Invalid alignment for the node messaging buffer.
- The specified direction is invalid for the stream.
- Invalid stream mode.
[ENOENT]
The specified object or file was not found.
[ESRCH]
A shared memory buffer contained in a message or stream could not be mapped
to the GPP client process's virtual space.
[EIO]
Driver interface I/O error.
or:
- Unable to plug channel ISR for configured IRQ.
- No free I/O request packets are available.
[ENXIO]
Unable to find a named section in DSP executable or a non-existent memory
segment identifier was specified.
[EBADF]
General error for file handling:
- Unable to open file.
- Unable to read file.
- An error occurred while parsing the DSP executable file.
[ENOMEM]
A memory allocation failure occurred.
[EACCES]
- Unable to read content of DCD data section; this is typically caused by
improperly configured nodes.
- Unable to decode DCD data section content; this is typically caused by
changes to DSP/BIOS Bridge data structures.
- Unable to get pointer to DCD data section; this is typically caused by
improperly configured UUIDs.
- Unable to load file containing DCD data section; this is typically
caused by a missing COFF file.
- The specified COFF file does not contain a valid node registration
section.
[EFAULT]
Invalid pointer or handler.
[EEXIST]
Attempted to create a channel manager when one already exists.
[EINVAL]
Invalid argument.
[ESPIPE]
Symbol not found in the COFF file. DSPNode_Create will return this if
the iAlg function table for an xDAIS socket is not found in the COFF file.
In this case, force the symbol to be linked into the COFF file.
DSPNode_Create, DSPNode_Execute, and DSPNode_Delete will return this if
the create, execute, or delete phase function, respectively, could not be
found in the COFF file.
- No symbol table is loaded/found for this board.
- Unable to initialize the ZL COFF parsing module.
[EPIPE]
I/O is currently pending.
- End of stream was already requested on this output channel.
[EDOM]
A parameter is specified outside its valid range.
[ENOSYS]
The indicated operation is not supported.
[EIDRM]
During enumeration a change in the number or properties of the objects
has occurred.
[ECHRNG]
Attempt to created channel manager with too many channels or channel ID out
of range.
[EBADR]
The state of the specified object is incorrect for the requested operation.
- Invalid segment ID.
[ENODATA]
Unable to retrieve resource information from the registry.
- No more registry values.
[ETIME]
A timeout occurred before the requested operation could complete.
[ENOSR]
A stream has been issued the maximum number of buffers allowed in the
stream at once; buffers must be reclaimed from the stream before any more
can be issued.
- No free channels are available.
[EILSEQ]
Error occurred in a dynamic loader library function.
[EISCONN]
The Specified Connection already exists.
[ENOTCONN]
Nodes not connected.
[ETIMEDOUT]
Timeout occurred waiting for a response from the hardware.
- Wait for flush operation on an output channel timed out.
[ECONNREFUSED]
No more connections can be made for this node.
[EALREADY]
Channel is already in use.
[EREMOTEIO]
dwTimeOut parameter was CHNL_IOCNOWAIT, yet no I/O completions were
queued.
[ECANCELED]
I/O has been cancelled on this channel.
[ENOKEY]
Invalid subkey parameter.
- UUID not found in registry.

69
drivers/staging/tidspbridge/Kconfig
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@ -1,69 +0,0 @@
#
# DSP Bridge Driver Support
#
menuconfig TIDSPBRIDGE
tristate "DSP Bridge driver"
depends on ARCH_OMAP3 && !ARCH_MULTIPLATFORM && BROKEN
select MAILBOX
select OMAP2PLUS_MBOX
help
DSP/BIOS Bridge is designed for platforms that contain a GPP and
one or more attached DSPs. The GPP is considered the master or
"host" processor, and the attached DSPs are processing resources
that can be utilized by applications and drivers running on the GPP.
This driver depends on OMAP Mailbox (OMAP_MBOX_FWK).
config TIDSPBRIDGE_DVFS
bool "Enable Bridge Dynamic Voltage and Frequency Scaling (DVFS)"
depends on TIDSPBRIDGE && CPU_FREQ
help
DVFS allows DSP Bridge to initiate the operating point change to
scale the chip voltage and frequency in order to match the
performance and power consumption to the current processing
requirements.
config TIDSPBRIDGE_MEMPOOL_SIZE
hex "Physical memory pool size (Byte)"
depends on TIDSPBRIDGE
default 0x600000
help
Allocate specified size of memory at booting time to avoid allocation
failure under heavy memory fragmentation after some use time.
config TIDSPBRIDGE_RECOVERY
bool "Recovery Support"
depends on TIDSPBRIDGE
default y
help
In case of DSP fatal error, BRIDGE driver will try to
recover itself.
config TIDSPBRIDGE_CACHE_LINE_CHECK
bool "Check buffers to be 128 byte aligned"
depends on TIDSPBRIDGE
help
When the DSP processes data, the DSP cache controller loads 128-Byte
chunks (lines) from SDRAM and writes the data back in 128-Byte chunks.
If a DMM buffer does not start and end on a 128-Byte boundary, the data
preceding the start address (SA) from the 128-Byte boundary to the SA
and the data at addresses trailing the end address (EA) from the EA to
the next 128-Byte boundary will be loaded and written back as well.
This can lead to heap corruption. Say Y, to enforce the check for 128
byte alignment, buffers failing this check will be rejected.
config TIDSPBRIDGE_NTFY_PWRERR
bool "Notify power errors"
depends on TIDSPBRIDGE
help
Enable notifications to registered clients on the event of power error
trying to suspend bridge driver. Say Y, to signal this event as a fatal
error, this will require a bridge restart to recover.
config TIDSPBRIDGE_BACKTRACE
bool "Dump backtraces on fatal errors"
depends on TIDSPBRIDGE
help
Enable useful information to backtrace fatal errors. Say Y if you
want to dump information for testing purposes.

32
drivers/staging/tidspbridge/Makefile
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@ -1,32 +0,0 @@
obj-$(CONFIG_TIDSPBRIDGE) += tidspbridge.o
libgen = gen/gh.o
libcore = core/chnl_sm.o core/msg_sm.o core/io_sm.o core/tiomap3430.o \
core/tiomap3430_pwr.o core/tiomap_io.o \
core/ue_deh.o core/wdt.o core/dsp-clock.o core/sync.o
libpmgr = pmgr/chnl.o pmgr/io.o pmgr/msg.o pmgr/cod.o pmgr/dev.o pmgr/dspapi.o \
pmgr/dmm.o pmgr/cmm.o pmgr/dbll.o
librmgr = rmgr/dbdcd.o rmgr/disp.o rmgr/drv.o rmgr/mgr.o rmgr/node.o \
rmgr/proc.o rmgr/pwr.o rmgr/rmm.o rmgr/strm.o rmgr/dspdrv.o \
rmgr/nldr.o rmgr/drv_interface.o
libdload = dynload/cload.o dynload/getsection.o dynload/reloc.o \
dynload/tramp.o
libhw = hw/hw_mmu.o
tidspbridge-y := $(libgen) $(libservices) $(libcore) $(libpmgr) $(librmgr) \
$(libdload) $(libhw)
#Machine dependent
ccflags-y += -D_TI_ -D_DB_TIOMAP -DTMS32060 \
-DTICFG_PROC_VER -DTICFG_EVM_TYPE -DCHNL_SMCLASS \
-DCHNL_MESSAGES -DUSE_LEVEL_1_MACROS
ccflags-y += -Idrivers/staging/tidspbridge/include
ccflags-y += -Idrivers/staging/tidspbridge/services
ccflags-y += -Idrivers/staging/tidspbridge/core
ccflags-y += -Idrivers/staging/tidspbridge/pmgr
ccflags-y += -Idrivers/staging/tidspbridge/rmgr
ccflags-y += -Idrivers/staging/tidspbridge/dynload
ccflags-y += -Idrivers/staging/tidspbridge/hw
ccflags-y += -Iarch/arm

18
drivers/staging/tidspbridge/TODO
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@ -1,18 +0,0 @@
* Migrate to (and if necessary, extend) existing upstream code such as
iommu, wdt, mcbsp, gptimers
* Decouple hardware-specific code (e.g. bridge_brd_start/stop/delete/monitor)
* DOFF binary loader: consider pushing to user space. at the very least
eliminate the direct filesystem access
* Eliminate general services and libraries - use or extend existing kernel
libraries instead (e.g. gcf/lcm in nldr.c, global helpers in gen/)
* Eliminate direct manipulation of OMAP_SYSC_BASE
* Eliminate DSP_SUCCEEDED macros and their imposed redundant indentations
(adopt the kernel way of checking for return values)
* Audit interfaces exposed to user space
* Audit and clean up header files folder
* Use kernel coding style
* checkpatch.pl fixes
* allocate ext_mem_pool from consistent memory instead of using ioremap
Please send any patches to Greg Kroah-Hartman <greg@kroah.com>
and Omar Ramirez Luna <omar.ramirez@ti.com>.

45
drivers/staging/tidspbridge/core/_cmm.h
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@ -1,45 +0,0 @@
/*
* _cmm.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Private header file defining CMM manager objects and defines needed
* by IO manager to register shared memory regions when DSP base image
* is loaded(bridge_io_on_loaded).
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef _CMM_
#define _CMM_
/*
* These target side symbols define the beginning and ending addresses
* of the section of shared memory used for shared memory manager CMM.
* They are defined in the *cfg.cmd file by cdb code.
*/
#define SHM0_SHARED_BASE_SYM "_SHM0_BEG"
#define SHM0_SHARED_END_SYM "_SHM0_END"
#define SHM0_SHARED_RESERVED_BASE_SYM "_SHM0_RSVDSTRT"
/*
* Shared Memory Region #0(SHMSEG0) is used in the following way:
*
* |(_SHM0_BEG) | (_SHM0_RSVDSTRT) | (_SHM0_END)
* V V V
* ------------------------------------------------------------
* | DSP-side allocations | GPP-side allocations |
* ------------------------------------------------------------
*
*
*/
#endif /* _CMM_ */

35
drivers/staging/tidspbridge/core/_deh.h
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@ -1,35 +0,0 @@
/*
* _deh.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Private header for DEH module.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
* Copyright (C) 2010 Felipe Contreras
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef _DEH_
#define _DEH_
#include <dspbridge/ntfy.h>
#include <dspbridge/dspdefs.h>
/* DEH Manager: only one created per board: */
struct deh_mgr {
struct bridge_dev_context *bridge_context; /* Bridge context. */
struct ntfy_object *ntfy_obj; /* NTFY object */
/* MMU Fault DPC */
struct tasklet_struct dpc_tasklet;
};
#endif /* _DEH_ */

142
drivers/staging/tidspbridge/core/_msg_sm.h
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@ -1,142 +0,0 @@
/*
* _msg_sm.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Private header file defining msg_ctrl manager objects and defines needed
* by IO manager.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef _MSG_SM_
#define _MSG_SM_
#include <linux/list.h>
#include <dspbridge/msgdefs.h>
/*
* These target side symbols define the beginning and ending addresses
* of the section of shared memory used for messages. They are
* defined in the *cfg.cmd file by cdb code.
*/
#define MSG_SHARED_BUFFER_BASE_SYM "_MSG_BEG"
#define MSG_SHARED_BUFFER_LIMIT_SYM "_MSG_END"
#ifndef _CHNL_WORDSIZE
#define _CHNL_WORDSIZE 4 /* default _CHNL_WORDSIZE is 2 bytes/word */
#endif
/*
* ======== msg_ctrl ========
* There is a control structure for messages to the DSP, and a control
* structure for messages from the DSP. The shared memory region for
* transferring messages is partitioned as follows:
*
* ----------------------------------------------------------
* |Control | Messages from DSP | Control | Messages to DSP |
* ----------------------------------------------------------
*
* msg_ctrl control structure for messages to the DSP is used in the following
* way:
*
* buf_empty - This flag is set to FALSE by the GPP after it has output
* messages for the DSP. The DSP host driver sets it to
* TRUE after it has copied the messages.
* post_swi - Set to 1 by the GPP after it has written the messages,
* set the size, and set buf_empty to FALSE.
* The DSP Host driver uses SWI_andn of the post_swi field
* when a host interrupt occurs. The host driver clears
* this after posting the SWI.
* size - Number of messages to be read by the DSP.
*
* For messages from the DSP:
* buf_empty - This flag is set to FALSE by the DSP after it has output
* messages for the GPP. The DPC on the GPP sets it to
* TRUE after it has copied the messages.
* post_swi - Set to 1 the DPC on the GPP after copying the messages.
* size - Number of messages to be read by the GPP.
*/
struct msg_ctrl {
u32 buf_empty; /* to/from DSP buffer is empty */
u32 post_swi; /* Set to "1" to post msg_ctrl SWI */
u32 size; /* Number of messages to/from the DSP */
u32 resvd;
};
/*
* ======== msg_mgr ========
* The msg_mgr maintains a list of all MSG_QUEUEs. Each NODE object can
* have msg_queue to hold all messages that come up from the corresponding
* node on the DSP. The msg_mgr also has a shared queue of messages
* ready to go to the DSP.
*/
struct msg_mgr {
/* The first field must match that in msgobj.h */
/* Function interface to Bridge driver */
struct bridge_drv_interface *intf_fxns;
struct io_mgr *iomgr; /* IO manager */
struct list_head queue_list; /* List of MSG_QUEUEs */
spinlock_t msg_mgr_lock; /* For critical sections */
/* Signalled when MsgFrame is available */
struct sync_object *sync_event;
struct list_head msg_free_list; /* Free MsgFrames ready to be filled */
struct list_head msg_used_list; /* MsgFrames ready to go to DSP */
u32 msgs_pending; /* # of queued messages to go to DSP */
u32 max_msgs; /* Max # of msgs that fit in buffer */
msg_onexit on_exit; /* called when RMS_EXIT is received */
};
/*
* ======== msg_queue ========
* Each NODE has a msg_queue for receiving messages from the
* corresponding node on the DSP. The msg_queue object maintains a list
* of messages that have been sent to the host, but not yet read (MSG_Get),
* and a list of free frames that can be filled when new messages arrive
* from the DSP.
* The msg_queue's hSynEvent gets posted when a message is ready.
*/
struct msg_queue {
struct list_head list_elem;
struct msg_mgr *msg_mgr;
u32 max_msgs; /* Node message depth */
u32 msgq_id; /* Node environment pointer */
struct list_head msg_free_list; /* Free MsgFrames ready to be filled */
/* Filled MsgFramess waiting to be read */
struct list_head msg_used_list;
void *arg; /* Handle passed to mgr on_exit callback */
struct sync_object *sync_event; /* Signalled when message is ready */
struct sync_object *sync_done; /* For synchronizing cleanup */
struct sync_object *sync_done_ack; /* For synchronizing cleanup */
struct ntfy_object *ntfy_obj; /* For notification of message ready */
bool done; /* TRUE <==> deleting the object */
u32 io_msg_pend; /* Number of pending MSG_get/put calls */
};
/*
* ======== msg_dspmsg ========
*/
struct msg_dspmsg {
struct dsp_msg msg;
u32 msgq_id; /* Identifies the node the message goes to */
};
/*
* ======== msg_frame ========
*/
struct msg_frame {
struct list_head list_elem;
struct msg_dspmsg msg_data;
};
#endif /* _MSG_SM_ */

382
drivers/staging/tidspbridge/core/_tiomap.h
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@ -1,382 +0,0 @@
/*
* _tiomap.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Definitions and types private to this Bridge driver.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef _TIOMAP_
#define _TIOMAP_
/*
* XXX These powerdomain.h/clockdomain.h includes are wrong and should
* be removed. No driver should call pwrdm_* or clkdm_* functions
* directly; they should rely on OMAP core code to do this.
*/
#include <mach-omap2/powerdomain.h>
#include <mach-omap2/clockdomain.h>
/*
* XXX These mach-omap2/ includes are wrong and should be removed. No
* driver should read or write to PRM/CM registers directly; they
* should rely on OMAP core code to do this.
*/
#include <mach-omap2/cm3xxx.h>
#include <mach-omap2/prm-regbits-34xx.h>
#include <mach-omap2/cm-regbits-34xx.h>
#include <dspbridge/devdefs.h>
#include <hw_defs.h>
#include <dspbridge/dspioctl.h> /* for bridge_ioctl_extproc defn */
#include <dspbridge/sync.h>
#include <dspbridge/clk.h>
struct map_l4_peripheral {
u32 phys_addr;
u32 dsp_virt_addr;
};
#define ARM_MAILBOX_START 0xfffcf000
#define ARM_MAILBOX_LENGTH 0x800
/* New Registers in OMAP3.1 */
#define TESTBLOCK_ID_START 0xfffed400
#define TESTBLOCK_ID_LENGTH 0xff
/* ID Returned by OMAP1510 */
#define TBC_ID_VALUE 0xB47002F
#define SPACE_LENGTH 0x2000
#define API_CLKM_DPLL_DMA 0xfffec000
#define ARM_INTERRUPT_OFFSET 0xb00
#define BIOS24XX
#define L4_PERIPHERAL_NULL 0x0
#define DSPVA_PERIPHERAL_NULL 0x0
#define MAX_LOCK_TLB_ENTRIES 15
#define L4_PERIPHERAL_PRM 0x48306000 /*PRM L4 Peripheral */
#define DSPVA_PERIPHERAL_PRM 0x1181e000
#define L4_PERIPHERAL_SCM 0x48002000 /*SCM L4 Peripheral */
#define DSPVA_PERIPHERAL_SCM 0x1181f000
#define L4_PERIPHERAL_MMU 0x5D000000 /*MMU L4 Peripheral */
#define DSPVA_PERIPHERAL_MMU 0x11820000
#define L4_PERIPHERAL_CM 0x48004000 /* Core L4, Clock Management */
#define DSPVA_PERIPHERAL_CM 0x1181c000
#define L4_PERIPHERAL_PER 0x48005000 /* PER */
#define DSPVA_PERIPHERAL_PER 0x1181d000
#define L4_PERIPHERAL_GPIO1 0x48310000
#define DSPVA_PERIPHERAL_GPIO1 0x11809000
#define L4_PERIPHERAL_GPIO2 0x49050000
#define DSPVA_PERIPHERAL_GPIO2 0x1180a000
#define L4_PERIPHERAL_GPIO3 0x49052000
#define DSPVA_PERIPHERAL_GPIO3 0x1180b000
#define L4_PERIPHERAL_GPIO4 0x49054000
#define DSPVA_PERIPHERAL_GPIO4 0x1180c000
#define L4_PERIPHERAL_GPIO5 0x49056000
#define DSPVA_PERIPHERAL_GPIO5 0x1180d000
#define L4_PERIPHERAL_IVA2WDT 0x49030000
#define DSPVA_PERIPHERAL_IVA2WDT 0x1180e000
#define L4_PERIPHERAL_DISPLAY 0x48050000
#define DSPVA_PERIPHERAL_DISPLAY 0x1180f000
#define L4_PERIPHERAL_SSI 0x48058000
#define DSPVA_PERIPHERAL_SSI 0x11804000
#define L4_PERIPHERAL_GDD 0x48059000
#define DSPVA_PERIPHERAL_GDD 0x11805000
#define L4_PERIPHERAL_SS1 0x4805a000
#define DSPVA_PERIPHERAL_SS1 0x11806000
#define L4_PERIPHERAL_SS2 0x4805b000
#define DSPVA_PERIPHERAL_SS2 0x11807000
#define L4_PERIPHERAL_CAMERA 0x480BC000
#define DSPVA_PERIPHERAL_CAMERA 0x11819000
#define L4_PERIPHERAL_SDMA 0x48056000
#define DSPVA_PERIPHERAL_SDMA 0x11810000 /* 0x1181d000 conflict w/ PER */
#define L4_PERIPHERAL_UART1 0x4806a000
#define DSPVA_PERIPHERAL_UART1 0x11811000
#define L4_PERIPHERAL_UART2 0x4806c000
#define DSPVA_PERIPHERAL_UART2 0x11812000
#define L4_PERIPHERAL_UART3 0x49020000
#define DSPVA_PERIPHERAL_UART3 0x11813000
#define L4_PERIPHERAL_MCBSP1 0x48074000
#define DSPVA_PERIPHERAL_MCBSP1 0x11814000
#define L4_PERIPHERAL_MCBSP2 0x49022000
#define DSPVA_PERIPHERAL_MCBSP2 0x11815000
#define L4_PERIPHERAL_MCBSP3 0x49024000
#define DSPVA_PERIPHERAL_MCBSP3 0x11816000
#define L4_PERIPHERAL_MCBSP4 0x49026000
#define DSPVA_PERIPHERAL_MCBSP4 0x11817000
#define L4_PERIPHERAL_MCBSP5 0x48096000
#define DSPVA_PERIPHERAL_MCBSP5 0x11818000
#define L4_PERIPHERAL_GPTIMER5 0x49038000
#define DSPVA_PERIPHERAL_GPTIMER5 0x11800000
#define L4_PERIPHERAL_GPTIMER6 0x4903a000
#define DSPVA_PERIPHERAL_GPTIMER6 0x11801000
#define L4_PERIPHERAL_GPTIMER7 0x4903c000
#define DSPVA_PERIPHERAL_GPTIMER7 0x11802000
#define L4_PERIPHERAL_GPTIMER8 0x4903e000
#define DSPVA_PERIPHERAL_GPTIMER8 0x11803000
#define L4_PERIPHERAL_SPI1 0x48098000
#define DSPVA_PERIPHERAL_SPI1 0x1181a000
#define L4_PERIPHERAL_SPI2 0x4809a000
#define DSPVA_PERIPHERAL_SPI2 0x1181b000
#define L4_PERIPHERAL_MBOX 0x48094000
#define DSPVA_PERIPHERAL_MBOX 0x11808000
#define PM_GRPSEL_BASE 0x48307000
#define DSPVA_GRPSEL_BASE 0x11821000
#define L4_PERIPHERAL_SIDETONE_MCBSP2 0x49028000
#define DSPVA_PERIPHERAL_SIDETONE_MCBSP2 0x11824000
#define L4_PERIPHERAL_SIDETONE_MCBSP3 0x4902a000
#define DSPVA_PERIPHERAL_SIDETONE_MCBSP3 0x11825000
/* define a static array with L4 mappings */
static const struct map_l4_peripheral l4_peripheral_table[] = {
{L4_PERIPHERAL_MBOX, DSPVA_PERIPHERAL_MBOX},
{L4_PERIPHERAL_SCM, DSPVA_PERIPHERAL_SCM},
{L4_PERIPHERAL_MMU, DSPVA_PERIPHERAL_MMU},
{L4_PERIPHERAL_GPTIMER5, DSPVA_PERIPHERAL_GPTIMER5},
{L4_PERIPHERAL_GPTIMER6, DSPVA_PERIPHERAL_GPTIMER6},
{L4_PERIPHERAL_GPTIMER7, DSPVA_PERIPHERAL_GPTIMER7},
{L4_PERIPHERAL_GPTIMER8, DSPVA_PERIPHERAL_GPTIMER8},
{L4_PERIPHERAL_GPIO1, DSPVA_PERIPHERAL_GPIO1},
{L4_PERIPHERAL_GPIO2, DSPVA_PERIPHERAL_GPIO2},
{L4_PERIPHERAL_GPIO3, DSPVA_PERIPHERAL_GPIO3},
{L4_PERIPHERAL_GPIO4, DSPVA_PERIPHERAL_GPIO4},
{L4_PERIPHERAL_GPIO5, DSPVA_PERIPHERAL_GPIO5},
{L4_PERIPHERAL_IVA2WDT, DSPVA_PERIPHERAL_IVA2WDT},
{L4_PERIPHERAL_DISPLAY, DSPVA_PERIPHERAL_DISPLAY},
{L4_PERIPHERAL_SSI, DSPVA_PERIPHERAL_SSI},
{L4_PERIPHERAL_GDD, DSPVA_PERIPHERAL_GDD},
{L4_PERIPHERAL_SS1, DSPVA_PERIPHERAL_SS1},
{L4_PERIPHERAL_SS2, DSPVA_PERIPHERAL_SS2},
{L4_PERIPHERAL_UART1, DSPVA_PERIPHERAL_UART1},
{L4_PERIPHERAL_UART2, DSPVA_PERIPHERAL_UART2},
{L4_PERIPHERAL_UART3, DSPVA_PERIPHERAL_UART3},
{L4_PERIPHERAL_MCBSP1, DSPVA_PERIPHERAL_MCBSP1},
{L4_PERIPHERAL_MCBSP2, DSPVA_PERIPHERAL_MCBSP2},
{L4_PERIPHERAL_MCBSP3, DSPVA_PERIPHERAL_MCBSP3},
{L4_PERIPHERAL_MCBSP4, DSPVA_PERIPHERAL_MCBSP4},
{L4_PERIPHERAL_MCBSP5, DSPVA_PERIPHERAL_MCBSP5},
{L4_PERIPHERAL_CAMERA, DSPVA_PERIPHERAL_CAMERA},
{L4_PERIPHERAL_SPI1, DSPVA_PERIPHERAL_SPI1},
{L4_PERIPHERAL_SPI2, DSPVA_PERIPHERAL_SPI2},
{L4_PERIPHERAL_PRM, DSPVA_PERIPHERAL_PRM},
{L4_PERIPHERAL_CM, DSPVA_PERIPHERAL_CM},
{L4_PERIPHERAL_PER, DSPVA_PERIPHERAL_PER},
{PM_GRPSEL_BASE, DSPVA_GRPSEL_BASE},
{L4_PERIPHERAL_SIDETONE_MCBSP2, DSPVA_PERIPHERAL_SIDETONE_MCBSP2},
{L4_PERIPHERAL_SIDETONE_MCBSP3, DSPVA_PERIPHERAL_SIDETONE_MCBSP3},
{L4_PERIPHERAL_NULL, DSPVA_PERIPHERAL_NULL}
};
/*
* 15 10 0
* ---------------------------------
* |0|0|1|0|0|0|c|c|c|i|i|i|i|i|i|i|
* ---------------------------------
* | (class) | (module specific) |
*
* where c -> Externel Clock Command: Clk & Autoidle Disable/Enable
* i -> External Clock ID Timers 5,6,7,8, McBSP1,2 and WDT3
*/
/* MBX_PM_CLK_IDMASK: DSP External clock id mask. */
#define MBX_PM_CLK_IDMASK 0x7F
/* MBX_PM_CLK_CMDSHIFT: DSP External clock command shift. */
#define MBX_PM_CLK_CMDSHIFT 7
/* MBX_PM_CLK_CMDMASK: DSP External clock command mask. */
#define MBX_PM_CLK_CMDMASK 7
/* MBX_PM_MAX_RESOURCES: CORE 1 Clock resources. */
#define MBX_CORE1_RESOURCES 7
/* MBX_PM_MAX_RESOURCES: CORE 2 Clock Resources. */
#define MBX_CORE2_RESOURCES 1
/* MBX_PM_MAX_RESOURCES: TOTAL Clock Resources. */
#define MBX_PM_MAX_RESOURCES 11
/* Power Management Commands */
#define BPWR_DISABLE_CLOCK 0
#define BPWR_ENABLE_CLOCK 1
/* OMAP242x specific resources */
enum bpwr_ext_clock_id {
BPWR_GP_TIMER5 = 0x10,
BPWR_GP_TIMER6,
BPWR_GP_TIMER7,
BPWR_GP_TIMER8,
BPWR_WD_TIMER3,
BPWR_MCBSP1,
BPWR_MCBSP2,
BPWR_MCBSP3,
BPWR_MCBSP4,
BPWR_MCBSP5,
BPWR_SSI = 0x20
};
static const u32 bpwr_clkid[] = {
(u32) BPWR_GP_TIMER5,
(u32) BPWR_GP_TIMER6,
(u32) BPWR_GP_TIMER7,
(u32) BPWR_GP_TIMER8,
(u32) BPWR_WD_TIMER3,
(u32) BPWR_MCBSP1,
(u32) BPWR_MCBSP2,
(u32) BPWR_MCBSP3,
(u32) BPWR_MCBSP4,
(u32) BPWR_MCBSP5,
(u32) BPWR_SSI
};
struct bpwr_clk_t {
u32 clk_id;
enum dsp_clk_id clk;
};
static const struct bpwr_clk_t bpwr_clks[] = {
{(u32) BPWR_GP_TIMER5, DSP_CLK_GPT5},
{(u32) BPWR_GP_TIMER6, DSP_CLK_GPT6},
{(u32) BPWR_GP_TIMER7, DSP_CLK_GPT7},
{(u32) BPWR_GP_TIMER8, DSP_CLK_GPT8},
{(u32) BPWR_WD_TIMER3, DSP_CLK_WDT3},
{(u32) BPWR_MCBSP1, DSP_CLK_MCBSP1},
{(u32) BPWR_MCBSP2, DSP_CLK_MCBSP2},
{(u32) BPWR_MCBSP3, DSP_CLK_MCBSP3},
{(u32) BPWR_MCBSP4, DSP_CLK_MCBSP4},
{(u32) BPWR_MCBSP5, DSP_CLK_MCBSP5},
{(u32) BPWR_SSI, DSP_CLK_SSI}
};
/* Interrupt Register Offsets */
#define INTH_IT_REG_OFFSET 0x00 /* Interrupt register offset */
#define INTH_MASK_IT_REG_OFFSET 0x04 /* Mask Interrupt reg offset */
#define DSP_MAILBOX1_INT 10
/*
* Bit definition of Interrupt Level Registers
*/
/* Mail Box defines */
#define MB_ARM2DSP1_REG_OFFSET 0x00
#define MB_ARM2DSP1B_REG_OFFSET 0x04
#define MB_DSP2ARM1B_REG_OFFSET 0x0C
#define MB_ARM2DSP1_FLAG_REG_OFFSET 0x18
#define MB_ARM2DSP_FLAG 0x0001
#define MBOX_ARM2DSP HW_MBOX_ID0
#define MBOX_DSP2ARM HW_MBOX_ID1
#define MBOX_ARM HW_MBOX_U0_ARM
#define MBOX_DSP HW_MBOX_U1_DSP1
#define ENABLE true
#define DISABLE false
#define HIGH_LEVEL true
#define LOW_LEVEL false
/* Macro's */
#define CLEAR_BIT(reg, mask) (reg &= ~mask)
#define SET_BIT(reg, mask) (reg |= mask)
#define SET_GROUP_BITS16(reg, position, width, value) \
do {\
reg &= ~((0xFFFF >> (16 - (width))) << (position)); \
reg |= ((value & (0xFFFF >> (16 - (width)))) << (position)); \
} while (0);
#define CLEAR_BIT_INDEX(reg, index) (reg &= ~(1 << (index)))
/* This Bridge driver's device context: */
struct bridge_dev_context {
struct dev_object *dev_obj; /* Handle to Bridge device object. */
u32 dsp_base_addr; /* Arm's API to DSP virt base addr */
/*
* DSP External memory prog address as seen virtually by the OS on
* the host side.
*/
u32 dsp_ext_base_addr; /* See the comment above */
u32 api_reg_base; /* API mem map'd registers */
void __iomem *dsp_mmu_base; /* DSP MMU Mapped registers */
u32 api_clk_base; /* CLK Registers */
u32 dsp_clk_m2_base; /* DSP Clock Module m2 */
u32 public_rhea; /* Pub Rhea */
u32 int_addr; /* MB INTR reg */
u32 tc_endianism; /* TC Endianism register */
u32 test_base; /* DSP MMU Mapped registers */
u32 self_loop; /* Pointer to the selfloop */
u32 dsp_start_add; /* API Boot vector */
u32 internal_size; /* Internal memory size */
struct omap_mbox *mbox; /* Mail box handle */
struct cfg_hostres *resources; /* Host Resources */
/*
* Processor specific info is set when prog loaded and read from DCD.
* [See bridge_dev_ctrl()] PROC info contains DSP-MMU TLB entries.
*/
/* DMMU TLB entries */
struct bridge_ioctl_extproc atlb_entry[BRDIOCTL_NUMOFMMUTLB];
u32 brd_state; /* Last known board state. */
/* TC Settings */
bool tc_word_swap_on; /* Traffic Controller Word Swap */
struct pg_table_attrs *pt_attrs;
u32 dsp_per_clks;
};
/*
* If dsp_debug is true, do not branch to the DSP entry
* point and wait for DSP to boot.
*/
extern s32 dsp_debug;
/*
* ======== sm_interrupt_dsp ========
* Purpose:
* Set interrupt value & send an interrupt to the DSP processor(s).
* This is typically used when mailbox interrupt mechanisms allow data
* to be associated with interrupt such as for OMAP's CMD/DATA regs.
* Parameters:
* dev_context: Handle to Bridge driver defined device info.
* mb_val: Value associated with interrupt(e.g. mailbox value).
* Returns:
* 0: Interrupt sent;
* else: Unable to send interrupt.
* Requires:
* Ensures:
*/
int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val);
#endif /* _TIOMAP_ */

85
drivers/staging/tidspbridge/core/_tiomap_pwr.h
View File

@ -1,85 +0,0 @@
/*
* _tiomap_pwr.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Definitions and types for the DSP wake/sleep routines.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef _TIOMAP_PWR_
#define _TIOMAP_PWR_
#ifdef CONFIG_PM
extern s32 dsp_test_sleepstate;
#endif
extern struct mailbox_context mboxsetting;
/*
* ======== wake_dsp =========
* Wakes up the DSP from DeepSleep
*/
extern int wake_dsp(struct bridge_dev_context *dev_context,
void *pargs);
/*
* ======== sleep_dsp =========
* Places the DSP in DeepSleep.
*/
extern int sleep_dsp(struct bridge_dev_context *dev_context,
u32 dw_cmd, void *pargs);
/*
* ========interrupt_dsp========
* Sends an interrupt to DSP unconditionally.
*/
extern void interrupt_dsp(struct bridge_dev_context *dev_context,
u16 mb_val);
/*
* ======== wake_dsp =========
* Wakes up the DSP from DeepSleep
*/
extern int dsp_peripheral_clk_ctrl(struct bridge_dev_context
*dev_context, void *pargs);
/*
* ======== handle_hibernation_from_dsp ========
* Handle Hibernation requested from DSP
*/
int handle_hibernation_from_dsp(struct bridge_dev_context *dev_context);
/*
* ======== post_scale_dsp ========
* Handle Post Scale notification to DSP
*/
int post_scale_dsp(struct bridge_dev_context *dev_context,
void *pargs);
/*
* ======== pre_scale_dsp ========
* Handle Pre Scale notification to DSP
*/
int pre_scale_dsp(struct bridge_dev_context *dev_context,
void *pargs);
/*
* ======== handle_constraints_set ========
* Handle constraints request from DSP
*/
int handle_constraints_set(struct bridge_dev_context *dev_context,
void *pargs);
/*
* ======== dsp_clk_wakeup_event_ctrl ========
* This function sets the group selction bits for while
* enabling/disabling.
*/
void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable);
#endif /* _TIOMAP_PWR_ */

908
drivers/staging/tidspbridge/core/chnl_sm.c
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@ -1,908 +0,0 @@
/*
* chnl_sm.c
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Implements upper edge functions for Bridge driver channel module.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
/*
* The lower edge functions must be implemented by the Bridge driver
* writer, and are declared in chnl_sm.h.
*
* Care is taken in this code to prevent simultaneous access to channel
* queues from
* 1. Threads.
* 2. io_dpc(), scheduled from the io_isr() as an event.
*
* This is done primarily by:
* - Semaphores.
* - state flags in the channel object; and
* - ensuring the IO_Dispatch() routine, which is called from both
* CHNL_AddIOReq() and the DPC(if implemented), is not re-entered.
*
* Channel Invariant:
* There is an important invariant condition which must be maintained per
* channel outside of bridge_chnl_get_ioc() and IO_Dispatch(), violation of
* which may cause timeouts and/or failure of function sync_wait_on_event.
* This invariant condition is:
*
* list_empty(&pchnl->io_completions) ==> pchnl->sync_event is reset
* and
* !list_empty(&pchnl->io_completions) ==> pchnl->sync_event is set.
*/
#include <linux/types.h>
/* ----------------------------------- OS */
#include <dspbridge/host_os.h>
/* ----------------------------------- DSP/BIOS Bridge */
#include <dspbridge/dbdefs.h>
/* ----------------------------------- OS Adaptation Layer */
#include <dspbridge/sync.h>
/* ----------------------------------- Bridge Driver */
#include <dspbridge/dspdefs.h>
#include <dspbridge/dspchnl.h>
#include "_tiomap.h"
/* ----------------------------------- Platform Manager */
#include <dspbridge/dev.h>
/* ----------------------------------- Others */
#include <dspbridge/io_sm.h>
/* ----------------------------------- Define for This */
#define USERMODE_ADDR PAGE_OFFSET
#define MAILBOX_IRQ INT_MAIL_MPU_IRQ
/* ----------------------------------- Function Prototypes */
static int create_chirp_list(struct list_head *list, u32 chirps);
static void free_chirp_list(struct list_head *list);
static int search_free_channel(struct chnl_mgr *chnl_mgr_obj,
u32 *chnl);
/*
* ======== bridge_chnl_add_io_req ========
* Enqueue an I/O request for data transfer on a channel to the DSP.
* The direction (mode) is specified in the channel object. Note the DSP
* address is specified for channels opened in direct I/O mode.
*/
int bridge_chnl_add_io_req(struct chnl_object *chnl_obj, void *host_buf,
u32 byte_size, u32 buf_size,
u32 dw_dsp_addr, u32 dw_arg)
{
int status = 0;
struct chnl_object *pchnl = (struct chnl_object *)chnl_obj;
struct chnl_irp *chnl_packet_obj = NULL;
struct bridge_dev_context *dev_ctxt;
struct dev_object *dev_obj;
u8 dw_state;
bool is_eos;
struct chnl_mgr *chnl_mgr_obj;
u8 *host_sys_buf = NULL;
bool sched_dpc = false;
u16 mb_val = 0;
is_eos = (byte_size == 0);
/* Validate args */
if (!host_buf || !pchnl)
return -EFAULT;
if (is_eos && CHNL_IS_INPUT(pchnl->chnl_mode))
return -EPERM;
/*
* Check the channel state: only queue chirp if channel state
* allows it.
*/
dw_state = pchnl->state;
if (dw_state != CHNL_STATEREADY) {
if (dw_state & CHNL_STATECANCEL)
return -ECANCELED;
if ((dw_state & CHNL_STATEEOS) &&
CHNL_IS_OUTPUT(pchnl->chnl_mode))
return -EPIPE;
/* No other possible states left */
}
dev_obj = dev_get_first();
dev_get_bridge_context(dev_obj, &dev_ctxt);
if (!dev_ctxt)
return -EFAULT;
if (pchnl->chnl_type == CHNL_PCPY && pchnl->chnl_id > 1 && host_buf) {
if (!(host_buf < (void *)USERMODE_ADDR)) {
host_sys_buf = host_buf;
goto func_cont;
}
/* if addr in user mode, then copy to kernel space */
host_sys_buf = kmalloc(buf_size, GFP_KERNEL);
if (host_sys_buf == NULL)
return -ENOMEM;
if (CHNL_IS_OUTPUT(pchnl->chnl_mode)) {
status = copy_from_user(host_sys_buf, host_buf,
buf_size);
if (status) {
kfree(host_sys_buf);
host_sys_buf = NULL;
return -EFAULT;
}
}
}
func_cont:
/* Mailbox IRQ is disabled to avoid race condition with DMA/ZCPY
* channels. DPCCS is held to avoid race conditions with PCPY channels.
* If DPC is scheduled in process context (iosm_schedule) and any
* non-mailbox interrupt occurs, that DPC will run and break CS. Hence
* we disable ALL DPCs. We will try to disable ONLY IO DPC later. */
chnl_mgr_obj = pchnl->chnl_mgr_obj;
spin_lock_bh(&chnl_mgr_obj->chnl_mgr_lock);
omap_mbox_disable_irq(dev_ctxt->mbox, IRQ_RX);
if (pchnl->chnl_type == CHNL_PCPY) {
/* This is a processor-copy channel. */
if (CHNL_IS_OUTPUT(pchnl->chnl_mode)) {
/* Check buffer size on output channels for fit. */
if (byte_size > io_buf_size(
pchnl->chnl_mgr_obj->iomgr)) {
status = -EINVAL;
goto out;
}
}
}
/* Get a free chirp: */
if (list_empty(&pchnl->free_packets_list)) {
status = -EIO;
goto out;
}
chnl_packet_obj = list_first_entry(&pchnl->free_packets_list,
struct chnl_irp, link);
list_del(&chnl_packet_obj->link);
/* Enqueue the chirp on the chnl's IORequest queue: */
chnl_packet_obj->host_user_buf = chnl_packet_obj->host_sys_buf =
host_buf;
if (pchnl->chnl_type == CHNL_PCPY && pchnl->chnl_id > 1)
chnl_packet_obj->host_sys_buf = host_sys_buf;
/*
* Note: for dma chans dw_dsp_addr contains dsp address
* of SM buffer.
*/
/* DSP address */
chnl_packet_obj->dsp_tx_addr = dw_dsp_addr / chnl_mgr_obj->word_size;
chnl_packet_obj->byte_size = byte_size;
chnl_packet_obj->buf_size = buf_size;
/* Only valid for output channel */
chnl_packet_obj->arg = dw_arg;
chnl_packet_obj->status = (is_eos ? CHNL_IOCSTATEOS :
CHNL_IOCSTATCOMPLETE);
list_add_tail(&chnl_packet_obj->link, &pchnl->io_requests);
pchnl->cio_reqs++;
/*
* If end of stream, update the channel state to prevent
* more IOR's.
*/
if (is_eos)
pchnl->state |= CHNL_STATEEOS;
/* Request IO from the DSP */
io_request_chnl(chnl_mgr_obj->iomgr, pchnl,
(CHNL_IS_INPUT(pchnl->chnl_mode) ? IO_INPUT :
IO_OUTPUT), &mb_val);
sched_dpc = true;
out:
omap_mbox_enable_irq(dev_ctxt->mbox, IRQ_RX);
spin_unlock_bh(&chnl_mgr_obj->chnl_mgr_lock);
if (mb_val != 0)
sm_interrupt_dsp(dev_ctxt, mb_val);
/* Schedule a DPC, to do the actual data transfer */
if (sched_dpc)
iosm_schedule(chnl_mgr_obj->iomgr);
return status;
}
/*
* ======== bridge_chnl_cancel_io ========
* Return all I/O requests to the client which have not yet been
* transferred. The channel's I/O completion object is
* signalled, and all the I/O requests are queued as IOC's, with the
* status field set to CHNL_IOCSTATCANCEL.
* This call is typically used in abort situations, and is a prelude to
* chnl_close();
*/
int bridge_chnl_cancel_io(struct chnl_object *chnl_obj)
{
struct chnl_object *pchnl = (struct chnl_object *)chnl_obj;
u32 chnl_id = -1;
s8 chnl_mode;
struct chnl_irp *chirp, *tmp;
struct chnl_mgr *chnl_mgr_obj = NULL;
/* Check args: */
if (!pchnl || !pchnl->chnl_mgr_obj)
return -EFAULT;
chnl_id = pchnl->chnl_id;
chnl_mode = pchnl->chnl_mode;
chnl_mgr_obj = pchnl->chnl_mgr_obj;
/* Mark this channel as cancelled, to prevent further IORequests or
* IORequests or dispatching. */
spin_lock_bh(&chnl_mgr_obj->chnl_mgr_lock);
pchnl->state |= CHNL_STATECANCEL;
if (list_empty(&pchnl->io_requests)) {
spin_unlock_bh(&chnl_mgr_obj->chnl_mgr_lock);
return 0;
}
if (pchnl->chnl_type == CHNL_PCPY) {
/* Indicate we have no more buffers available for transfer: */
if (CHNL_IS_INPUT(pchnl->chnl_mode)) {
io_cancel_chnl(chnl_mgr_obj->iomgr, chnl_id);
} else {
/* Record that we no longer have output buffers
* available: */
chnl_mgr_obj->output_mask &= ~(1 << chnl_id);
}
}
/* Move all IOR's to IOC queue: */
list_for_each_entry_safe(chirp, tmp, &pchnl->io_requests, link) {
list_del(&chirp->link);
chirp->byte_size = 0;
chirp->status |= CHNL_IOCSTATCANCEL;
list_add_tail(&chirp->link, &pchnl->io_completions);
pchnl->cio_cs++;
pchnl->cio_reqs--;
}
spin_unlock_bh(&chnl_mgr_obj->chnl_mgr_lock);
return 0;
}
/*
* ======== bridge_chnl_close ========
* Purpose:
* Ensures all pending I/O on this channel is cancelled, discards all
* queued I/O completion notifications, then frees the resources allocated
* for this channel, and makes the corresponding logical channel id
* available for subsequent use.
*/
int bridge_chnl_close(struct chnl_object *chnl_obj)
{
int status;
struct chnl_object *pchnl = (struct chnl_object *)chnl_obj;
/* Check args: */
if (!pchnl)
return -EFAULT;
/* Cancel IO: this ensures no further IO requests or notifications */
status = bridge_chnl_cancel_io(chnl_obj);
if (status)
return status;
/* Invalidate channel object: Protects from CHNL_GetIOCompletion() */
/* Free the slot in the channel manager: */
pchnl->chnl_mgr_obj->channels[pchnl->chnl_id] = NULL;
spin_lock_bh(&pchnl->chnl_mgr_obj->chnl_mgr_lock);
pchnl->chnl_mgr_obj->open_channels -= 1;
spin_unlock_bh(&pchnl->chnl_mgr_obj->chnl_mgr_lock);
if (pchnl->ntfy_obj) {
ntfy_delete(pchnl->ntfy_obj);
kfree(pchnl->ntfy_obj);
pchnl->ntfy_obj = NULL;
}
/* Reset channel event: (NOTE: user_event freed in user context) */
if (pchnl->sync_event) {
sync_reset_event(pchnl->sync_event);
kfree(pchnl->sync_event);
pchnl->sync_event = NULL;
}
/* Free I/O request and I/O completion queues: */
free_chirp_list(&pchnl->io_completions);
pchnl->cio_cs = 0;
free_chirp_list(&pchnl->io_requests);
pchnl->cio_reqs = 0;
free_chirp_list(&pchnl->free_packets_list);
/* Release channel object. */
kfree(pchnl);
return status;
}
/*
* ======== bridge_chnl_create ========
* Create a channel manager object, responsible for opening new channels
* and closing old ones for a given board.
*/
int bridge_chnl_create(struct chnl_mgr **channel_mgr,
struct dev_object *hdev_obj,
const struct chnl_mgrattrs *mgr_attrts)
{
int status = 0;
struct chnl_mgr *chnl_mgr_obj = NULL;
u8 max_channels;
/* Allocate channel manager object */
chnl_mgr_obj = kzalloc(sizeof(struct chnl_mgr), GFP_KERNEL);
if (chnl_mgr_obj) {
/*
* The max_channels attr must equal the # of supported chnls for
* each transport(# chnls for PCPY = DDMA = ZCPY): i.e.
* mgr_attrts->max_channels = CHNL_MAXCHANNELS =
* DDMA_MAXDDMACHNLS = DDMA_MAXZCPYCHNLS.
*/
max_channels = CHNL_MAXCHANNELS + CHNL_MAXCHANNELS * CHNL_PCPY;
/* Create array of channels */
chnl_mgr_obj->channels = kzalloc(sizeof(struct chnl_object *)
* max_channels, GFP_KERNEL);
if (chnl_mgr_obj->channels) {
/* Initialize chnl_mgr object */
chnl_mgr_obj->type = CHNL_TYPESM;
chnl_mgr_obj->word_size = mgr_attrts->word_size;
/* Total # chnls supported */
chnl_mgr_obj->max_channels = max_channels;
chnl_mgr_obj->open_channels = 0;
chnl_mgr_obj->output_mask = 0;
chnl_mgr_obj->last_output = 0;
chnl_mgr_obj->dev_obj = hdev_obj;
spin_lock_init(&chnl_mgr_obj->chnl_mgr_lock);
} else {
status = -ENOMEM;
}
} else {
status = -ENOMEM;
}
if (status) {
bridge_chnl_destroy(chnl_mgr_obj);
*channel_mgr = NULL;
} else {
/* Return channel manager object to caller... */
*channel_mgr = chnl_mgr_obj;
}
return status;
}
/*
* ======== bridge_chnl_destroy ========
* Purpose:
* Close all open channels, and destroy the channel manager.
*/
int bridge_chnl_destroy(struct chnl_mgr *hchnl_mgr)
{
int status = 0;
struct chnl_mgr *chnl_mgr_obj = hchnl_mgr;
u32 chnl_id;
if (hchnl_mgr) {
/* Close all open channels: */
for (chnl_id = 0; chnl_id < chnl_mgr_obj->max_channels;
chnl_id++) {
status =
bridge_chnl_close(chnl_mgr_obj->channels
[chnl_id]);
if (status)
dev_dbg(bridge, "%s: Error status 0x%x\n",
__func__, status);
}
/* Free channel manager object: */
kfree(chnl_mgr_obj->channels);
/* Set hchnl_mgr to NULL in device object. */
dev_set_chnl_mgr(chnl_mgr_obj->dev_obj, NULL);
/* Free this Chnl Mgr object: */
kfree(hchnl_mgr);
} else {
status = -EFAULT;
}
return status;
}
/*
* ======== bridge_chnl_flush_io ========
* purpose:
* Flushes all the outstanding data requests on a channel.
*/
int bridge_chnl_flush_io(struct chnl_object *chnl_obj, u32 timeout)
{
int status = 0;
struct chnl_object *pchnl = (struct chnl_object *)chnl_obj;
s8 chnl_mode = -1;
struct chnl_mgr *chnl_mgr_obj;
struct chnl_ioc chnl_ioc_obj;
/* Check args: */
if (pchnl) {
if ((timeout == CHNL_IOCNOWAIT)
&& CHNL_IS_OUTPUT(pchnl->chnl_mode)) {
status = -EINVAL;
} else {
chnl_mode = pchnl->chnl_mode;
chnl_mgr_obj = pchnl->chnl_mgr_obj;
}
} else {
status = -EFAULT;
}
if (!status) {
/* Note: Currently, if another thread continues to add IO
* requests to this channel, this function will continue to
* flush all such queued IO requests. */
if (CHNL_IS_OUTPUT(chnl_mode)
&& (pchnl->chnl_type == CHNL_PCPY)) {
/* Wait for IO completions, up to the specified
* timeout: */
while (!list_empty(&pchnl->io_requests) && !status) {
status = bridge_chnl_get_ioc(chnl_obj,
timeout, &chnl_ioc_obj);
if (status)
continue;
if (chnl_ioc_obj.status & CHNL_IOCSTATTIMEOUT)
status = -ETIMEDOUT;
}
} else {
status = bridge_chnl_cancel_io(chnl_obj);
/* Now, leave the channel in the ready state: */
pchnl->state &= ~CHNL_STATECANCEL;
}
}
return status;
}
/*
* ======== bridge_chnl_get_info ========
* Purpose:
* Retrieve information related to a channel.
*/
int bridge_chnl_get_info(struct chnl_object *chnl_obj,
struct chnl_info *channel_info)
{
int status = 0;
struct chnl_object *pchnl = (struct chnl_object *)chnl_obj;
if (channel_info != NULL) {
if (pchnl) {
/* Return the requested information: */
channel_info->chnl_mgr = pchnl->chnl_mgr_obj;
channel_info->event_obj = pchnl->user_event;
channel_info->cnhl_id = pchnl->chnl_id;
channel_info->mode = pchnl->chnl_mode;
channel_info->bytes_tx = pchnl->bytes_moved;
channel_info->process = pchnl->process;
channel_info->sync_event = pchnl->sync_event;
channel_info->cio_cs = pchnl->cio_cs;
channel_info->cio_reqs = pchnl->cio_reqs;
channel_info->state = pchnl->state;
} else {
status = -EFAULT;
}
} else {
status = -EFAULT;
}
return status;
}
/*
* ======== bridge_chnl_get_ioc ========
* Optionally wait for I/O completion on a channel. Dequeue an I/O
* completion record, which contains information about the completed
* I/O request.
* Note: Ensures Channel Invariant (see notes above).
*/
int bridge_chnl_get_ioc(struct chnl_object *chnl_obj, u32 timeout,
struct chnl_ioc *chan_ioc)
{
int status = 0;
struct chnl_object *pchnl = (struct chnl_object *)chnl_obj;
struct chnl_irp *chnl_packet_obj;
int stat_sync;
bool dequeue_ioc = true;
struct chnl_ioc ioc = { NULL, 0, 0, 0, 0 };
u8 *host_sys_buf = NULL;
struct bridge_dev_context *dev_ctxt;
struct dev_object *dev_obj;
/* Check args: */
if (!chan_ioc || !pchnl) {
status = -EFAULT;
} else if (timeout == CHNL_IOCNOWAIT) {
if (list_empty(&pchnl->io_completions))
status = -EREMOTEIO;
}
dev_obj = dev_get_first();
dev_get_bridge_context(dev_obj, &dev_ctxt);
if (!dev_ctxt)
status = -EFAULT;
if (status)
goto func_end;
ioc.status = CHNL_IOCSTATCOMPLETE;
if (timeout !=
CHNL_IOCNOWAIT && list_empty(&pchnl->io_completions)) {
if (timeout == CHNL_IOCINFINITE)
timeout = SYNC_INFINITE;
stat_sync = sync_wait_on_event(pchnl->sync_event, timeout);
if (stat_sync == -ETIME) {
/* No response from DSP */
ioc.status |= CHNL_IOCSTATTIMEOUT;
dequeue_ioc = false;
} else if (stat_sync == -EPERM) {
/* This can occur when the user mode thread is
* aborted (^C), or when _VWIN32_WaitSingleObject()
* fails due to unknown causes. */
/* Even though Wait failed, there may be something in
* the Q: */
if (list_empty(&pchnl->io_completions)) {
ioc.status |= CHNL_IOCSTATCANCEL;
dequeue_ioc = false;
}
}
}
/* See comment in AddIOReq */
spin_lock_bh(&pchnl->chnl_mgr_obj->chnl_mgr_lock);
omap_mbox_disable_irq(dev_ctxt->mbox, IRQ_RX);
if (dequeue_ioc) {
/* Dequeue IOC and set chan_ioc; */
chnl_packet_obj = list_first_entry(&pchnl->io_completions,
struct chnl_irp, link);
list_del(&chnl_packet_obj->link);
/* Update chan_ioc from channel state and chirp: */
pchnl->cio_cs--;
/*
* If this is a zero-copy channel, then set IOC's pbuf
* to the DSP's address. This DSP address will get
* translated to user's virtual addr later.
*/
host_sys_buf = chnl_packet_obj->host_sys_buf;
ioc.buf = chnl_packet_obj->host_user_buf;
ioc.byte_size = chnl_packet_obj->byte_size;
ioc.buf_size = chnl_packet_obj->buf_size;
ioc.arg = chnl_packet_obj->arg;
ioc.status |= chnl_packet_obj->status;
/* Place the used chirp on the free list: */
list_add_tail(&chnl_packet_obj->link,
&pchnl->free_packets_list);
} else {
ioc.buf = NULL;
ioc.byte_size = 0;
ioc.arg = 0;
ioc.buf_size = 0;
}
/* Ensure invariant: If any IOC's are queued for this channel... */
if (!list_empty(&pchnl->io_completions)) {
/* Since DSPStream_Reclaim() does not take a timeout
* parameter, we pass the stream's timeout value to
* bridge_chnl_get_ioc. We cannot determine whether or not
* we have waited in user mode. Since the stream's timeout
* value may be non-zero, we still have to set the event.
* Therefore, this optimization is taken out.
*
* if (timeout == CHNL_IOCNOWAIT) {
* ... ensure event is set..
* sync_set_event(pchnl->sync_event);
* } */
sync_set_event(pchnl->sync_event);
} else {
/* else, if list is empty, ensure event is reset. */
sync_reset_event(pchnl->sync_event);
}
omap_mbox_enable_irq(dev_ctxt->mbox, IRQ_RX);
spin_unlock_bh(&pchnl->chnl_mgr_obj->chnl_mgr_lock);
if (dequeue_ioc
&& (pchnl->chnl_type == CHNL_PCPY && pchnl->chnl_id > 1)) {
if (!(ioc.buf < (void *)USERMODE_ADDR))
goto func_cont;
/* If the addr is in user mode, then copy it */
if (!host_sys_buf || !ioc.buf) {
status = -EFAULT;
goto func_cont;
}
if (!CHNL_IS_INPUT(pchnl->chnl_mode))
goto func_cont1;
/*host_user_buf */
status = copy_to_user(ioc.buf, host_sys_buf, ioc.byte_size);
if (status) {
if (current->flags & PF_EXITING)
status = 0;
}
if (status)
status = -EFAULT;
func_cont1:
kfree(host_sys_buf);
}
func_cont:
/* Update User's IOC block: */
*chan_ioc = ioc;
func_end:
return status;
}
/*
* ======== bridge_chnl_get_mgr_info ========
* Retrieve information related to the channel manager.
*/
int bridge_chnl_get_mgr_info(struct chnl_mgr *hchnl_mgr, u32 ch_id,
struct chnl_mgrinfo *mgr_info)
{
struct chnl_mgr *chnl_mgr_obj = (struct chnl_mgr *)hchnl_mgr;
if (!mgr_info || !hchnl_mgr)
return -EFAULT;
if (ch_id > CHNL_MAXCHANNELS)
return -ECHRNG;
/* Return the requested information: */
mgr_info->chnl_obj = chnl_mgr_obj->channels[ch_id];
mgr_info->open_channels = chnl_mgr_obj->open_channels;
mgr_info->type = chnl_mgr_obj->type;
/* total # of chnls */
mgr_info->max_channels = chnl_mgr_obj->max_channels;
return 0;
}
/*
* ======== bridge_chnl_idle ========
* Idles a particular channel.
*/
int bridge_chnl_idle(struct chnl_object *chnl_obj, u32 timeout,
bool flush_data)
{
s8 chnl_mode;
struct chnl_mgr *chnl_mgr_obj;
int status = 0;
chnl_mode = chnl_obj->chnl_mode;
chnl_mgr_obj = chnl_obj->chnl_mgr_obj;
if (CHNL_IS_OUTPUT(chnl_mode) && !flush_data) {
/* Wait for IO completions, up to the specified timeout: */
status = bridge_chnl_flush_io(chnl_obj, timeout);
} else {
status = bridge_chnl_cancel_io(chnl_obj);
/* Reset the byte count and put channel back in ready state. */
chnl_obj->bytes_moved = 0;
chnl_obj->state &= ~CHNL_STATECANCEL;
}
return status;
}
/*
* ======== bridge_chnl_open ========
* Open a new half-duplex channel to the DSP board.
*/
int bridge_chnl_open(struct chnl_object **chnl,
struct chnl_mgr *hchnl_mgr, s8 chnl_mode,
u32 ch_id, const struct chnl_attr *pattrs)
{
int status = 0;
struct chnl_mgr *chnl_mgr_obj = hchnl_mgr;
struct chnl_object *pchnl = NULL;
struct sync_object *sync_event = NULL;
*chnl = NULL;
/* Validate Args: */
if (!pattrs->uio_reqs)
return -EINVAL;
if (!hchnl_mgr)
return -EFAULT;
if (ch_id != CHNL_PICKFREE) {
if (ch_id >= chnl_mgr_obj->max_channels)
return -ECHRNG;
if (chnl_mgr_obj->channels[ch_id] != NULL)
return -EALREADY;
} else {
/* Check for free channel */
status = search_free_channel(chnl_mgr_obj, &ch_id);
if (status)
return status;
}
/* Create channel object: */
pchnl = kzalloc(sizeof(struct chnl_object), GFP_KERNEL);
if (!pchnl)
return -ENOMEM;
/* Protect queues from io_dpc: */
pchnl->state = CHNL_STATECANCEL;
/* Allocate initial IOR and IOC queues: */
status = create_chirp_list(&pchnl->free_packets_list,
pattrs->uio_reqs);
if (status)
goto out_err;
INIT_LIST_HEAD(&pchnl->io_requests);
INIT_LIST_HEAD(&pchnl->io_completions);
pchnl->chnl_packets = pattrs->uio_reqs;
pchnl->cio_cs = 0;
pchnl->cio_reqs = 0;
sync_event = kzalloc(sizeof(struct sync_object), GFP_KERNEL);
if (!sync_event) {
status = -ENOMEM;
goto out_err;
}
sync_init_event(sync_event);
pchnl->ntfy_obj = kmalloc(sizeof(struct ntfy_object), GFP_KERNEL);
if (!pchnl->ntfy_obj) {
status = -ENOMEM;
goto out_err;
}
ntfy_init(pchnl->ntfy_obj);
/* Initialize CHNL object fields: */
pchnl->chnl_mgr_obj = chnl_mgr_obj;
pchnl->chnl_id = ch_id;
pchnl->chnl_mode = chnl_mode;
pchnl->user_event = sync_event;
pchnl->sync_event = sync_event;
/* Get the process handle */
pchnl->process = current->tgid;
pchnl->cb_arg = 0;
pchnl->bytes_moved = 0;
/* Default to proc-copy */
pchnl->chnl_type = CHNL_PCPY;
/* Insert channel object in channel manager: */
chnl_mgr_obj->channels[pchnl->chnl_id] = pchnl;
spin_lock_bh(&chnl_mgr_obj->chnl_mgr_lock);
chnl_mgr_obj->open_channels++;
spin_unlock_bh(&chnl_mgr_obj->chnl_mgr_lock);
/* Return result... */
pchnl->state = CHNL_STATEREADY;
*chnl = pchnl;
return status;
out_err:
/* Free memory */
free_chirp_list(&pchnl->io_completions);
free_chirp_list(&pchnl->io_requests);
free_chirp_list(&pchnl->free_packets_list);
kfree(sync_event);
if (pchnl->ntfy_obj) {
ntfy_delete(pchnl->ntfy_obj);
kfree(pchnl->ntfy_obj);
pchnl->ntfy_obj = NULL;
}
kfree(pchnl);
return status;
}
/*
* ======== bridge_chnl_register_notify ========
* Registers for events on a particular channel.
*/
int bridge_chnl_register_notify(struct chnl_object *chnl_obj,
u32 event_mask, u32 notify_type,
struct dsp_notification *hnotification)
{
int status = 0;
if (event_mask)
status = ntfy_register(chnl_obj->ntfy_obj, hnotification,
event_mask, notify_type);
else
status = ntfy_unregister(chnl_obj->ntfy_obj, hnotification);
return status;
}
/*
* ======== create_chirp_list ========
* Purpose:
* Initialize a queue of channel I/O Request/Completion packets.
* Parameters:
* list: Pointer to a list_head
* chirps: Number of Chirps to allocate.
* Returns:
* 0 if successful, error code otherwise.
* Requires:
* Ensures:
*/
static int create_chirp_list(struct list_head *list, u32 chirps)
{
struct chnl_irp *chirp;
u32 i;
INIT_LIST_HEAD(list);
/* Make N chirps and place on queue. */
for (i = 0; i < chirps; i++) {
chirp = kzalloc(sizeof(struct chnl_irp), GFP_KERNEL);
if (!chirp)
break;
list_add_tail(&chirp->link, list);
}
/* If we couldn't allocate all chirps, free those allocated: */
if (i != chirps) {
free_chirp_list(list);
return -ENOMEM;
}
return 0;
}
/*
* ======== free_chirp_list ========
* Purpose:
* Free the queue of Chirps.
*/
static void free_chirp_list(struct list_head *chirp_list)
{
struct chnl_irp *chirp, *tmp;
list_for_each_entry_safe(chirp, tmp, chirp_list, link) {
list_del(&chirp->link);
kfree(chirp);
}
}
/*
* ======== search_free_channel ========
* Search for a free channel slot in the array of channel pointers.
*/
static int search_free_channel(struct chnl_mgr *chnl_mgr_obj,
u32 *chnl)
{
int status = -ENOSR;
u32 i;
for (i = 0; i < chnl_mgr_obj->max_channels; i++) {
if (chnl_mgr_obj->channels[i] == NULL) {
status = 0;
*chnl = i;
break;
}
}
return status;
}

391
drivers/staging/tidspbridge/core/dsp-clock.c
View File

@ -1,391 +0,0 @@
/*
* clk.c
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Clock and Timer services.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#define L4_34XX_BASE 0x48000000
#include <linux/types.h>
/* ----------------------------------- Host OS */
#include <dspbridge/host_os.h>
#include <plat/dmtimer.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>
/* ----------------------------------- DSP/BIOS Bridge */
#include <dspbridge/dbdefs.h>
#include <dspbridge/drv.h>
#include <dspbridge/dev.h>
#include "_tiomap.h"
/* ----------------------------------- This */
#include <dspbridge/clk.h>
/* ----------------------------------- Defines, Data Structures, Typedefs */
#define OMAP_SSI_OFFSET 0x58000
#define OMAP_SSI_SIZE 0x1000
#define OMAP_SSI_SYSCONFIG_OFFSET 0x10
#define SSI_AUTOIDLE (1 << 0)
#define SSI_SIDLE_SMARTIDLE (2 << 3)
#define SSI_MIDLE_NOIDLE (1 << 12)
/* Clk types requested by the dsp */
#define IVA2_CLK 0
#define GPT_CLK 1
#define WDT_CLK 2
#define MCBSP_CLK 3
#define SSI_CLK 4
/* Bridge GPT id (1 - 4), DM Timer id (5 - 8) */
#define DMT_ID(id) ((id) + 4)
#define DM_TIMER_CLOCKS 4
/* Bridge MCBSP id (6 - 10), OMAP Mcbsp id (0 - 4) */
#define MCBSP_ID(id) ((id) - 6)
static struct omap_dm_timer *timer[4];
struct clk *iva2_clk;
struct dsp_ssi {
struct clk *sst_fck;
struct clk *ssr_fck;
struct clk *ick;
};
static struct dsp_ssi ssi;
static u32 dsp_clocks;
static inline u32 is_dsp_clk_active(u32 clk, u8 id)
{
return clk & (1 << id);
}
static inline void set_dsp_clk_active(u32 *clk, u8 id)
{
*clk |= (1 << id);
}
static inline void set_dsp_clk_inactive(u32 *clk, u8 id)
{
*clk &= ~(1 << id);
}
static s8 get_clk_type(u8 id)
{
s8 type;
if (id == DSP_CLK_IVA2)
type = IVA2_CLK;
else if (id <= DSP_CLK_GPT8)
type = GPT_CLK;
else if (id == DSP_CLK_WDT3)
type = WDT_CLK;
else if (id <= DSP_CLK_MCBSP5)
type = MCBSP_CLK;
else if (id == DSP_CLK_SSI)
type = SSI_CLK;
else
type = -1;
return type;
}
/*
* ======== dsp_clk_exit ========
* Purpose:
* Cleanup CLK module.
*/
void dsp_clk_exit(void)
{
int i;
dsp_clock_disable_all(dsp_clocks);
for (i = 0; i < DM_TIMER_CLOCKS; i++)
omap_dm_timer_free(timer[i]);
clk_unprepare(iva2_clk);
clk_put(iva2_clk);
clk_unprepare(ssi.sst_fck);
clk_put(ssi.sst_fck);
clk_unprepare(ssi.ssr_fck);
clk_put(ssi.ssr_fck);
clk_unprepare(ssi.ick);
clk_put(ssi.ick);
}
/*
* ======== dsp_clk_init ========
* Purpose:
* Initialize CLK module.
*/
void dsp_clk_init(void)
{
static struct platform_device dspbridge_device;
int i, id;
dspbridge_device.dev.bus = &platform_bus_type;
for (i = 0, id = 5; i < DM_TIMER_CLOCKS; i++, id++)
timer[i] = omap_dm_timer_request_specific(id);
iva2_clk = clk_get(&dspbridge_device.dev, "iva2_ck");
if (IS_ERR(iva2_clk))
dev_err(bridge, "failed to get iva2 clock %p\n", iva2_clk);
else
clk_prepare(iva2_clk);
ssi.sst_fck = clk_get(&dspbridge_device.dev, "ssi_sst_fck");
ssi.ssr_fck = clk_get(&dspbridge_device.dev, "ssi_ssr_fck");
ssi.ick = clk_get(&dspbridge_device.dev, "ssi_ick");
if (IS_ERR(ssi.sst_fck) || IS_ERR(ssi.ssr_fck) || IS_ERR(ssi.ick)) {
dev_err(bridge, "failed to get ssi: sst %p, ssr %p, ick %p\n",
ssi.sst_fck, ssi.ssr_fck, ssi.ick);
} else {
clk_prepare(ssi.sst_fck);
clk_prepare(ssi.ssr_fck);
clk_prepare(ssi.ick);
}
}
/**
* dsp_gpt_wait_overflow - set gpt overflow and wait for fixed timeout
* @clk_id: GP Timer clock id.
* @load: Overflow value.
*
* Sets an overflow interrupt for the desired GPT waiting for a timeout
* of 5 msecs for the interrupt to occur.
*/
void dsp_gpt_wait_overflow(short int clk_id, unsigned int load)
{
struct omap_dm_timer *gpt = timer[clk_id - 1];
unsigned long timeout;
if (!gpt)
return;
/* Enable overflow interrupt */
omap_dm_timer_set_int_enable(gpt, OMAP_TIMER_INT_OVERFLOW);
/*
* Set counter value to overflow counter after
* one tick and start timer.
*/
omap_dm_timer_set_load_start(gpt, 0, load);
/* Wait 80us for timer to overflow */
udelay(80);
timeout = msecs_to_jiffies(5);
/* Check interrupt status and wait for interrupt */
while (!(omap_dm_timer_read_status(gpt) & OMAP_TIMER_INT_OVERFLOW)) {
if (time_is_after_jiffies(timeout)) {
pr_err("%s: GPTimer interrupt failed\n", __func__);
break;
}
}
}
/*
* ======== dsp_clk_enable ========
* Purpose:
* Enable Clock .
*
*/
int dsp_clk_enable(enum dsp_clk_id clk_id)
{
int status = 0;
if (is_dsp_clk_active(dsp_clocks, clk_id)) {
dev_err(bridge, "WARN: clock id %d already enabled\n", clk_id);
goto out;
}
switch (get_clk_type(clk_id)) {
case IVA2_CLK:
clk_enable(iva2_clk);
break;
case GPT_CLK:
status = omap_dm_timer_start(timer[clk_id - 1]);
break;
#ifdef CONFIG_SND_OMAP_SOC_MCBSP
case MCBSP_CLK:
omap_mcbsp_request(MCBSP_ID(clk_id));
omap2_mcbsp_set_clks_src(MCBSP_ID(clk_id), MCBSP_CLKS_PAD_SRC);
break;
#endif
case WDT_CLK:
dev_err(bridge, "ERROR: DSP requested to enable WDT3 clk\n");
break;
case SSI_CLK:
clk_enable(ssi.sst_fck);
clk_enable(ssi.ssr_fck);
clk_enable(ssi.ick);
/*
* The SSI module need to configured not to have the Forced
* idle for master interface. If it is set to forced idle,
* the SSI module is transitioning to standby thereby causing
* the client in the DSP hang waiting for the SSI module to
* be active after enabling the clocks
*/
ssi_clk_prepare(true);
break;
default:
dev_err(bridge, "Invalid clock id for enable\n");
status = -EPERM;
}
if (!status)
set_dsp_clk_active(&dsp_clocks, clk_id);
out:
return status;
}
/**
* dsp_clock_enable_all - Enable clocks used by the DSP
* @dev_context Driver's device context strucure
*
* This function enables all the peripheral clocks that were requested by DSP.
*/
u32 dsp_clock_enable_all(u32 dsp_per_clocks)
{
u32 clk_id;
u32 status = -EPERM;
for (clk_id = 0; clk_id < DSP_CLK_NOT_DEFINED; clk_id++) {
if (is_dsp_clk_active(dsp_per_clocks, clk_id))
status = dsp_clk_enable(clk_id);
}
return status;
}
/*
* ======== dsp_clk_disable ========
* Purpose:
* Disable the clock.
*
*/
int dsp_clk_disable(enum dsp_clk_id clk_id)
{
int status = 0;
if (!is_dsp_clk_active(dsp_clocks, clk_id)) {
dev_err(bridge, "ERR: clock id %d already disabled\n", clk_id);
goto out;
}
switch (get_clk_type(clk_id)) {
case IVA2_CLK:
clk_disable(iva2_clk);
break;
case GPT_CLK:
status = omap_dm_timer_stop(timer[clk_id - 1]);
break;
#ifdef CONFIG_SND_OMAP_SOC_MCBSP
case MCBSP_CLK:
omap2_mcbsp_set_clks_src(MCBSP_ID(clk_id), MCBSP_CLKS_PRCM_SRC);
omap_mcbsp_free(MCBSP_ID(clk_id));
break;
#endif
case WDT_CLK:
dev_err(bridge, "ERROR: DSP requested to disable WDT3 clk\n");
break;
case SSI_CLK:
ssi_clk_prepare(false);
ssi_clk_prepare(false);
clk_disable(ssi.sst_fck);
clk_disable(ssi.ssr_fck);
clk_disable(ssi.ick);
break;
default:
dev_err(bridge, "Invalid clock id for disable\n");
status = -EPERM;
}
if (!status)
set_dsp_clk_inactive(&dsp_clocks, clk_id);
out:
return status;
}
/**
* dsp_clock_disable_all - Disable all active clocks
* @dev_context Driver's device context structure
*
* This function disables all the peripheral clocks that were enabled by DSP.
* It is meant to be called only when DSP is entering hibernation or when DSP
* is in error state.
*/
u32 dsp_clock_disable_all(u32 dsp_per_clocks)
{
u32 clk_id;
u32 status = -EPERM;
for (clk_id = 0; clk_id < DSP_CLK_NOT_DEFINED; clk_id++) {
if (is_dsp_clk_active(dsp_per_clocks, clk_id))
status = dsp_clk_disable(clk_id);
}
return status;
}
u32 dsp_clk_get_iva2_rate(void)
{
u32 clk_speed_khz;
clk_speed_khz = clk_get_rate(iva2_clk);
clk_speed_khz /= 1000;
dev_dbg(bridge, "%s: clk speed Khz = %d\n", __func__, clk_speed_khz);
return clk_speed_khz;
}
void ssi_clk_prepare(bool FLAG)
{
void __iomem *ssi_base;
unsigned int value;
ssi_base = ioremap(L4_34XX_BASE + OMAP_SSI_OFFSET, OMAP_SSI_SIZE);
if (!ssi_base) {
pr_err("%s: error, SSI not configured\n", __func__);
return;
}
if (FLAG) {
/* Set Autoidle, SIDLEMode to smart idle, and MIDLEmode to
* no idle
*/
value = SSI_AUTOIDLE | SSI_SIDLE_SMARTIDLE | SSI_MIDLE_NOIDLE;
} else {
/* Set Autoidle, SIDLEMode to forced idle, and MIDLEmode to
* forced idle
*/
value = SSI_AUTOIDLE;
}
__raw_writel(value, ssi_base + OMAP_SSI_SYSCONFIG_OFFSET);
iounmap(ssi_base);
}

2246
drivers/staging/tidspbridge/core/io_sm.c
View File

File diff suppressed because it is too large Load Diff

564
drivers/staging/tidspbridge/core/msg_sm.c
View File

@ -1,564 +0,0 @@
/*
* msg_sm.c
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Implements upper edge functions for Bridge message module.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#include <linux/types.h>
/* ----------------------------------- DSP/BIOS Bridge */
#include <dspbridge/dbdefs.h>
/* ----------------------------------- OS Adaptation Layer */
#include <dspbridge/sync.h>
/* ----------------------------------- Platform Manager */
#include <dspbridge/dev.h>
/* ----------------------------------- Others */
#include <dspbridge/io_sm.h>
/* ----------------------------------- This */
#include <_msg_sm.h>
#include <dspbridge/dspmsg.h>
/* ----------------------------------- Function Prototypes */
static int add_new_msg(struct list_head *msg_list);
static void delete_msg_mgr(struct msg_mgr *hmsg_mgr);
static void delete_msg_queue(struct msg_queue *msg_queue_obj, u32 num_to_dsp);
static void free_msg_list(struct list_head *msg_list);
/*
* ======== bridge_msg_create ========
* Create an object to manage message queues. Only one of these objects
* can exist per device object.
*/
int bridge_msg_create(struct msg_mgr **msg_man,
struct dev_object *hdev_obj,
msg_onexit msg_callback)
{
struct msg_mgr *msg_mgr_obj;
struct io_mgr *hio_mgr;
int status = 0;
if (!msg_man || !msg_callback || !hdev_obj)
return -EFAULT;
dev_get_io_mgr(hdev_obj, &hio_mgr);
if (!hio_mgr)
return -EFAULT;
*msg_man = NULL;
/* Allocate msg_ctrl manager object */
msg_mgr_obj = kzalloc(sizeof(struct msg_mgr), GFP_KERNEL);
if (!msg_mgr_obj)
return -ENOMEM;
msg_mgr_obj->on_exit = msg_callback;
msg_mgr_obj->iomgr = hio_mgr;
/* List of MSG_QUEUEs */
INIT_LIST_HEAD(&msg_mgr_obj->queue_list);
/*
* Queues of message frames for messages to the DSP. Message
* frames will only be added to the free queue when a
* msg_queue object is created.
*/
INIT_LIST_HEAD(&msg_mgr_obj->msg_free_list);
INIT_LIST_HEAD(&msg_mgr_obj->msg_used_list);
spin_lock_init(&msg_mgr_obj->msg_mgr_lock);
/*
* Create an event to be used by bridge_msg_put() in waiting
* for an available free frame from the message manager.
*/
msg_mgr_obj->sync_event =
kzalloc(sizeof(struct sync_object), GFP_KERNEL);
if (!msg_mgr_obj->sync_event) {
kfree(msg_mgr_obj);
return -ENOMEM;
}
sync_init_event(msg_mgr_obj->sync_event);
*msg_man = msg_mgr_obj;
return status;
}
/*
* ======== bridge_msg_create_queue ========
* Create a msg_queue for sending/receiving messages to/from a node
* on the DSP.
*/
int bridge_msg_create_queue(struct msg_mgr *hmsg_mgr, struct msg_queue **msgq,
u32 msgq_id, u32 max_msgs, void *arg)
{
u32 i;
u32 num_allocated = 0;
struct msg_queue *msg_q;
int status = 0;
if (!hmsg_mgr || msgq == NULL)
return -EFAULT;
*msgq = NULL;
/* Allocate msg_queue object */
msg_q = kzalloc(sizeof(struct msg_queue), GFP_KERNEL);
if (!msg_q)
return -ENOMEM;
msg_q->max_msgs = max_msgs;
msg_q->msg_mgr = hmsg_mgr;
msg_q->arg = arg; /* Node handle */
msg_q->msgq_id = msgq_id; /* Node env (not valid yet) */
/* Queues of Message frames for messages from the DSP */
INIT_LIST_HEAD(&msg_q->msg_free_list);
INIT_LIST_HEAD(&msg_q->msg_used_list);
/* Create event that will be signalled when a message from
* the DSP is available. */
msg_q->sync_event = kzalloc(sizeof(struct sync_object), GFP_KERNEL);
if (!msg_q->sync_event) {
status = -ENOMEM;
goto out_err;
}
sync_init_event(msg_q->sync_event);
/* Create a notification list for message ready notification. */
msg_q->ntfy_obj = kmalloc(sizeof(struct ntfy_object), GFP_KERNEL);
if (!msg_q->ntfy_obj) {
status = -ENOMEM;
goto out_err;
}
ntfy_init(msg_q->ntfy_obj);
/* Create events that will be used to synchronize cleanup
* when the object is deleted. sync_done will be set to
* unblock threads in MSG_Put() or MSG_Get(). sync_done_ack
* will be set by the unblocked thread to signal that it
* is unblocked and will no longer reference the object. */
msg_q->sync_done = kzalloc(sizeof(struct sync_object), GFP_KERNEL);
if (!msg_q->sync_done) {
status = -ENOMEM;
goto out_err;
}
sync_init_event(msg_q->sync_done);
msg_q->sync_done_ack = kzalloc(sizeof(struct sync_object), GFP_KERNEL);
if (!msg_q->sync_done_ack) {
status = -ENOMEM;
goto out_err;
}
sync_init_event(msg_q->sync_done_ack);
/* Enter critical section */
spin_lock_bh(&hmsg_mgr->msg_mgr_lock);
/* Initialize message frames and put in appropriate queues */
for (i = 0; i < max_msgs && !status; i++) {
status = add_new_msg(&hmsg_mgr->msg_free_list);
if (!status) {
num_allocated++;
status = add_new_msg(&msg_q->msg_free_list);
}
}
if (status) {
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
goto out_err;
}
list_add_tail(&msg_q->list_elem, &hmsg_mgr->queue_list);
*msgq = msg_q;
/* Signal that free frames are now available */
if (!list_empty(&hmsg_mgr->msg_free_list))
sync_set_event(hmsg_mgr->sync_event);
/* Exit critical section */
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
return 0;
out_err:
delete_msg_queue(msg_q, num_allocated);
return status;
}
/*
* ======== bridge_msg_delete ========
* Delete a msg_ctrl manager allocated in bridge_msg_create().
*/
void bridge_msg_delete(struct msg_mgr *hmsg_mgr)
{
delete_msg_mgr(hmsg_mgr);
}
/*
* ======== bridge_msg_delete_queue ========
* Delete a msg_ctrl queue allocated in bridge_msg_create_queue.
*/
void bridge_msg_delete_queue(struct msg_queue *msg_queue_obj)
{
struct msg_mgr *hmsg_mgr;
u32 io_msg_pend;
if (!msg_queue_obj || !msg_queue_obj->msg_mgr)
return;
hmsg_mgr = msg_queue_obj->msg_mgr;
msg_queue_obj->done = true;
/* Unblock all threads blocked in MSG_Get() or MSG_Put(). */
io_msg_pend = msg_queue_obj->io_msg_pend;
while (io_msg_pend) {
/* Unblock thread */
sync_set_event(msg_queue_obj->sync_done);
/* Wait for acknowledgement */
sync_wait_on_event(msg_queue_obj->sync_done_ack, SYNC_INFINITE);
io_msg_pend = msg_queue_obj->io_msg_pend;
}
/* Remove message queue from hmsg_mgr->queue_list */
spin_lock_bh(&hmsg_mgr->msg_mgr_lock);
list_del(&msg_queue_obj->list_elem);
/* Free the message queue object */
delete_msg_queue(msg_queue_obj, msg_queue_obj->max_msgs);
if (list_empty(&hmsg_mgr->msg_free_list))
sync_reset_event(hmsg_mgr->sync_event);
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
}
/*
* ======== bridge_msg_get ========
* Get a message from a msg_ctrl queue.
*/
int bridge_msg_get(struct msg_queue *msg_queue_obj,
struct dsp_msg *pmsg, u32 utimeout)
{
struct msg_frame *msg_frame_obj;
struct msg_mgr *hmsg_mgr;
struct sync_object *syncs[2];
u32 index;
int status = 0;
if (!msg_queue_obj || pmsg == NULL)
return -ENOMEM;
hmsg_mgr = msg_queue_obj->msg_mgr;
spin_lock_bh(&hmsg_mgr->msg_mgr_lock);
/* If a message is already there, get it */
if (!list_empty(&msg_queue_obj->msg_used_list)) {
msg_frame_obj = list_first_entry(&msg_queue_obj->msg_used_list,
struct msg_frame, list_elem);
list_del(&msg_frame_obj->list_elem);
*pmsg = msg_frame_obj->msg_data.msg;
list_add_tail(&msg_frame_obj->list_elem,
&msg_queue_obj->msg_free_list);
if (list_empty(&msg_queue_obj->msg_used_list))
sync_reset_event(msg_queue_obj->sync_event);
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
return 0;
}
if (msg_queue_obj->done) {
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
return -EPERM;
}
msg_queue_obj->io_msg_pend++;
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
/*
* Wait til message is available, timeout, or done. We don't
* have to schedule the DPC, since the DSP will send messages
* when they are available.
*/
syncs[0] = msg_queue_obj->sync_event;
syncs[1] = msg_queue_obj->sync_done;
status = sync_wait_on_multiple_events(syncs, 2, utimeout, &index);
spin_lock_bh(&hmsg_mgr->msg_mgr_lock);
if (msg_queue_obj->done) {
msg_queue_obj->io_msg_pend--;
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
/*
* Signal that we're not going to access msg_queue_obj
* anymore, so it can be deleted.
*/
sync_set_event(msg_queue_obj->sync_done_ack);
return -EPERM;
}
if (!status && !list_empty(&msg_queue_obj->msg_used_list)) {
/* Get msg from used list */
msg_frame_obj = list_first_entry(&msg_queue_obj->msg_used_list,
struct msg_frame, list_elem);
list_del(&msg_frame_obj->list_elem);
/* Copy message into pmsg and put frame on the free list */
*pmsg = msg_frame_obj->msg_data.msg;
list_add_tail(&msg_frame_obj->list_elem,
&msg_queue_obj->msg_free_list);
}
msg_queue_obj->io_msg_pend--;
/* Reset the event if there are still queued messages */
if (!list_empty(&msg_queue_obj->msg_used_list))
sync_set_event(msg_queue_obj->sync_event);
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
return status;
}
/*
* ======== bridge_msg_put ========
* Put a message onto a msg_ctrl queue.
*/
int bridge_msg_put(struct msg_queue *msg_queue_obj,
const struct dsp_msg *pmsg, u32 utimeout)
{
struct msg_frame *msg_frame_obj;
struct msg_mgr *hmsg_mgr;
struct sync_object *syncs[2];
u32 index;
int status;
if (!msg_queue_obj || !pmsg || !msg_queue_obj->msg_mgr)
return -EFAULT;
hmsg_mgr = msg_queue_obj->msg_mgr;
spin_lock_bh(&hmsg_mgr->msg_mgr_lock);
/* If a message frame is available, use it */
if (!list_empty(&hmsg_mgr->msg_free_list)) {
msg_frame_obj = list_first_entry(&hmsg_mgr->msg_free_list,
struct msg_frame, list_elem);
list_del(&msg_frame_obj->list_elem);
msg_frame_obj->msg_data.msg = *pmsg;
msg_frame_obj->msg_data.msgq_id =
msg_queue_obj->msgq_id;
list_add_tail(&msg_frame_obj->list_elem,
&hmsg_mgr->msg_used_list);
hmsg_mgr->msgs_pending++;
if (list_empty(&hmsg_mgr->msg_free_list))
sync_reset_event(hmsg_mgr->sync_event);
/* Release critical section before scheduling DPC */
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
/* Schedule a DPC, to do the actual data transfer: */
iosm_schedule(hmsg_mgr->iomgr);
return 0;
}
if (msg_queue_obj->done) {
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
return -EPERM;
}
msg_queue_obj->io_msg_pend++;
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
/* Wait til a free message frame is available, timeout, or done */
syncs[0] = hmsg_mgr->sync_event;
syncs[1] = msg_queue_obj->sync_done;
status = sync_wait_on_multiple_events(syncs, 2, utimeout, &index);
if (status)
return status;
/* Enter critical section */
spin_lock_bh(&hmsg_mgr->msg_mgr_lock);
if (msg_queue_obj->done) {
msg_queue_obj->io_msg_pend--;
/* Exit critical section */
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
/*
* Signal that we're not going to access msg_queue_obj
* anymore, so it can be deleted.
*/
sync_set_event(msg_queue_obj->sync_done_ack);
return -EPERM;
}
if (list_empty(&hmsg_mgr->msg_free_list)) {
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
return -EFAULT;
}
/* Get msg from free list */
msg_frame_obj = list_first_entry(&hmsg_mgr->msg_free_list,
struct msg_frame, list_elem);
/*
* Copy message into pmsg and put frame on the
* used list.
*/
list_del(&msg_frame_obj->list_elem);
msg_frame_obj->msg_data.msg = *pmsg;
msg_frame_obj->msg_data.msgq_id = msg_queue_obj->msgq_id;
list_add_tail(&msg_frame_obj->list_elem, &hmsg_mgr->msg_used_list);
hmsg_mgr->msgs_pending++;
/*
* Schedule a DPC, to do the actual
* data transfer.
*/
iosm_schedule(hmsg_mgr->iomgr);
msg_queue_obj->io_msg_pend--;
/* Reset event if there are still frames available */
if (!list_empty(&hmsg_mgr->msg_free_list))
sync_set_event(hmsg_mgr->sync_event);
/* Exit critical section */
spin_unlock_bh(&hmsg_mgr->msg_mgr_lock);
return 0;
}
/*
* ======== bridge_msg_register_notify ========
*/
int bridge_msg_register_notify(struct msg_queue *msg_queue_obj,
u32 event_mask, u32 notify_type,
struct dsp_notification *hnotification)
{
int status = 0;
if (!msg_queue_obj || !hnotification) {
status = -ENOMEM;
goto func_end;
}
if (!(event_mask == DSP_NODEMESSAGEREADY || event_mask == 0)) {
status = -EPERM;
goto func_end;
}
if (notify_type != DSP_SIGNALEVENT) {
status = -EBADR;
goto func_end;
}
if (event_mask)
status = ntfy_register(msg_queue_obj->ntfy_obj, hnotification,
event_mask, notify_type);
else
status = ntfy_unregister(msg_queue_obj->ntfy_obj,
hnotification);
if (status == -EINVAL) {
/* Not registered. Ok, since we couldn't have known. Node
* notifications are split between node state change handled
* by NODE, and message ready handled by msg_ctrl. */
status = 0;
}
func_end:
return status;
}
/*
* ======== bridge_msg_set_queue_id ========
*/
void bridge_msg_set_queue_id(struct msg_queue *msg_queue_obj, u32 msgq_id)
{
/*
* A message queue must be created when a node is allocated,
* so that node_register_notify() can be called before the node
* is created. Since we don't know the node environment until the
* node is created, we need this function to set msg_queue_obj->msgq_id
* to the node environment, after the node is created.
*/
if (msg_queue_obj)
msg_queue_obj->msgq_id = msgq_id;
}
/*
* ======== add_new_msg ========
* Must be called in message manager critical section.
*/
static int add_new_msg(struct list_head *msg_list)
{
struct msg_frame *pmsg;
pmsg = kzalloc(sizeof(struct msg_frame), GFP_ATOMIC);
if (!pmsg)
return -ENOMEM;
list_add_tail(&pmsg->list_elem, msg_list);
return 0;
}
/*
* ======== delete_msg_mgr ========
*/
static void delete_msg_mgr(struct msg_mgr *hmsg_mgr)
{
if (!hmsg_mgr)
return;
/* FIXME: free elements from queue_list? */
free_msg_list(&hmsg_mgr->msg_free_list);
free_msg_list(&hmsg_mgr->msg_used_list);
kfree(hmsg_mgr->sync_event);
kfree(hmsg_mgr);
}
/*
* ======== delete_msg_queue ========
*/
static void delete_msg_queue(struct msg_queue *msg_queue_obj, u32 num_to_dsp)
{
struct msg_mgr *hmsg_mgr;
struct msg_frame *pmsg, *tmp;
u32 i;
if (!msg_queue_obj || !msg_queue_obj->msg_mgr)
return;
hmsg_mgr = msg_queue_obj->msg_mgr;
/* Pull off num_to_dsp message frames from Msg manager and free */
i = 0;
list_for_each_entry_safe(pmsg, tmp, &hmsg_mgr->msg_free_list,
list_elem) {
list_del(&pmsg->list_elem);
kfree(pmsg);
if (i++ >= num_to_dsp)
break;
}
free_msg_list(&msg_queue_obj->msg_free_list);
free_msg_list(&msg_queue_obj->msg_used_list);
if (msg_queue_obj->ntfy_obj) {
ntfy_delete(msg_queue_obj->ntfy_obj);
kfree(msg_queue_obj->ntfy_obj);
}
kfree(msg_queue_obj->sync_event);
kfree(msg_queue_obj->sync_done);
kfree(msg_queue_obj->sync_done_ack);
kfree(msg_queue_obj);
}
/*
* ======== free_msg_list ========
*/
static void free_msg_list(struct list_head *msg_list)
{
struct msg_frame *pmsg, *tmp;
if (!msg_list)
return;
list_for_each_entry_safe(pmsg, tmp, msg_list, list_elem) {
list_del(&pmsg->list_elem);
kfree(pmsg);
}
}

121
drivers/staging/tidspbridge/core/sync.c
View File

@ -1,121 +0,0 @@
/*
* sync.c
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Synchronization services.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
/* ----------------------------------- Host OS */
#include <dspbridge/host_os.h>
/* ----------------------------------- This */
#include <dspbridge/sync.h>
#include <dspbridge/ntfy.h>
DEFINE_SPINLOCK(sync_lock);
/**
* sync_set_event() - set or signal and specified event
* @event: Event to be set..
*
* set the @event, if there is an thread waiting for the event
* it will be waken up, this function only wakes one thread.
*/
void sync_set_event(struct sync_object *event)
{
spin_lock_bh(&sync_lock);
complete(&event->comp);
if (event->multi_comp)
complete(event->multi_comp);
spin_unlock_bh(&sync_lock);
}
/**
* sync_wait_on_multiple_events() - waits for multiple events to be set.
* @events: Array of events to wait for them.
* @count: number of elements of the array.
* @timeout timeout on waiting for the evetns.
* @pu_index index of the event set.
*
* These functions will wait until any of the array element is set or until
* timeout. In case of success the function will return 0 and
* @pu_index will store the index of the array element set or in case
* of timeout the function will return -ETIME or in case of
* interrupting by a signal it will return -EPERM.
*/
int sync_wait_on_multiple_events(struct sync_object **events,
unsigned count, unsigned timeout,
unsigned *index)
{
unsigned i;
int status = -EPERM;
struct completion m_comp;
init_completion(&m_comp);
if (SYNC_INFINITE == timeout)
timeout = MAX_SCHEDULE_TIMEOUT;
spin_lock_bh(&sync_lock);
for (i = 0; i < count; i++) {
if (completion_done(&events[i]->comp)) {
reinit_completion(&events[i]->comp);
*index = i;
spin_unlock_bh(&sync_lock);
status = 0;
goto func_end;
}
}
for (i = 0; i < count; i++)
events[i]->multi_comp = &m_comp;
spin_unlock_bh(&sync_lock);
if (!wait_for_completion_interruptible_timeout(&m_comp,
msecs_to_jiffies(timeout)))
status = -ETIME;
spin_lock_bh(&sync_lock);
for (i = 0; i < count; i++) {
if (completion_done(&events[i]->comp)) {
reinit_completion(&events[i]->comp);
*index = i;
status = 0;
}
events[i]->multi_comp = NULL;
}
spin_unlock_bh(&sync_lock);
func_end:
return status;
}
/**
* dsp_notifier_event() - callback function to nofity events
* @this: pointer to itself struct notifier_block
* @event: event to be notified.
* @data: Currently not used.
*
*/
int dsp_notifier_event(struct notifier_block *this, unsigned long event,
void *data)
{
struct ntfy_event *ne = container_of(this, struct ntfy_event,
noti_block);
if (ne->event & event)
sync_set_event(&ne->sync_obj);
return NOTIFY_OK;
}

1815
drivers/staging/tidspbridge/core/tiomap3430.c
View File

File diff suppressed because it is too large Load Diff

556
drivers/staging/tidspbridge/core/tiomap3430_pwr.c
View File

@ -1,556 +0,0 @@
/*
* tiomap_pwr.c
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Implementation of DSP wake/sleep routines.
*
* Copyright (C) 2007-2008 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
/* ----------------------------------- Host OS */
#include <dspbridge/host_os.h>
#include <linux/platform_data/dsp-omap.h>
/* ----------------------------------- DSP/BIOS Bridge */
#include <dspbridge/dbdefs.h>
#include <dspbridge/drv.h>
#include <dspbridge/io_sm.h>
/* ----------------------------------- Platform Manager */
#include <dspbridge/brddefs.h>
#include <dspbridge/dev.h>
#include <dspbridge/io.h>
/* ------------------------------------ Hardware Abstraction Layer */
#include <hw_defs.h>
#include <hw_mmu.h>
#include <dspbridge/pwr.h>
/* ----------------------------------- Bridge Driver */
#include <dspbridge/dspdeh.h>
#include <dspbridge/wdt.h>
/* ----------------------------------- specific to this file */
#include "_tiomap.h"
#include "_tiomap_pwr.h"
#include <mach-omap2/prm-regbits-34xx.h>
#include <mach-omap2/cm-regbits-34xx.h>
#define PWRSTST_TIMEOUT 200
/*
* ======== handle_constraints_set ========
* Sets new DSP constraint
*/
int handle_constraints_set(struct bridge_dev_context *dev_context,
void *pargs)
{
#ifdef CONFIG_TIDSPBRIDGE_DVFS
u32 *constraint_val;
struct omap_dsp_platform_data *pdata =
omap_dspbridge_dev->dev.platform_data;
constraint_val = (u32 *) (pargs);
/* Read the target value requested by DSP */
dev_dbg(bridge, "OPP: %s opp requested = 0x%x\n", __func__,
(u32) *(constraint_val + 1));
/* Set the new opp value */
if (pdata->dsp_set_min_opp)
(*pdata->dsp_set_min_opp) ((u32) *(constraint_val + 1));
#endif /* #ifdef CONFIG_TIDSPBRIDGE_DVFS */
return 0;
}
/*
* ======== handle_hibernation_from_dsp ========
* Handle Hibernation requested from DSP
*/
int handle_hibernation_from_dsp(struct bridge_dev_context *dev_context)
{
int status = 0;
#ifdef CONFIG_PM
u16 timeout = PWRSTST_TIMEOUT / 10;
u32 pwr_state;
#ifdef CONFIG_TIDSPBRIDGE_DVFS
u32 opplevel;
struct io_mgr *hio_mgr;
#endif
struct omap_dsp_platform_data *pdata =
omap_dspbridge_dev->dev.platform_data;
pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
OMAP_POWERSTATEST_MASK;
/* Wait for DSP to move into OFF state */
while ((pwr_state != PWRDM_POWER_OFF) && --timeout) {
if (msleep_interruptible(10)) {
pr_err("Waiting for DSP OFF mode interrupted\n");
return -EPERM;
}
pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD,
OMAP2_PM_PWSTST) &
OMAP_POWERSTATEST_MASK;
}
if (timeout == 0) {
pr_err("%s: Timed out waiting for DSP off mode\n", __func__);
status = -ETIMEDOUT;
return status;
} else {
/* Save mailbox settings */
omap_mbox_save_ctx(dev_context->mbox);
/* Turn off DSP Peripheral clocks and DSP Load monitor timer */
status = dsp_clock_disable_all(dev_context->dsp_per_clks);
/* Disable wdt on hibernation. */
dsp_wdt_enable(false);
if (!status) {
/* Update the Bridger Driver state */
dev_context->brd_state = BRD_DSP_HIBERNATION;
#ifdef CONFIG_TIDSPBRIDGE_DVFS
status =
dev_get_io_mgr(dev_context->dev_obj, &hio_mgr);
if (!hio_mgr) {
status = DSP_EHANDLE;
return status;
}
io_sh_msetting(hio_mgr, SHM_GETOPP, &opplevel);
/*
* Set the OPP to low level before moving to OFF
* mode
*/
if (pdata->dsp_set_min_opp)
(*pdata->dsp_set_min_opp) (VDD1_OPP1);
status = 0;
#endif /* CONFIG_TIDSPBRIDGE_DVFS */
}
}
#endif
return status;
}
/*
* ======== sleep_dsp ========
* Put DSP in low power consuming state.
*/
int sleep_dsp(struct bridge_dev_context *dev_context, u32 dw_cmd,
void *pargs)
{
int status = 0;
#ifdef CONFIG_PM
#ifdef CONFIG_TIDSPBRIDGE_NTFY_PWRERR
struct deh_mgr *hdeh_mgr;
#endif /* CONFIG_TIDSPBRIDGE_NTFY_PWRERR */
u16 timeout = PWRSTST_TIMEOUT / 10;
u32 pwr_state, target_pwr_state;
struct omap_dsp_platform_data *pdata =
omap_dspbridge_dev->dev.platform_data;
/* Check if sleep code is valid */
if ((dw_cmd != PWR_DEEPSLEEP) && (dw_cmd != PWR_EMERGENCYDEEPSLEEP))
return -EINVAL;
switch (dev_context->brd_state) {
case BRD_RUNNING:
omap_mbox_save_ctx(dev_context->mbox);
if (dsp_test_sleepstate == PWRDM_POWER_OFF) {
sm_interrupt_dsp(dev_context, MBX_PM_DSPHIBERNATE);
dev_dbg(bridge, "PM: %s - sent hibernate cmd to DSP\n",
__func__);
target_pwr_state = PWRDM_POWER_OFF;
} else {
sm_interrupt_dsp(dev_context, MBX_PM_DSPRETENTION);
target_pwr_state = PWRDM_POWER_RET;
}
break;
case BRD_RETENTION:
omap_mbox_save_ctx(dev_context->mbox);
if (dsp_test_sleepstate == PWRDM_POWER_OFF) {
sm_interrupt_dsp(dev_context, MBX_PM_DSPHIBERNATE);
target_pwr_state = PWRDM_POWER_OFF;
} else
return 0;
break;
case BRD_HIBERNATION:
case BRD_DSP_HIBERNATION:
/* Already in Hibernation, so just return */
dev_dbg(bridge, "PM: %s - DSP already in hibernation\n",
__func__);
return 0;
case BRD_STOPPED:
dev_dbg(bridge, "PM: %s - Board in STOP state\n", __func__);
return 0;
default:
dev_dbg(bridge, "PM: %s - Bridge in Illegal state\n", __func__);
return -EPERM;
}
/* Get the PRCM DSP power domain status */
pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
OMAP_POWERSTATEST_MASK;
/* Wait for DSP to move into target power state */
while ((pwr_state != target_pwr_state) && --timeout) {
if (msleep_interruptible(10)) {
pr_err("Waiting for DSP to Suspend interrupted\n");
return -EPERM;
}
pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD,
OMAP2_PM_PWSTST) &
OMAP_POWERSTATEST_MASK;
}
if (!timeout) {
pr_err("%s: Timed out waiting for DSP off mode, state %x\n",
__func__, pwr_state);
#ifdef CONFIG_TIDSPBRIDGE_NTFY_PWRERR
dev_get_deh_mgr(dev_context->dev_obj, &hdeh_mgr);
bridge_deh_notify(hdeh_mgr, DSP_PWRERROR, 0);
#endif /* CONFIG_TIDSPBRIDGE_NTFY_PWRERR */
return -ETIMEDOUT;
} else {
/* Update the Bridger Driver state */
if (dsp_test_sleepstate == PWRDM_POWER_OFF)
dev_context->brd_state = BRD_HIBERNATION;
else
dev_context->brd_state = BRD_RETENTION;
/* Disable wdt on hibernation. */
dsp_wdt_enable(false);
/* Turn off DSP Peripheral clocks */
status = dsp_clock_disable_all(dev_context->dsp_per_clks);
if (status)
return status;
#ifdef CONFIG_TIDSPBRIDGE_DVFS
else if (target_pwr_state == PWRDM_POWER_OFF) {
/*
* Set the OPP to low level before moving to OFF mode
*/
if (pdata->dsp_set_min_opp)
(*pdata->dsp_set_min_opp) (VDD1_OPP1);
}
#endif /* CONFIG_TIDSPBRIDGE_DVFS */
}
#endif /* CONFIG_PM */
return status;
}
/*
* ======== wake_dsp ========
* Wake up DSP from sleep.
*/
int wake_dsp(struct bridge_dev_context *dev_context, void *pargs)
{
int status = 0;
#ifdef CONFIG_PM
/* Check the board state, if it is not 'SLEEP' then return */
if (dev_context->brd_state == BRD_RUNNING ||
dev_context->brd_state == BRD_STOPPED) {
/* The Device is in 'RET' or 'OFF' state and Bridge state is not
* 'SLEEP', this means state inconsistency, so return */
return 0;
}
/* Send a wakeup message to DSP */
sm_interrupt_dsp(dev_context, MBX_PM_DSPWAKEUP);
/* Set the device state to RUNNIG */
dev_context->brd_state = BRD_RUNNING;
#endif /* CONFIG_PM */
return status;
}
/*
* ======== dsp_peripheral_clk_ctrl ========
* Enable/Disable the DSP peripheral clocks as needed..
*/
int dsp_peripheral_clk_ctrl(struct bridge_dev_context *dev_context,
void *pargs)
{
u32 ext_clk = 0;
u32 ext_clk_id = 0;
u32 ext_clk_cmd = 0;
u32 clk_id_index = MBX_PM_MAX_RESOURCES;
u32 tmp_index;
u32 dsp_per_clks_before;
int status = 0;
dsp_per_clks_before = dev_context->dsp_per_clks;
ext_clk = (u32) *((u32 *) pargs);
ext_clk_id = ext_clk & MBX_PM_CLK_IDMASK;
/* process the power message -- TODO, keep it in a separate function */
for (tmp_index = 0; tmp_index < MBX_PM_MAX_RESOURCES; tmp_index++) {
if (ext_clk_id == bpwr_clkid[tmp_index]) {
clk_id_index = tmp_index;
break;
}
}
/* TODO -- Assert may be a too hard restriction here.. May be we should
* just return with failure when the CLK ID does not match */
if (clk_id_index == MBX_PM_MAX_RESOURCES) {
/* return with a more meaningfull error code */
return -EPERM;
}
ext_clk_cmd = (ext_clk >> MBX_PM_CLK_CMDSHIFT) & MBX_PM_CLK_CMDMASK;
switch (ext_clk_cmd) {
case BPWR_DISABLE_CLOCK:
status = dsp_clk_disable(bpwr_clks[clk_id_index].clk);
dsp_clk_wakeup_event_ctrl(bpwr_clks[clk_id_index].clk_id,
false);
if (!status) {
(dev_context->dsp_per_clks) &=
(~((u32) (1 << bpwr_clks[clk_id_index].clk)));
}
break;
case BPWR_ENABLE_CLOCK:
status = dsp_clk_enable(bpwr_clks[clk_id_index].clk);
dsp_clk_wakeup_event_ctrl(bpwr_clks[clk_id_index].clk_id, true);
if (!status)
(dev_context->dsp_per_clks) |=
(1 << bpwr_clks[clk_id_index].clk);
break;
default:
dev_dbg(bridge, "%s: Unsupported CMD\n", __func__);
/* unsupported cmd */
/* TODO -- provide support for AUTOIDLE Enable/Disable
* commands */
}
return status;
}
/*
* ========pre_scale_dsp========
* Sends prescale notification to DSP
*
*/
int pre_scale_dsp(struct bridge_dev_context *dev_context, void *pargs)
{
#ifdef CONFIG_TIDSPBRIDGE_DVFS
u32 level;
u32 voltage_domain;
voltage_domain = *((u32 *) pargs);
level = *((u32 *) pargs + 1);
dev_dbg(bridge, "OPP: %s voltage_domain = %x, level = 0x%x\n",
__func__, voltage_domain, level);
if ((dev_context->brd_state == BRD_HIBERNATION) ||
(dev_context->brd_state == BRD_RETENTION) ||
(dev_context->brd_state == BRD_DSP_HIBERNATION)) {
dev_dbg(bridge, "OPP: %s IVA in sleep. No message to DSP\n");
return 0;
} else if (dev_context->brd_state == BRD_RUNNING) {
/* Send a prenotification to DSP */
dev_dbg(bridge, "OPP: %s sent notification to DSP\n", __func__);
sm_interrupt_dsp(dev_context, MBX_PM_SETPOINT_PRENOTIFY);
return 0;
} else {
return -EPERM;
}
#endif /* #ifdef CONFIG_TIDSPBRIDGE_DVFS */
return 0;
}
/*
* ========post_scale_dsp========
* Sends postscale notification to DSP
*
*/
int post_scale_dsp(struct bridge_dev_context *dev_context,
void *pargs)
{
int status = 0;
#ifdef CONFIG_TIDSPBRIDGE_DVFS
u32 level;
u32 voltage_domain;
struct io_mgr *hio_mgr;
status = dev_get_io_mgr(dev_context->dev_obj, &hio_mgr);
if (!hio_mgr)
return -EFAULT;
voltage_domain = *((u32 *) pargs);
level = *((u32 *) pargs + 1);
dev_dbg(bridge, "OPP: %s voltage_domain = %x, level = 0x%x\n",
__func__, voltage_domain, level);
if ((dev_context->brd_state == BRD_HIBERNATION) ||
(dev_context->brd_state == BRD_RETENTION) ||
(dev_context->brd_state == BRD_DSP_HIBERNATION)) {
/* Update the OPP value in shared memory */
io_sh_msetting(hio_mgr, SHM_CURROPP, &level);
dev_dbg(bridge, "OPP: %s IVA in sleep. Wrote to shm\n",
__func__);
} else if (dev_context->brd_state == BRD_RUNNING) {
/* Update the OPP value in shared memory */
io_sh_msetting(hio_mgr, SHM_CURROPP, &level);
/* Send a post notification to DSP */
sm_interrupt_dsp(dev_context, MBX_PM_SETPOINT_POSTNOTIFY);
dev_dbg(bridge,
"OPP: %s wrote to shm. Sent post notification to DSP\n",
__func__);
} else {
status = -EPERM;
}
#endif /* #ifdef CONFIG_TIDSPBRIDGE_DVFS */
return status;
}
void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
{
struct cfg_hostres *resources;
int status = 0;
u32 iva2_grpsel;
u32 mpu_grpsel;
struct dev_object *hdev_object = NULL;
struct bridge_dev_context *bridge_context = NULL;
hdev_object = (struct dev_object *)drv_get_first_dev_object();
if (!hdev_object)
return;
status = dev_get_bridge_context(hdev_object, &bridge_context);
if (!bridge_context)
return;
resources = bridge_context->resources;
if (!resources)
return;
switch (clock_id) {
case BPWR_GP_TIMER5:
iva2_grpsel = readl(resources->per_pm_base + 0xA8);
mpu_grpsel = readl(resources->per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_GPT5_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_GPT5_MASK;
} else {
mpu_grpsel |= OMAP3430_GRPSEL_GPT5_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_GPT5_MASK;
}
writel(iva2_grpsel, resources->per_pm_base + 0xA8);
writel(mpu_grpsel, resources->per_pm_base + 0xA4);
break;
case BPWR_GP_TIMER6:
iva2_grpsel = readl(resources->per_pm_base + 0xA8);
mpu_grpsel = readl(resources->per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_GPT6_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_GPT6_MASK;
} else {
mpu_grpsel |= OMAP3430_GRPSEL_GPT6_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_GPT6_MASK;
}
writel(iva2_grpsel, resources->per_pm_base + 0xA8);
writel(mpu_grpsel, resources->per_pm_base + 0xA4);
break;
case BPWR_GP_TIMER7:
iva2_grpsel = readl(resources->per_pm_base + 0xA8);
mpu_grpsel = readl(resources->per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_GPT7_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_GPT7_MASK;
} else {
mpu_grpsel |= OMAP3430_GRPSEL_GPT7_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_GPT7_MASK;
}
writel(iva2_grpsel, resources->per_pm_base + 0xA8);
writel(mpu_grpsel, resources->per_pm_base + 0xA4);
break;
case BPWR_GP_TIMER8:
iva2_grpsel = readl(resources->per_pm_base + 0xA8);
mpu_grpsel = readl(resources->per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_GPT8_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_GPT8_MASK;
} else {
mpu_grpsel |= OMAP3430_GRPSEL_GPT8_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_GPT8_MASK;
}
writel(iva2_grpsel, resources->per_pm_base + 0xA8);
writel(mpu_grpsel, resources->per_pm_base + 0xA4);
break;
case BPWR_MCBSP1:
iva2_grpsel = readl(resources->core_pm_base + 0xA8);
mpu_grpsel = readl(resources->core_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK;
} else {
mpu_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK;
}
writel(iva2_grpsel, resources->core_pm_base + 0xA8);
writel(mpu_grpsel, resources->core_pm_base + 0xA4);
break;
case BPWR_MCBSP2:
iva2_grpsel = readl(resources->per_pm_base + 0xA8);
mpu_grpsel = readl(resources->per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_MCBSP2_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP2_MASK;
} else {
mpu_grpsel |= OMAP3430_GRPSEL_MCBSP2_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP2_MASK;
}
writel(iva2_grpsel, resources->per_pm_base + 0xA8);
writel(mpu_grpsel, resources->per_pm_base + 0xA4);
break;
case BPWR_MCBSP3:
iva2_grpsel = readl(resources->per_pm_base + 0xA8);
mpu_grpsel = readl(resources->per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_MCBSP3_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP3_MASK;
} else {
mpu_grpsel |= OMAP3430_GRPSEL_MCBSP3_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP3_MASK;
}
writel(iva2_grpsel, resources->per_pm_base + 0xA8);
writel(mpu_grpsel, resources->per_pm_base + 0xA4);
break;
case BPWR_MCBSP4:
iva2_grpsel = readl(resources->per_pm_base + 0xA8);
mpu_grpsel = readl(resources->per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_MCBSP4_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP4_MASK;
} else {
mpu_grpsel |= OMAP3430_GRPSEL_MCBSP4_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP4_MASK;
}
writel(iva2_grpsel, resources->per_pm_base + 0xA8);
writel(mpu_grpsel, resources->per_pm_base + 0xA4);
break;
case BPWR_MCBSP5:
iva2_grpsel = readl(resources->per_pm_base + 0xA8);
mpu_grpsel = readl(resources->per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_MCBSP5_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP5_MASK;
} else {
mpu_grpsel |= OMAP3430_GRPSEL_MCBSP5_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP5_MASK;
}
writel(iva2_grpsel, resources->per_pm_base + 0xA8);
writel(mpu_grpsel, resources->per_pm_base + 0xA4);
break;
}
}

440
drivers/staging/tidspbridge/core/tiomap_io.c
View File

@ -1,440 +0,0 @@
/*
* tiomap_io.c
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Implementation for the io read/write routines.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#include <linux/platform_data/dsp-omap.h>
/* ----------------------------------- DSP/BIOS Bridge */
#include <dspbridge/dbdefs.h>
/* ----------------------------------- Platform Manager */
#include <dspbridge/dev.h>
#include <dspbridge/drv.h>
/* ----------------------------------- OS Adaptation Layer */
#include <dspbridge/wdt.h>
/* ----------------------------------- specific to this file */
#include "_tiomap.h"
#include "_tiomap_pwr.h"
#include "tiomap_io.h"
static u32 ul_ext_base;
static u32 ul_ext_end;
static u32 shm0_end;
static u32 ul_dyn_ext_base;
static u32 ul_trace_sec_beg;
static u32 ul_trace_sec_end;
static u32 ul_shm_base_virt;
bool symbols_reloaded = true;
/*
* ======== read_ext_dsp_data ========
* Copies DSP external memory buffers to the host side buffers.
*/
int read_ext_dsp_data(struct bridge_dev_context *dev_ctxt,
u8 *host_buff, u32 dsp_addr,
u32 ul_num_bytes, u32 mem_type)
{
int status = 0;
struct bridge_dev_context *dev_context = dev_ctxt;
u32 offset;
u32 ul_tlb_base_virt = 0;
u32 ul_shm_offset_virt = 0;
u32 dw_ext_prog_virt_mem;
u32 dw_base_addr = dev_context->dsp_ext_base_addr;
bool trace_read = false;
if (!ul_shm_base_virt) {
status = dev_get_symbol(dev_context->dev_obj,
SHMBASENAME, &ul_shm_base_virt);
}
/* Check if it is a read of Trace section */
if (!status && !ul_trace_sec_beg) {
status = dev_get_symbol(dev_context->dev_obj,
DSP_TRACESEC_BEG, &ul_trace_sec_beg);
}
if (!status && !ul_trace_sec_end) {
status = dev_get_symbol(dev_context->dev_obj,
DSP_TRACESEC_END, &ul_trace_sec_end);
}
if (!status) {
if ((dsp_addr <= ul_trace_sec_end) &&
(dsp_addr >= ul_trace_sec_beg))
trace_read = true;
}
/* If reading from TRACE, force remap/unmap */
if (trace_read && dw_base_addr) {
dw_base_addr = 0;
dev_context->dsp_ext_base_addr = 0;
}
if (!dw_base_addr) {
/* Initialize ul_ext_base and ul_ext_end */
ul_ext_base = 0;
ul_ext_end = 0;
/* Get DYNEXT_BEG, EXT_BEG and EXT_END. */
if (!status && !ul_dyn_ext_base) {
status = dev_get_symbol(dev_context->dev_obj,
DYNEXTBASE, &ul_dyn_ext_base);
}
if (!status) {
status = dev_get_symbol(dev_context->dev_obj,
EXTBASE, &ul_ext_base);
}
if (!status) {
status = dev_get_symbol(dev_context->dev_obj,
EXTEND, &ul_ext_end);
}
/* Trace buffer is right after the shm SEG0,
* so set the base address to SHMBASE */
if (trace_read) {
ul_ext_base = ul_shm_base_virt;
ul_ext_end = ul_trace_sec_end;
}
if (ul_ext_end < ul_ext_base)
status = -EPERM;
if (!status) {
ul_tlb_base_virt =
dev_context->atlb_entry[0].dsp_va * DSPWORDSIZE;
dw_ext_prog_virt_mem =
dev_context->atlb_entry[0].gpp_va;
if (!trace_read) {
ul_shm_offset_virt =
ul_shm_base_virt - ul_tlb_base_virt;
ul_shm_offset_virt +=
PG_ALIGN_HIGH(ul_ext_end - ul_dyn_ext_base +
1, HW_PAGE_SIZE64KB);
dw_ext_prog_virt_mem -= ul_shm_offset_virt;
dw_ext_prog_virt_mem +=
(ul_ext_base - ul_dyn_ext_base);
dev_context->dsp_ext_base_addr =
dw_ext_prog_virt_mem;
/*
* This dsp_ext_base_addr will get cleared
* only when the board is stopped.
*/
if (!dev_context->dsp_ext_base_addr)
status = -EPERM;
}
dw_base_addr = dw_ext_prog_virt_mem;
}
}
if (!dw_base_addr || !ul_ext_base || !ul_ext_end)
status = -EPERM;
offset = dsp_addr - ul_ext_base;
if (!status)
memcpy(host_buff, (u8 *) dw_base_addr + offset, ul_num_bytes);
return status;
}
/*
* ======== write_dsp_data ========
* purpose:
* Copies buffers to the DSP internal/external memory.
*/
int write_dsp_data(struct bridge_dev_context *dev_context,
u8 *host_buff, u32 dsp_addr, u32 ul_num_bytes,
u32 mem_type)
{
u32 offset;
u32 dw_base_addr = dev_context->dsp_base_addr;
struct cfg_hostres *resources = dev_context->resources;
int status = 0;
u32 base1, base2, base3;
base1 = OMAP_DSP_MEM1_SIZE;
base2 = OMAP_DSP_MEM2_BASE - OMAP_DSP_MEM1_BASE;
base3 = OMAP_DSP_MEM3_BASE - OMAP_DSP_MEM1_BASE;
if (!resources)
return -EPERM;
offset = dsp_addr - dev_context->dsp_start_add;
if (offset < base1) {
dw_base_addr = MEM_LINEAR_ADDRESS(resources->mem_base[2],
resources->mem_length[2]);
} else if (offset > base1 && offset < base2 + OMAP_DSP_MEM2_SIZE) {
dw_base_addr = MEM_LINEAR_ADDRESS(resources->mem_base[3],
resources->mem_length[3]);
offset = offset - base2;
} else if (offset >= base2 + OMAP_DSP_MEM2_SIZE &&
offset < base3 + OMAP_DSP_MEM3_SIZE) {
dw_base_addr = MEM_LINEAR_ADDRESS(resources->mem_base[4],
resources->mem_length[4]);
offset = offset - base3;
} else {
return -EPERM;
}
if (ul_num_bytes)
memcpy((u8 *) (dw_base_addr + offset), host_buff, ul_num_bytes);
else
*((u32 *) host_buff) = dw_base_addr + offset;
return status;
}
/*
* ======== write_ext_dsp_data ========
* purpose:
* Copies buffers to the external memory.
*
*/
int write_ext_dsp_data(struct bridge_dev_context *dev_context,
u8 *host_buff, u32 dsp_addr,
u32 ul_num_bytes, u32 mem_type,
bool dynamic_load)
{
u32 dw_base_addr = dev_context->dsp_ext_base_addr;
u32 dw_offset = 0;
u8 temp_byte1, temp_byte2;
u8 remain_byte[4];
s32 i;
int ret = 0;
u32 dw_ext_prog_virt_mem;
u32 ul_tlb_base_virt = 0;
u32 ul_shm_offset_virt = 0;
struct cfg_hostres *host_res = dev_context->resources;
bool trace_load = false;
temp_byte1 = 0x0;
temp_byte2 = 0x0;
if (symbols_reloaded) {
/* Check if it is a load to Trace section */
ret = dev_get_symbol(dev_context->dev_obj,
DSP_TRACESEC_BEG, &ul_trace_sec_beg);
if (!ret)
ret = dev_get_symbol(dev_context->dev_obj,
DSP_TRACESEC_END,
&ul_trace_sec_end);
}
if (!ret) {
if ((dsp_addr <= ul_trace_sec_end) &&
(dsp_addr >= ul_trace_sec_beg))
trace_load = true;
}
/* If dynamic, force remap/unmap */
if ((dynamic_load || trace_load) && dw_base_addr) {
dw_base_addr = 0;
MEM_UNMAP_LINEAR_ADDRESS((void *)
dev_context->dsp_ext_base_addr);
dev_context->dsp_ext_base_addr = 0x0;
}
if (!dw_base_addr) {
if (symbols_reloaded)
/* Get SHM_BEG EXT_BEG and EXT_END. */
ret = dev_get_symbol(dev_context->dev_obj,
SHMBASENAME, &ul_shm_base_virt);
if (dynamic_load) {
if (!ret) {
if (symbols_reloaded)
ret =
dev_get_symbol
(dev_context->dev_obj, DYNEXTBASE,
&ul_ext_base);
}
if (!ret) {
/* DR OMAPS00013235 : DLModules array may be
* in EXTMEM. It is expected that DYNEXTMEM and
* EXTMEM are contiguous, so checking for the
* upper bound at EXTEND should be Ok. */
if (symbols_reloaded)
ret =
dev_get_symbol
(dev_context->dev_obj, EXTEND,
&ul_ext_end);
}
} else {
if (symbols_reloaded) {
if (!ret)
ret =
dev_get_symbol
(dev_context->dev_obj, EXTBASE,
&ul_ext_base);
if (!ret)
ret =
dev_get_symbol
(dev_context->dev_obj, EXTEND,
&ul_ext_end);
}
}
/* Trace buffer it right after the shm SEG0, so set the
* base address to SHMBASE */
if (trace_load)
ul_ext_base = ul_shm_base_virt;
if (ul_ext_end < ul_ext_base)
ret = -EPERM;
if (!ret) {
ul_tlb_base_virt =
dev_context->atlb_entry[0].dsp_va * DSPWORDSIZE;
if (symbols_reloaded) {
ret = dev_get_symbol
(dev_context->dev_obj,
DSP_TRACESEC_END, &shm0_end);
if (!ret) {
ret =
dev_get_symbol
(dev_context->dev_obj, DYNEXTBASE,
&ul_dyn_ext_base);
}
}
ul_shm_offset_virt =
ul_shm_base_virt - ul_tlb_base_virt;
if (trace_load) {
dw_ext_prog_virt_mem =
dev_context->atlb_entry[0].gpp_va;
} else {
dw_ext_prog_virt_mem = host_res->mem_base[1];
dw_ext_prog_virt_mem +=
(ul_ext_base - ul_dyn_ext_base);
}
dev_context->dsp_ext_base_addr =
(u32) MEM_LINEAR_ADDRESS((void *)
dw_ext_prog_virt_mem,
ul_ext_end - ul_ext_base);
dw_base_addr += dev_context->dsp_ext_base_addr;
/* This dsp_ext_base_addr will get cleared only when
* the board is stopped. */
if (!dev_context->dsp_ext_base_addr)
ret = -EPERM;
}
}
if (!dw_base_addr || !ul_ext_base || !ul_ext_end)
ret = -EPERM;
if (!ret) {
for (i = 0; i < 4; i++)
remain_byte[i] = 0x0;
dw_offset = dsp_addr - ul_ext_base;
/* Also make sure the dsp_addr is < ul_ext_end */
if (dsp_addr > ul_ext_end || dw_offset > dsp_addr)
ret = -EPERM;
}
if (!ret) {
if (ul_num_bytes)
memcpy((u8 *) dw_base_addr + dw_offset, host_buff,
ul_num_bytes);
else
*((u32 *) host_buff) = dw_base_addr + dw_offset;
}
/* Unmap here to force remap for other Ext loads */
if ((dynamic_load || trace_load) && dev_context->dsp_ext_base_addr) {
MEM_UNMAP_LINEAR_ADDRESS((void *)
dev_context->dsp_ext_base_addr);
dev_context->dsp_ext_base_addr = 0x0;
}
symbols_reloaded = false;
return ret;
}
int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val)
{
#ifdef CONFIG_TIDSPBRIDGE_DVFS
u32 opplevel = 0;
#endif
struct omap_dsp_platform_data *pdata =
omap_dspbridge_dev->dev.platform_data;
struct cfg_hostres *resources = dev_context->resources;
int status = 0;
u32 temp;
if (!dev_context->mbox)
return 0;
if (!resources)
return -EPERM;
if (dev_context->brd_state == BRD_DSP_HIBERNATION ||
dev_context->brd_state == BRD_HIBERNATION) {
#ifdef CONFIG_TIDSPBRIDGE_DVFS
if (pdata->dsp_get_opp)
opplevel = (*pdata->dsp_get_opp) ();
if (opplevel == VDD1_OPP1) {
if (pdata->dsp_set_min_opp)
(*pdata->dsp_set_min_opp) (VDD1_OPP2);
}
#endif
/* Restart the peripheral clocks */
dsp_clock_enable_all(dev_context->dsp_per_clks);
dsp_wdt_enable(true);
/*
* 2:0 AUTO_IVA2_DPLL - Enabling IVA2 DPLL auto control
* in CM_AUTOIDLE_PLL_IVA2 register
*/
(*pdata->dsp_cm_write)(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL);
/*
* 7:4 IVA2_DPLL_FREQSEL - IVA2 internal frq set to
* 0.75 MHz - 1.0 MHz
* 2:0 EN_IVA2_DPLL - Enable IVA2 DPLL in lock mode
*/
(*pdata->dsp_cm_rmw_bits)(OMAP3430_IVA2_DPLL_FREQSEL_MASK |
OMAP3430_EN_IVA2_DPLL_MASK,
0x3 << OMAP3430_IVA2_DPLL_FREQSEL_SHIFT |
0x7 << OMAP3430_EN_IVA2_DPLL_SHIFT,
OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
/* Restore mailbox settings */
omap_mbox_restore_ctx(dev_context->mbox);
/* Access MMU SYS CONFIG register to generate a short wakeup */
temp = readl(resources->dmmu_base + 0x10);
dev_context->brd_state = BRD_RUNNING;
} else if (dev_context->brd_state == BRD_RETENTION) {
/* Restart the peripheral clocks */
dsp_clock_enable_all(dev_context->dsp_per_clks);
}
status = omap_mbox_msg_send(dev_context->mbox, mb_val);
if (status) {
pr_err("omap_mbox_msg_send Fail and status = %d\n", status);
status = -EPERM;
}
return 0;
}

104
drivers/staging/tidspbridge/core/tiomap_io.h
View File

@ -1,104 +0,0 @@
/*
* tiomap_io.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Definitions, types and function prototypes for the io (r/w external mem).
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef _TIOMAP_IO_
#define _TIOMAP_IO_
/*
* Symbol that defines beginning of shared memory.
* For OMAP (Helen) this is the DSP Virtual base address of SDRAM.
* This will be used to program DSP MMU to map DSP Virt to GPP phys.
* (see dspMmuTlbEntry()).
*/
#define SHMBASENAME "SHM_BEG"
#define EXTBASE "EXT_BEG"
#define EXTEND "_EXT_END"
#define DYNEXTBASE "_DYNEXT_BEG"
#define DYNEXTEND "_DYNEXT_END"
#define IVAEXTMEMBASE "_IVAEXTMEM_BEG"
#define IVAEXTMEMEND "_IVAEXTMEM_END"
#define DSP_TRACESEC_BEG "_BRIDGE_TRACE_BEG"
#define DSP_TRACESEC_END "_BRIDGE_TRACE_END"
#define SYS_PUTCBEG "_SYS_PUTCBEG"
#define SYS_PUTCEND "_SYS_PUTCEND"
#define BRIDGE_SYS_PUTC_CURRENT "_BRIDGE_SYS_PUTC_current"
#define WORDSWAP_ENABLE 0x3 /* Enable word swap */
/*
* ======== read_ext_dsp_data ========
* Reads it from DSP External memory. The external memory for the DSP
* is configured by the combination of DSP MMU and shm Memory manager in the CDB
*/
extern int read_ext_dsp_data(struct bridge_dev_context *dev_ctxt,
u8 *host_buff, u32 dsp_addr,
u32 ul_num_bytes, u32 mem_type);
/*
* ======== write_dsp_data ========
*/
extern int write_dsp_data(struct bridge_dev_context *dev_context,
u8 *host_buff, u32 dsp_addr,
u32 ul_num_bytes, u32 mem_type);
/*
* ======== write_ext_dsp_data ========
* Writes to the DSP External memory for external program.
* The ext mem for progra is configured by the combination of DSP MMU and
* shm Memory manager in the CDB
*/
extern int write_ext_dsp_data(struct bridge_dev_context *dev_context,
u8 *host_buff, u32 dsp_addr,
u32 ul_num_bytes, u32 mem_type,
bool dynamic_load);
/*
* ======== write_ext32_bit_dsp_data ========
* Writes 32 bit data to the external memory
*/
extern inline void write_ext32_bit_dsp_data(const
struct bridge_dev_context *dev_context,
u32 dsp_addr, u32 val)
{
*(u32 *) dsp_addr = ((dev_context->tc_word_swap_on) ? (((val << 16) &
0xFFFF0000) |
((val >> 16) &
0x0000FFFF)) :
val);
}
/*
* ======== read_ext32_bit_dsp_data ========
* Reads 32 bit data from the external memory
*/
extern inline u32 read_ext32_bit_dsp_data(const struct bridge_dev_context
*dev_context, u32 dsp_addr)
{
u32 ret;
ret = *(u32 *) dsp_addr;
ret = ((dev_context->tc_word_swap_on) ? (((ret << 16)
& 0xFFFF0000) | ((ret >> 16) &
0x0000FFFF))
: ret);
return ret;
}
#endif /* _TIOMAP_IO_ */

272
drivers/staging/tidspbridge/core/ue_deh.c
View File

@ -1,272 +0,0 @@
/*
* ue_deh.c
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Implements upper edge DSP exception handling (DEH) functions.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
* Copyright (C) 2010 Felipe Contreras
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <dspbridge/dbdefs.h>
#include <dspbridge/dspdeh.h>
#include <dspbridge/dev.h>
#include "_tiomap.h"
#include "_deh.h"
#include <dspbridge/io_sm.h>
#include <dspbridge/drv.h>
#include <dspbridge/wdt.h>
static u32 fault_addr;
static void mmu_fault_dpc(unsigned long data)
{
struct deh_mgr *deh = (void *)data;
if (!deh)
return;
bridge_deh_notify(deh, DSP_MMUFAULT, 0);
}
static irqreturn_t mmu_fault_isr(int irq, void *data)
{
struct deh_mgr *deh = data;
struct cfg_hostres *resources;
u32 event;
if (!deh)
return IRQ_HANDLED;
resources = deh->bridge_context->resources;
if (!resources) {
dev_dbg(bridge, "%s: Failed to get Host Resources\n",
__func__);
return IRQ_HANDLED;
}
hw_mmu_event_status(resources->dmmu_base, &event);
if (event == HW_MMU_TRANSLATION_FAULT) {
hw_mmu_fault_addr_read(resources->dmmu_base, &fault_addr);
dev_dbg(bridge, "%s: event=0x%x, fault_addr=0x%x\n", __func__,
event, fault_addr);
/*
* Schedule a DPC directly. In the future, it may be
* necessary to check if DSP MMU fault is intended for
* Bridge.
*/
tasklet_schedule(&deh->dpc_tasklet);
/* Disable the MMU events, else once we clear it will
* start to raise INTs again */
hw_mmu_event_disable(resources->dmmu_base,
HW_MMU_TRANSLATION_FAULT);
} else {
hw_mmu_event_disable(resources->dmmu_base,
HW_MMU_ALL_INTERRUPTS);
}
return IRQ_HANDLED;
}
int bridge_deh_create(struct deh_mgr **ret_deh,
struct dev_object *hdev_obj)
{
int status;
struct deh_mgr *deh;
struct bridge_dev_context *hbridge_context = NULL;
/* Message manager will be created when a file is loaded, since
* size of message buffer in shared memory is configurable in
* the base image. */
/* Get Bridge context info. */
dev_get_bridge_context(hdev_obj, &hbridge_context);
/* Allocate IO manager object: */
deh = kzalloc(sizeof(*deh), GFP_KERNEL);
if (!deh) {
status = -ENOMEM;
goto err;
}
/* Create an NTFY object to manage notifications */
deh->ntfy_obj = kmalloc(sizeof(struct ntfy_object), GFP_KERNEL);
if (!deh->ntfy_obj) {
status = -ENOMEM;
goto err;
}
ntfy_init(deh->ntfy_obj);
/* Create a MMUfault DPC */
tasklet_init(&deh->dpc_tasklet, mmu_fault_dpc, (u32) deh);
/* Fill in context structure */
deh->bridge_context = hbridge_context;
/* Install ISR function for DSP MMU fault */
status = request_irq(INT_DSP_MMU_IRQ, mmu_fault_isr, 0,
"DspBridge\tiommu fault", deh);
if (status < 0)
goto err;
*ret_deh = deh;
return 0;
err:
bridge_deh_destroy(deh);
*ret_deh = NULL;
return status;
}
int bridge_deh_destroy(struct deh_mgr *deh)
{
if (!deh)
return -EFAULT;
/* If notification object exists, delete it */
if (deh->ntfy_obj) {
ntfy_delete(deh->ntfy_obj);
kfree(deh->ntfy_obj);
}
/* Disable DSP MMU fault */
free_irq(INT_DSP_MMU_IRQ, deh);
/* Free DPC object */
tasklet_kill(&deh->dpc_tasklet);
/* Deallocate the DEH manager object */
kfree(deh);
return 0;
}
int bridge_deh_register_notify(struct deh_mgr *deh, u32 event_mask,
u32 notify_type,
struct dsp_notification *hnotification)
{
if (!deh)
return -EFAULT;
if (event_mask)
return ntfy_register(deh->ntfy_obj, hnotification,
event_mask, notify_type);
else
return ntfy_unregister(deh->ntfy_obj, hnotification);
}
#ifdef CONFIG_TIDSPBRIDGE_BACKTRACE
static void mmu_fault_print_stack(struct bridge_dev_context *dev_context)
{
struct cfg_hostres *resources;
struct hw_mmu_map_attrs_t map_attrs = {
.endianism = HW_LITTLE_ENDIAN,
.element_size = HW_ELEM_SIZE16BIT,
.mixed_size = HW_MMU_CPUES,
};
void *dummy_va_addr;
resources = dev_context->resources;
dummy_va_addr = (void *)__get_free_page(GFP_ATOMIC);
/*
* Before acking the MMU fault, let's make sure MMU can only
* access entry #0. Then add a new entry so that the DSP OS
* can continue in order to dump the stack.
*/
hw_mmu_twl_disable(resources->dmmu_base);
hw_mmu_tlb_flush_all(resources->dmmu_base);
hw_mmu_tlb_add(resources->dmmu_base,
virt_to_phys(dummy_va_addr), fault_addr,
HW_PAGE_SIZE4KB, 1,
&map_attrs, HW_SET, HW_SET);
dsp_clk_enable(DSP_CLK_GPT8);
dsp_gpt_wait_overflow(DSP_CLK_GPT8, 0xfffffffe);
/* Clear MMU interrupt */
hw_mmu_event_ack(resources->dmmu_base,
HW_MMU_TRANSLATION_FAULT);
dump_dsp_stack(dev_context);
dsp_clk_disable(DSP_CLK_GPT8);
hw_mmu_disable(resources->dmmu_base);
free_page((unsigned long)dummy_va_addr);
}
#endif
static inline const char *event_to_string(int event)
{
switch (event) {
case DSP_SYSERROR: return "DSP_SYSERROR"; break;
case DSP_MMUFAULT: return "DSP_MMUFAULT"; break;
case DSP_PWRERROR: return "DSP_PWRERROR"; break;
case DSP_WDTOVERFLOW: return "DSP_WDTOVERFLOW"; break;
default: return "unknown event"; break;
}
}
void bridge_deh_notify(struct deh_mgr *deh, int event, int info)
{
struct bridge_dev_context *dev_context;
const char *str = event_to_string(event);
if (!deh)
return;
dev_dbg(bridge, "%s: device exception", __func__);
dev_context = deh->bridge_context;
switch (event) {
case DSP_SYSERROR:
dev_err(bridge, "%s: %s, info=0x%x", __func__,
str, info);
#ifdef CONFIG_TIDSPBRIDGE_BACKTRACE
dump_dl_modules(dev_context);
dump_dsp_stack(dev_context);
#endif
break;
case DSP_MMUFAULT:
dev_err(bridge, "%s: %s, addr=0x%x", __func__,
str, fault_addr);
#ifdef CONFIG_TIDSPBRIDGE_BACKTRACE
print_dsp_trace_buffer(dev_context);
dump_dl_modules(dev_context);
mmu_fault_print_stack(dev_context);
#endif
break;
default:
dev_err(bridge, "%s: %s", __func__, str);
break;
}
/* Filter subsequent notifications when an error occurs */
if (dev_context->brd_state != BRD_ERROR) {
ntfy_notify(deh->ntfy_obj, event);
#ifdef CONFIG_TIDSPBRIDGE_RECOVERY
bridge_recover_schedule();
#endif
}
/* Set the Board state as ERROR */
dev_context->brd_state = BRD_ERROR;
/* Disable all the clocks that were enabled by DSP */
dsp_clock_disable_all(dev_context->dsp_per_clks);
/*
* Avoid the subsequent WDT if it happens once,
* also if fatal error occurs.
*/
dsp_wdt_enable(false);
}

144
drivers/staging/tidspbridge/core/wdt.c
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@ -1,144 +0,0 @@
/*
* wdt.c
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* IO dispatcher for a shared memory channel driver.
*
* Copyright (C) 2010 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#include <linux/types.h>
#include <dspbridge/dbdefs.h>
#include <dspbridge/dspdeh.h>
#include <dspbridge/dev.h>
#include <dspbridge/_chnl_sm.h>
#include <dspbridge/wdt.h>
#include <dspbridge/host_os.h>
#define OMAP34XX_WDT3_BASE (0x49000000 + 0x30000)
#define INT_34XX_WDT3_IRQ (36 + NR_IRQS)
static struct dsp_wdt_setting dsp_wdt;
void dsp_wdt_dpc(unsigned long data)
{
struct deh_mgr *deh_mgr;
dev_get_deh_mgr(dev_get_first(), &deh_mgr);
if (deh_mgr)
bridge_deh_notify(deh_mgr, DSP_WDTOVERFLOW, 0);
}
irqreturn_t dsp_wdt_isr(int irq, void *data)
{
u32 value;
/* ack wdt3 interrupt */
value = __raw_readl(dsp_wdt.reg_base + OMAP3_WDT3_ISR_OFFSET);
__raw_writel(value, dsp_wdt.reg_base + OMAP3_WDT3_ISR_OFFSET);
tasklet_schedule(&dsp_wdt.wdt3_tasklet);
return IRQ_HANDLED;
}
int dsp_wdt_init(void)
{
int ret = 0;
dsp_wdt.sm_wdt = NULL;
dsp_wdt.reg_base = ioremap(OMAP34XX_WDT3_BASE, SZ_4K);
if (!dsp_wdt.reg_base)
return -ENOMEM;
tasklet_init(&dsp_wdt.wdt3_tasklet, dsp_wdt_dpc, 0);
dsp_wdt.fclk = clk_get(NULL, "wdt3_fck");
if (!IS_ERR(dsp_wdt.fclk)) {
clk_prepare(dsp_wdt.fclk);
dsp_wdt.iclk = clk_get(NULL, "wdt3_ick");
if (IS_ERR(dsp_wdt.iclk)) {
clk_put(dsp_wdt.fclk);
dsp_wdt.fclk = NULL;
ret = -EFAULT;
} else {
clk_prepare(dsp_wdt.iclk);
}
} else
ret = -EFAULT;
if (!ret)
ret = request_irq(INT_34XX_WDT3_IRQ, dsp_wdt_isr, 0,
"dsp_wdt", &dsp_wdt);
/* Disable at this moment, it will be enabled when DSP starts */
if (!ret)
disable_irq(INT_34XX_WDT3_IRQ);
return ret;
}
void dsp_wdt_sm_set(void *data)
{
dsp_wdt.sm_wdt = data;
dsp_wdt.sm_wdt->wdt_overflow = 5; /* in seconds */
}
void dsp_wdt_exit(void)
{
free_irq(INT_34XX_WDT3_IRQ, &dsp_wdt);
tasklet_kill(&dsp_wdt.wdt3_tasklet);
if (dsp_wdt.fclk) {
clk_unprepare(dsp_wdt.fclk);
clk_put(dsp_wdt.fclk);
}
if (dsp_wdt.iclk) {
clk_unprepare(dsp_wdt.iclk);
clk_put(dsp_wdt.iclk);
}
dsp_wdt.fclk = NULL;
dsp_wdt.iclk = NULL;
dsp_wdt.sm_wdt = NULL;
if (dsp_wdt.reg_base)
iounmap(dsp_wdt.reg_base);
dsp_wdt.reg_base = NULL;
}
void dsp_wdt_enable(bool enable)
{
u32 tmp;
static bool wdt_enable;
if (wdt_enable == enable || !dsp_wdt.fclk || !dsp_wdt.iclk)
return;
wdt_enable = enable;
if (enable) {
clk_enable(dsp_wdt.fclk);
clk_enable(dsp_wdt.iclk);
dsp_wdt.sm_wdt->wdt_setclocks = 1;
tmp = __raw_readl(dsp_wdt.reg_base + OMAP3_WDT3_ISR_OFFSET);
__raw_writel(tmp, dsp_wdt.reg_base + OMAP3_WDT3_ISR_OFFSET);
enable_irq(INT_34XX_WDT3_IRQ);
} else {
disable_irq(INT_34XX_WDT3_IRQ);
dsp_wdt.sm_wdt->wdt_setclocks = 0;
clk_disable(dsp_wdt.iclk);
clk_disable(dsp_wdt.fclk);
}
}

1959
drivers/staging/tidspbridge/dynload/cload.c
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344
drivers/staging/tidspbridge/dynload/dload_internal.h
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@ -1,344 +0,0 @@
/*
* dload_internal.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef _DLOAD_INTERNAL_
#define _DLOAD_INTERNAL_
#include <linux/types.h>
/*
* Internal state definitions for the dynamic loader
*/
/* type used for relocation intermediate results */
typedef s32 rvalue;
/* unsigned version of same; must have at least as many bits */
typedef u32 urvalue;
/*
* Dynamic loader configuration constants
*/
/* error issued if input has more sections than this limit */
#define REASONABLE_SECTION_LIMIT 100
/* (Addressable unit) value used to clear BSS section */
#define DLOAD_FILL_BSS 0
/*
* Reorder maps explained (?)
*
* The doff file format defines a 32-bit pattern used to determine the
* byte order of an image being read. That value is
* BYTE_RESHUFFLE_VALUE == 0x00010203
* For purposes of the reorder routine, we would rather have the all-is-OK
* for 32-bits pattern be 0x03020100. This first macro makes the
* translation from doff file header value to MAP value: */
#define REORDER_MAP(rawmap) ((rawmap) ^ 0x3030303)
/* This translation is made in dload_headers. Thereafter, the all-is-OK
* value for the maps stored in dlthis is REORDER_MAP(BYTE_RESHUFFLE_VALUE).
* But sadly, not all bits of the doff file are 32-bit integers.
* The notable exceptions are strings and image bits.
* Strings obey host byte order: */
#if defined(_BIG_ENDIAN)
#define HOST_BYTE_ORDER(cookedmap) ((cookedmap) ^ 0x3030303)
#else
#define HOST_BYTE_ORDER(cookedmap) (cookedmap)
#endif
/* Target bits consist of target AUs (could be bytes, or 16-bits,
* or 32-bits) stored as an array in host order. A target order
* map is defined by: */
#if !defined(_BIG_ENDIAN) || TARGET_AU_BITS > 16
#define TARGET_ORDER(cookedmap) (cookedmap)
#elif TARGET_AU_BITS > 8
#define TARGET_ORDER(cookedmap) ((cookedmap) ^ 0x2020202)
#else
#define TARGET_ORDER(cookedmap) ((cookedmap) ^ 0x3030303)
#endif
/* forward declaration for handle returned by dynamic loader */
struct my_handle;
/*
* a list of module handles, which mirrors the debug list on the target
*/
struct dbg_mirror_root {
/* must be same as dbg_mirror_list; __DLModules address on target */
u32 dbthis;
struct my_handle *next; /* must be same as dbg_mirror_list */
u16 changes; /* change counter */
u16 refcount; /* number of modules referencing this root */
};
struct dbg_mirror_list {
u32 dbthis;
struct my_handle *next, *prev;
struct dbg_mirror_root *root;
u16 dbsiz;
u32 context; /* Save context for .dllview memory allocation */
};
#define VARIABLE_SIZE 1
/*
* the structure we actually return as an opaque module handle
*/
struct my_handle {
struct dbg_mirror_list dm; /* !!! must be first !!! */
/* sections following << 1, LSB is set for big-endian target */
u16 secn_count;
struct ldr_section_info secns[VARIABLE_SIZE];
};
#define MY_HANDLE_SIZE (sizeof(struct my_handle) -\
sizeof(struct ldr_section_info))
/* real size of my_handle */
/*
* reduced symbol structure used for symbols during relocation
*/
struct local_symbol {
s32 value; /* Relocated symbol value */
s32 delta; /* Original value in input file */
s16 secnn; /* section number */
s16 sclass; /* symbol class */
};
/*
* Trampoline data structures
*/
#define TRAMP_NO_GEN_AVAIL 65535
#define TRAMP_SYM_PREFIX "__$dbTR__"
#define TRAMP_SECT_NAME ".dbTR"
/* MUST MATCH THE LENGTH ABOVE!! */
#define TRAMP_SYM_PREFIX_LEN 9
/* Includes NULL termination */
#define TRAMP_SYM_HEX_ASCII_LEN 9
#define GET_CONTAINER(ptr, type, field) ((type *)((unsigned long)ptr -\
(unsigned long)(&((type *)0)->field)))
#ifndef FIELD_OFFSET
#define FIELD_OFFSET(type, field) ((unsigned long)(&((type *)0)->field))
#endif
/*
The trampoline code for the target is located in a table called
"tramp_gen_info" with is indexed by looking up the index in the table
"tramp_map". The tramp_map index is acquired using the target
HASH_FUNC on the relocation type that caused the trampoline. Each
trampoline code table entry MUST follow this format:
|----------------------------------------------|
| tramp_gen_code_hdr |
|----------------------------------------------|
| Trampoline image code |
| (the raw instruction code for the target) |
|----------------------------------------------|
| Relocation entries for the image code |
|----------------------------------------------|
This is very similar to how image data is laid out in the DOFF file
itself.
*/
struct tramp_gen_code_hdr {
u32 tramp_code_size; /* in BYTES */
u32 num_relos;
u32 relo_offset; /* in BYTES */
};
struct tramp_img_pkt {
struct tramp_img_pkt *next; /* MUST BE FIRST */
u32 base;
struct tramp_gen_code_hdr hdr;
u8 payload[VARIABLE_SIZE];
};
struct tramp_img_dup_relo {
struct tramp_img_dup_relo *next;
struct reloc_record_t relo;
};
struct tramp_img_dup_pkt {
struct tramp_img_dup_pkt *next; /* MUST BE FIRST */
s16 secnn;
u32 offset;
struct image_packet_t img_pkt;
struct tramp_img_dup_relo *relo_chain;
/* PAYLOAD OF IMG PKT FOLLOWS */
};
struct tramp_sym {
struct tramp_sym *next; /* MUST BE FIRST */
u32 index;
u32 str_index;
struct local_symbol sym_info;
};
struct tramp_string {
struct tramp_string *next; /* MUST BE FIRST */
u32 index;
char str[VARIABLE_SIZE]; /* NULL terminated */
};
struct tramp_info {
u32 tramp_sect_next_addr;
struct ldr_section_info sect_info;
struct tramp_sym *symbol_head;
struct tramp_sym *symbol_tail;
u32 tramp_sym_next_index;
struct local_symbol *final_sym_table;
struct tramp_string *string_head;
struct tramp_string *string_tail;
u32 tramp_string_next_index;
u32 tramp_string_size;
char *final_string_table;
struct tramp_img_pkt *tramp_pkts;
struct tramp_img_dup_pkt *dup_pkts;
};
/*
* States of the .cinit state machine
*/
enum cinit_mode {
CI_COUNT = 0, /* expecting a count */
CI_ADDRESS, /* expecting an address */
#if CINIT_ALIGN < CINIT_ADDRESS /* handle case of partial address field */
CI_PARTADDRESS, /* have only part of the address */
#endif
CI_COPY, /* in the middle of copying data */
CI_DONE /* end of .cinit table */
};
/*
* The internal state of the dynamic loader, which is passed around as
* an object
*/
struct dload_state {
struct dynamic_loader_stream *strm; /* The module input stream */
struct dynamic_loader_sym *mysym; /* Symbols for this session */
/* target memory allocator */
struct dynamic_loader_allocate *myalloc;
struct dynamic_loader_initialize *myio; /* target memory initializer */
unsigned myoptions; /* Options parameter dynamic_load_module */
char *str_head; /* Pointer to string table */
#if BITS_PER_AU > BITS_PER_BYTE
char *str_temp; /* Pointer to temporary buffer for strings */
/* big enough to hold longest string */
unsigned temp_len; /* length of last temporary string */
char *xstrings; /* Pointer to buffer for expanded */
/* strings for sec names */
#endif
/* Total size of strings for DLLView section names */
unsigned debug_string_size;
/* Pointer to parallel section info for allocated sections only */
struct doff_scnhdr_t *sect_hdrs; /* Pointer to section table */
struct ldr_section_info *ldr_sections;
#if TMS32060
/* The address of the start of the .bss section */
ldr_addr bss_run_base;
#endif
struct local_symbol *local_symtab; /* Relocation symbol table */
/* pointer to DL section info for the section being relocated */
struct ldr_section_info *image_secn;
/* change in run address for current section during relocation */
ldr_addr delta_runaddr;
ldr_addr image_offset; /* offset of current packet in section */
enum cinit_mode cinit_state; /* current state of cload_cinit() */
int cinit_count; /* the current count */
ldr_addr cinit_addr; /* the current address */
s16 cinit_page; /* the current page */
/* Handle to be returned by dynamic_load_module */
struct my_handle *myhandle;
unsigned dload_errcount; /* Total # of errors reported so far */
/* Number of target sections that require allocation and relocation */
unsigned allocated_secn_count;
#ifndef TARGET_ENDIANNESS
int big_e_target; /* Target data in big-endian format */
#endif
/* map for reordering bytes, 0 if not needed */
u32 reorder_map;
struct doff_filehdr_t dfile_hdr; /* DOFF file header structure */
struct doff_verify_rec_t verify; /* Verify record */
struct tramp_info tramp; /* Trampoline data, if needed */
int relstkidx; /* index into relocation value stack */
/* relocation value stack used in relexp.c */
rvalue relstk[STATIC_EXPR_STK_SIZE];
};
#ifdef TARGET_ENDIANNESS
#define TARGET_BIG_ENDIAN TARGET_ENDIANNESS
#else
#define TARGET_BIG_ENDIAN (dlthis->big_e_target)
#endif
/*
* Exports from cload.c to rest of the world
*/
extern void dload_error(struct dload_state *dlthis, const char *errtxt, ...);
extern void dload_syms_error(struct dynamic_loader_sym *syms,
const char *errtxt, ...);
extern void dload_headers(struct dload_state *dlthis);
extern void dload_strings(struct dload_state *dlthis, bool sec_names_only);
extern void dload_sections(struct dload_state *dlthis);
extern void dload_reorder(void *data, int dsiz, u32 map);
extern u32 dload_checksum(void *data, unsigned siz);
#if HOST_ENDIANNESS
extern uint32_t dload_reverse_checksum(void *data, unsigned siz);
#if (TARGET_AU_BITS > 8) && (TARGET_AU_BITS < 32)
extern uint32_t dload_reverse_checksum16(void *data, unsigned siz);
#endif
#endif
/*
* exported by reloc.c
*/
extern void dload_relocate(struct dload_state *dlthis, tgt_au_t *data,
struct reloc_record_t *rp, bool *tramps_generated,
bool second_pass);
extern rvalue dload_unpack(struct dload_state *dlthis, tgt_au_t *data,
int fieldsz, int offset, unsigned sgn);
extern int dload_repack(struct dload_state *dlthis, rvalue val, tgt_au_t *data,
int fieldsz, int offset, unsigned sgn);
/*
* exported by tramp.c
*/
extern bool dload_tramp_avail(struct dload_state *dlthis,
struct reloc_record_t *rp);
int dload_tramp_generate(struct dload_state *dlthis, s16 secnn,
u32 image_offset, struct image_packet_t *ipacket,
struct reloc_record_t *rp);
extern int dload_tramp_pkt_udpate(struct dload_state *dlthis,
s16 secnn, u32 image_offset,
struct image_packet_t *ipacket);
extern int dload_tramp_finalize(struct dload_state *dlthis);
extern void dload_tramp_cleanup(struct dload_state *dlthis);
#endif /* _DLOAD_INTERNAL_ */

354
drivers/staging/tidspbridge/dynload/doff.h
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@ -1,354 +0,0 @@
/*
* doff.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Structures & definitions used for dynamically loaded modules file format.
* This format is a reformatted version of COFF. It optimizes the layout for
* the dynamic loader.
*
* .dof files, when viewed as a sequence of 32-bit integers, look the same
* on big-endian and little-endian machines.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef _DOFF_H
#define _DOFF_H
#define BYTE_RESHUFFLE_VALUE 0x00010203
/* DOFF file header containing fields categorizing the remainder of the file */
struct doff_filehdr_t {
/* string table size, including filename, in bytes */
u32 df_strtab_size;
/* entry point if one exists */
u32 df_entrypt;
/* identifies byte ordering of file;
* always set to BYTE_RESHUFFLE_VALUE */
u32 df_byte_reshuffle;
/* Size of the string table up to and including the last section name */
/* Size includes the name of the COFF file also */
u32 df_scn_name_size;
#ifndef _BIG_ENDIAN
/* number of symbols */
u16 df_no_syms;
/* length in bytes of the longest string, including terminating NULL */
/* excludes the name of the file */
u16 df_max_str_len;
/* total number of sections including no-load ones */
u16 df_no_scns;
/* number of sections containing target code allocated or downloaded */
u16 df_target_scns;
/* unique id for dll file format & version */
u16 df_doff_version;
/* identifies ISA */
u16 df_target_id;
/* useful file flags */
u16 df_flags;
/* section reference for entry point, N_UNDEF for none, */
/* N_ABS for absolute address */
s16 df_entry_secn;
#else
/* length of the longest string, including terminating NULL */
u16 df_max_str_len;
/* number of symbols */
u16 df_no_syms;
/* number of sections containing target code allocated or downloaded */
u16 df_target_scns;
/* total number of sections including no-load ones */
u16 df_no_scns;
/* identifies ISA */
u16 df_target_id;
/* unique id for dll file format & version */
u16 df_doff_version;
/* section reference for entry point, N_UNDEF for none, */
/* N_ABS for absolute address */
s16 df_entry_secn;
/* useful file flags */
u16 df_flags;
#endif
/* checksum for file header record */
u32 df_checksum;
};
/* flags in the df_flags field */
#define DF_LITTLE 0x100
#define DF_BIG 0x200
#define DF_BYTE_ORDER (DF_LITTLE | DF_BIG)
/* Supported processors */
#define TMS470_ID 0x97
#define LEAD_ID 0x98
#define TMS32060_ID 0x99
#define LEAD3_ID 0x9c
/* Primary processor for loading */
#if TMS32060
#define TARGET_ID TMS32060_ID
#endif
/* Verification record containing values used to test integrity of the bits */
struct doff_verify_rec_t {
/* time and date stamp */
u32 dv_timdat;
/* checksum for all section records */
u32 dv_scn_rec_checksum;
/* checksum for string table */
u32 dv_str_tab_checksum;
/* checksum for symbol table */
u32 dv_sym_tab_checksum;
/* checksum for verification record */
u32 dv_verify_rec_checksum;
};
/* String table is an array of null-terminated strings. The first entry is
* the filename, which is added by DLLcreate. No new structure definitions
* are required.
*/
/* Section Records including information on the corresponding image packets */
/*
* !!WARNING!!
*
* This structure is expected to match in form ldr_section_info in
* dynamic_loader.h
*/
struct doff_scnhdr_t {
s32 ds_offset; /* offset into string table of name */
s32 ds_paddr; /* RUN address, in target AU */
s32 ds_vaddr; /* LOAD address, in target AU */
s32 ds_size; /* section size, in target AU */
#ifndef _BIG_ENDIAN
u16 ds_page; /* memory page id */
u16 ds_flags; /* section flags */
#else
u16 ds_flags; /* section flags */
u16 ds_page; /* memory page id */
#endif
u32 ds_first_pkt_offset;
/* Absolute byte offset into the file */
/* where the first image record resides */
s32 ds_nipacks; /* number of image packets */
};
/* Symbol table entry */
struct doff_syment_t {
s32 dn_offset; /* offset into string table of name */
s32 dn_value; /* value of symbol */
#ifndef _BIG_ENDIAN
s16 dn_scnum; /* section number */
s16 dn_sclass; /* storage class */
#else
s16 dn_sclass; /* storage class */
s16 dn_scnum; /* section number, 1-based */
#endif
};
/* special values for dn_scnum */
#define DN_UNDEF 0 /* undefined symbol */
#define DN_ABS (-1) /* value of symbol is absolute */
/* special values for dn_sclass */
#define DN_EXT 2
#define DN_STATLAB 20
#define DN_EXTLAB 21
/* Default value of image bits in packet */
/* Configurable by user on the command line */
#define IMAGE_PACKET_SIZE 1024
/* An image packet contains a chunk of data from a section along with */
/* information necessary for its processing. */
struct image_packet_t {
s32 num_relocs; /* number of relocations for */
/* this packet */
s32 packet_size; /* number of bytes in array */
/* "bits" occupied by */
/* valid data. Could be */
/* < IMAGE_PACKET_SIZE to */
/* prevent splitting a */
/* relocation across packets. */
/* Last packet of a section */
/* will most likely contain */
/* < IMAGE_PACKET_SIZE bytes */
/* of valid data */
s32 img_chksum; /* Checksum for image packet */
/* and the corresponding */
/* relocation records */
u8 *img_data; /* Actual data in section */
};
/* The relocation structure definition matches the COFF version. Offsets */
/* however are relative to the image packet base not the section base. */
struct reloc_record_t {
s32 vaddr;
/* expressed in target AUs */
union {
struct {
#ifndef _BIG_ENDIAN
u8 _offset; /* bit offset of rel fld */
u8 _fieldsz; /* size of rel fld */
u8 _wordsz; /* # bytes containing rel fld */
u8 _dum1;
u16 _dum2;
u16 _type;
#else
unsigned _dum1:8;
unsigned _wordsz:8; /* # bytes containing rel fld */
unsigned _fieldsz:8; /* size of rel fld */
unsigned _offset:8; /* bit offset of rel fld */
u16 _type;
u16 _dum2;
#endif
} _r_field;
struct {
u32 _spc; /* image packet relative PC */
#ifndef _BIG_ENDIAN
u16 _dum;
u16 _type; /* relocation type */
#else
u16 _type; /* relocation type */
u16 _dum;
#endif
} _r_spc;
struct {
u32 _uval; /* constant value */
#ifndef _BIG_ENDIAN
u16 _dum;
u16 _type; /* relocation type */
#else
u16 _type; /* relocation type */
u16 _dum;
#endif
} _r_uval;
struct {
s32 _symndx; /* 32-bit sym tbl index */
#ifndef _BIG_ENDIAN
u16 _disp; /* extra addr encode data */
u16 _type; /* relocation type */
#else
u16 _type; /* relocation type */
u16 _disp; /* extra addr encode data */
#endif
} _r_sym;
} _u_reloc;
};
/* abbreviations for convenience */
#ifndef TYPE
#define TYPE _u_reloc._r_sym._type
#define UVAL _u_reloc._r_uval._uval
#define SYMNDX _u_reloc._r_sym._symndx
#define OFFSET _u_reloc._r_field._offset
#define FIELDSZ _u_reloc._r_field._fieldsz
#define WORDSZ _u_reloc._r_field._wordsz
#define R_DISP _u_reloc._r_sym._disp
#endif
/**************************************************************************** */
/* */
/* Important DOFF macros used for file processing */
/* */
/**************************************************************************** */
/* DOFF Versions */
#define DOFF0 0
/* Return the address/size >= to addr that is at a 32-bit boundary */
/* This assumes that a byte is 8 bits */
#define DOFF_ALIGN(addr) (((addr) + 3) & ~3UL)
/**************************************************************************** */
/* */
/* The DOFF section header flags field is laid out as follows: */
/* */
/* Bits 0-3 : Section Type */
/* Bit 4 : Set when section requires target memory to be allocated by DL */
/* Bit 5 : Set when section requires downloading */
/* Bits 8-11: Alignment, same as COFF */
/* */
/**************************************************************************** */
/* Enum for DOFF section types (bits 0-3 of flag): See dynamic_loader.h */
#define DS_SECTION_TYPE_MASK 0xF
/* DS_ALLOCATE indicates whether a section needs space on the target */
#define DS_ALLOCATE_MASK 0x10
/* DS_DOWNLOAD indicates that the loader needs to copy bits */
#define DS_DOWNLOAD_MASK 0x20
/* Section alignment requirement in AUs */
#define DS_ALIGNMENT_SHIFT 8
static inline bool dload_check_type(struct doff_scnhdr_t *sptr, u32 flag)
{
return (sptr->ds_flags & DS_SECTION_TYPE_MASK) == flag;
}
static inline bool ds_needs_allocation(struct doff_scnhdr_t *sptr)
{
return sptr->ds_flags & DS_ALLOCATE_MASK;
}
static inline bool ds_needs_download(struct doff_scnhdr_t *sptr)
{
return sptr->ds_flags & DS_DOWNLOAD_MASK;
}
static inline int ds_alignment(u16 ds_flags)
{
return 1 << ((ds_flags >> DS_ALIGNMENT_SHIFT) & DS_SECTION_TYPE_MASK);
}
#endif /* _DOFF_H */

407
drivers/staging/tidspbridge/dynload/getsection.c
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@ -1,407 +0,0 @@
/*
* getsection.c
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#include <dspbridge/getsection.h>
#include "header.h"
/*
* Error strings
*/
static const char readstrm[] = { "Error reading %s from input stream" };
static const char seek[] = { "Set file position to %d failed" };
static const char isiz[] = { "Bad image packet size %d" };
static const char err_checksum[] = { "Checksum failed on %s" };
static const char err_reloc[] = { "dload_get_section unable to read"
"sections containing relocation entries"
};
#if BITS_PER_AU > BITS_PER_BYTE
static const char err_alloc[] = { "Syms->dload_allocate( %d ) failed" };
static const char stbl[] = { "Bad string table offset " FMT_UI32 };
#endif
/************************************************************** */
/********************* SUPPORT FUNCTIONS ********************** */
/************************************************************** */
#if BITS_PER_AU > BITS_PER_BYTE
/**************************************************************************
* Procedure unpack_sec_name
*
* Parameters:
* dlthis Handle from dload_module_open for this module
* soffset Byte offset into the string table
* dst Place to store the expanded string
*
* Effect:
* Stores a string from the string table into the destination, expanding
* it in the process. Returns a pointer just past the end of the stored
* string on success, or NULL on failure.
*
************************************************************************ */
static char *unpack_sec_name(struct dload_state *dlthis, u32 soffset, char *dst)
{
u8 tmp, *src;
if (soffset >= dlthis->dfile_hdr.df_scn_name_size) {
dload_error(dlthis, stbl, soffset);
return NULL;
}
src = (u8 *) dlthis->str_head +
(soffset >> (LOG_BITS_PER_AU - LOG_BITS_PER_BYTE));
if (soffset & 1)
*dst++ = *src++; /* only 1 character in first word */
do {
tmp = *src++;
*dst = (tmp >> BITS_PER_BYTE)
if (!(*dst++))
break;
} while ((*dst++ = tmp & BYTE_MASK));
return dst;
}
/**************************************************************************
* Procedure expand_sec_names
*
* Parameters:
* dlthis Handle from dload_module_open for this module
*
* Effect:
* Allocates a buffer, unpacks and copies strings from string table into it.
* Stores a pointer to the buffer into a state variable.
************************************************************************* */
static void expand_sec_names(struct dload_state *dlthis)
{
char *xstrings, *curr, *next;
u32 xsize;
u16 sec;
struct ldr_section_info *shp;
/* assume worst-case size requirement */
xsize = dlthis->dfile_hdr.df_max_str_len * dlthis->dfile_hdr.df_no_scns;
xstrings = (char *)dlthis->mysym->dload_allocate(dlthis->mysym, xsize);
if (xstrings == NULL) {
dload_error(dlthis, err_alloc, xsize);
return;
}
dlthis->xstrings = xstrings;
/* For each sec, copy and expand its name */
curr = xstrings;
for (sec = 0; sec < dlthis->dfile_hdr.df_no_scns; sec++) {
shp = (struct ldr_section_info *)&dlthis->sect_hdrs[sec];
next = unpack_sec_name(dlthis, *(u32 *) &shp->name, curr);
if (next == NULL)
break; /* error */
shp->name = curr;
curr = next;
}
}
#endif
/************************************************************** */
/********************* EXPORTED FUNCTIONS ********************* */
/************************************************************** */
/**************************************************************************
* Procedure dload_module_open
*
* Parameters:
* module The input stream that supplies the module image
* syms Host-side malloc/free and error reporting functions.
* Other methods are unused.
*
* Effect:
* Reads header information from a dynamic loader module using the
specified
* stream object, and returns a handle for the module information. This
* handle may be used in subsequent query calls to obtain information
* contained in the module.
*
* Returns:
* NULL if an error is encountered, otherwise a module handle for use
* in subsequent operations.
************************************************************************* */
void *dload_module_open(struct dynamic_loader_stream *module,
struct dynamic_loader_sym *syms)
{
struct dload_state *dlthis; /* internal state for this call */
unsigned *dp, sz;
u32 sec_start;
#if BITS_PER_AU <= BITS_PER_BYTE
u16 sec;
#endif
/* Check that mandatory arguments are present */
if (!module || !syms) {
if (syms != NULL)
dload_syms_error(syms, "Required parameter is NULL");
return NULL;
}
dlthis = (struct dload_state *)
syms->dload_allocate(syms, sizeof(struct dload_state));
if (!dlthis) {
/* not enough storage */
dload_syms_error(syms, "Can't allocate module info");
return NULL;
}
/* clear our internal state */
dp = (unsigned *)dlthis;
for (sz = sizeof(struct dload_state) / sizeof(unsigned);
sz > 0; sz -= 1)
*dp++ = 0;
dlthis->strm = module;
dlthis->mysym = syms;
/* read in the doff image and store in our state variable */
dload_headers(dlthis);
if (!dlthis->dload_errcount)
dload_strings(dlthis, true);
/* skip ahead past the unread portion of the string table */
sec_start = sizeof(struct doff_filehdr_t) +
sizeof(struct doff_verify_rec_t) +
BYTE_TO_HOST(DOFF_ALIGN(dlthis->dfile_hdr.df_strtab_size));
if (dlthis->strm->set_file_posn(dlthis->strm, sec_start) != 0) {
dload_error(dlthis, seek, sec_start);
return NULL;
}
if (!dlthis->dload_errcount)
dload_sections(dlthis);
if (dlthis->dload_errcount) {
dload_module_close(dlthis); /* errors, blow off our state */
dlthis = NULL;
return NULL;
}
#if BITS_PER_AU > BITS_PER_BYTE
/* Expand all section names from the string table into the */
/* state variable, and convert section names from a relative */
/* string table offset to a pointers to the expanded string. */
expand_sec_names(dlthis);
#else
/* Convert section names from a relative string table offset */
/* to a pointer into the string table. */
for (sec = 0; sec < dlthis->dfile_hdr.df_no_scns; sec++) {
struct ldr_section_info *shp =
(struct ldr_section_info *)&dlthis->sect_hdrs[sec];
shp->name = dlthis->str_head + *(u32 *) &shp->name;
}
#endif
return dlthis;
}
/***************************************************************************
* Procedure dload_get_section_info
*
* Parameters:
* minfo Handle from dload_module_open for this module
* section_name Pointer to the string name of the section desired
* section_info Address of a section info structure pointer to be
* initialized
*
* Effect:
* Finds the specified section in the module information, and initializes
* the provided struct ldr_section_info pointer.
*
* Returns:
* true for success, false for section not found
************************************************************************* */
int dload_get_section_info(void *minfo, const char *section_name,
const struct ldr_section_info **const section_info)
{
struct dload_state *dlthis;
struct ldr_section_info *shp;
u16 sec;
dlthis = (struct dload_state *)minfo;
if (!dlthis)
return false;
for (sec = 0; sec < dlthis->dfile_hdr.df_no_scns; sec++) {
shp = (struct ldr_section_info *)&dlthis->sect_hdrs[sec];
if (strcmp(section_name, shp->name) == 0) {
*section_info = shp;
return true;
}
}
return false;
}
#define IPH_SIZE (sizeof(struct image_packet_t) - sizeof(u32))
/**************************************************************************
* Procedure dload_get_section
*
* Parameters:
* minfo Handle from dload_module_open for this module
* section_info Pointer to a section info structure for the desired
* section
* section_data Buffer to contain the section initialized data
*
* Effect:
* Copies the initialized data for the specified section into the
* supplied buffer.
*
* Returns:
* true for success, false for section not found
************************************************************************* */
int dload_get_section(void *minfo,
const struct ldr_section_info *section_info,
void *section_data)
{
struct dload_state *dlthis;
u32 pos;
struct doff_scnhdr_t *sptr = NULL;
s32 nip;
struct image_packet_t ipacket;
s32 ipsize;
u32 checks;
s8 *dest = (s8 *) section_data;
dlthis = (struct dload_state *)minfo;
if (!dlthis)
return false;
sptr = (struct doff_scnhdr_t *)section_info;
if (sptr == NULL)
return false;
/* skip ahead to the start of the first packet */
pos = BYTE_TO_HOST(DOFF_ALIGN((u32) sptr->ds_first_pkt_offset));
if (dlthis->strm->set_file_posn(dlthis->strm, pos) != 0) {
dload_error(dlthis, seek, pos);
return false;
}
nip = sptr->ds_nipacks;
while ((nip -= 1) >= 0) { /* for each packet */
/* get the fixed header bits */
if (dlthis->strm->read_buffer(dlthis->strm, &ipacket,
IPH_SIZE) != IPH_SIZE) {
dload_error(dlthis, readstrm, "image packet");
return false;
}
/* reorder the header if need be */
if (dlthis->reorder_map)
dload_reorder(&ipacket, IPH_SIZE, dlthis->reorder_map);
/* Now read the packet image bits. Note: round the size up to
* the next multiple of 4 bytes; this is what checksum
* routines want. */
ipsize = BYTE_TO_HOST(DOFF_ALIGN(ipacket.packet_size));
if (ipsize > BYTE_TO_HOST(IMAGE_PACKET_SIZE)) {
dload_error(dlthis, isiz, ipsize);
return false;
}
if (dlthis->strm->read_buffer
(dlthis->strm, dest, ipsize) != ipsize) {
dload_error(dlthis, readstrm, "image packet");
return false;
}
/* reorder the bytes if need be */
#if !defined(_BIG_ENDIAN) || (TARGET_AU_BITS > 16)
if (dlthis->reorder_map)
dload_reorder(dest, ipsize, dlthis->reorder_map);
checks = dload_checksum(dest, ipsize);
#else
if (dlthis->dfile_hdr.df_byte_reshuffle !=
TARGET_ORDER(REORDER_MAP(BYTE_RESHUFFLE_VALUE))) {
/* put image bytes in big-endian order, not PC order */
dload_reorder(dest, ipsize,
TARGET_ORDER(dlthis->
dfile_hdr.df_byte_reshuffle));
}
#if TARGET_AU_BITS > 8
checks = dload_reverse_checksum16(dest, ipsize);
#else
checks = dload_reverse_checksum(dest, ipsize);
#endif
#endif
checks += dload_checksum(&ipacket, IPH_SIZE);
/* NYI: unable to handle relocation entries here. Reloc
* entries referring to fields that span the packet boundaries
* may result in packets of sizes that are not multiple of
* 4 bytes. Our checksum implementation works on 32-bit words
* only. */
if (ipacket.num_relocs != 0) {
dload_error(dlthis, err_reloc, ipsize);
return false;
}
if (~checks) {
dload_error(dlthis, err_checksum, "image packet");
return false;
}
/*Advance destination ptr by the size of the just-read packet */
dest += ipsize;
}
return true;
}
/***************************************************************************
* Procedure dload_module_close
*
* Parameters:
* minfo Handle from dload_module_open for this module
*
* Effect:
* Releases any storage associated with the module handle. On return,
* the module handle is invalid.
*
* Returns:
* Zero for success. On error, the number of errors detected is returned.
* Individual errors are reported using syms->error_report(), where syms was
* an argument to dload_module_open
************************************************************************* */
void dload_module_close(void *minfo)
{
struct dload_state *dlthis;
dlthis = (struct dload_state *)minfo;
if (!dlthis)
return;
if (dlthis->str_head)
dlthis->mysym->dload_deallocate(dlthis->mysym,
dlthis->str_head);
if (dlthis->sect_hdrs)
dlthis->mysym->dload_deallocate(dlthis->mysym,
dlthis->sect_hdrs);
#if BITS_PER_AU > BITS_PER_BYTE
if (dlthis->xstrings)
dlthis->mysym->dload_deallocate(dlthis->mysym,
dlthis->xstrings);
#endif
dlthis->mysym->dload_deallocate(dlthis->mysym, dlthis);
}

49
drivers/staging/tidspbridge/dynload/header.h
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@ -1,49 +0,0 @@
/*
* header.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#include <linux/string.h>
#define DL_STRCMP strcmp
/* maximum parenthesis nesting in relocation stack expressions */
#define STATIC_EXPR_STK_SIZE 10
#include <linux/types.h>
#include "doff.h"
#include <dspbridge/dynamic_loader.h>
#include "params.h"
#include "dload_internal.h"
#include "reloc_table.h"
/*
* Plausibility limits
*
* These limits are imposed upon the input DOFF file as a check for validity.
* They are hard limits, in that the load will fail if they are exceeded.
* The numbers selected are arbitrary, in that the loader implementation does
* not require these limits.
*/
/* maximum number of bytes in string table */
#define MAX_REASONABLE_STRINGTAB (0x100000)
/* maximum number of code,data,etc. sections */
#define MAX_REASONABLE_SECTIONS (200)
/* maximum number of linker symbols */
#define MAX_REASONABLE_SYMBOLS (100000)
/* shift count to align F_BIG with DLOAD_LITTLE */
#define ALIGN_COFF_ENDIANNESS 7
#define ENDIANNESS_MASK (DF_BYTE_ORDER >> ALIGN_COFF_ENDIANNESS)

159
drivers/staging/tidspbridge/dynload/module_list.h
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@ -1,159 +0,0 @@
/*
* dspbridge/mpu_driver/src/dynload/module_list.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Copyright (C) 2008 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
/*
* This C header file gives the layout of the data structure created by the
* dynamic loader to describe the set of modules loaded into the DSP.
*
* Linked List Structure:
* ----------------------
* The data structure defined here is a singly-linked list. The list
* represents the set of modules which are currently loaded in the DSP memory.
* The first entry in the list is a header record which contains a flag
* representing the state of the list. The rest of the entries in the list
* are module records.
*
* Global symbol _DLModules designates the first record in the list (i.e. the
* header record). This symbol must be defined in any program that wishes to
* use DLLview plug-in.
*
* String Representation:
* ----------------------
* The string names of the module and its sections are stored in a block of
* memory which follows the module record itself. The strings are ordered:
* module name first, followed by section names in order from the first
* section to the last. String names are tightly packed arrays of 8-bit
* characters (two characters per 16-bit word on the C55x). Strings are
* zero-byte-terminated.
*
* Creating and updating the list:
* -------------------------------
* Upon loading a new module into the DSP memory the dynamic loader inserts a
* new module record as the first module record in the list. The fields of
* this module record are initialized to reflect the properties of the module.
* The dynamic loader does NOT increment the flag/counter in the list's header
* record.
*
* Upon unloading a module from the DSP memory the dynamic loader removes the
* module's record from this list. The dynamic loader also increments the
* flag/counter in the list's header record to indicate that the list has been
* changed.
*/
#ifndef _MODULE_LIST_H_
#define _MODULE_LIST_H_
#include <linux/types.h>
/* Global pointer to the modules_header structure */
#define MODULES_HEADER "_DLModules"
#define MODULES_HEADER_NO_UNDERSCORE "DLModules"
/* Initial version number */
#define INIT_VERSION 1
/* Verification number -- to be recorded in each module record */
#define VERIFICATION 0x79
/* forward declarations */
struct dll_module;
struct dll_sect;
/* the first entry in the list is the modules_header record;
* its address is contained in the global _DLModules pointer */
struct modules_header {
/*
* Address of the first dll_module record in the list or NULL.
* Note: for C55x this is a word address (C55x data is
* word-addressable)
*/
u32 first_module;
/* Combined storage size (in target addressable units) of the
* dll_module record which follows this header record, or zero
* if the list is empty. This size includes the module's string table.
* Note: for C55x the unit is a 16-bit word */
u16 first_module_size;
/* Counter is incremented whenever a module record is removed from
* the list */
u16 update_flag;
};
/* for each 32-bits in above structure, a bitmap, LSB first, whose bits are:
* 0 => a 32-bit value, 1 => 2 16-bit values */
/* swapping bitmap for type modules_header */
#define MODULES_HEADER_BITMAP 0x2
/* information recorded about each section in a module */
struct dll_sect {
/* Load-time address of the section.
* Note: for C55x this is a byte address for program sections, and
* a word address for data sections. C55x program memory is
* byte-addressable, while data memory is word-addressable. */
u32 sect_load_adr;
/* Run-time address of the section.
* Note 1: for C55x this is a byte address for program sections, and
* a word address for data sections.
* Note 2: for C55x two most significant bits of this field indicate
* the section type: '00' for a code section, '11' for a data section
* (C55 addresses are really only 24-bits wide). */
u32 sect_run_adr;
};
/* the rest of the entries in the list are module records */
struct dll_module {
/* Address of the next dll_module record in the list, or 0 if this is
* the last record in the list.
* Note: for C55x this is a word address (C55x data is
* word-addressable) */
u32 next_module;
/* Combined storage size (in target addressable units) of the
* dll_module record which follows this one, or zero if this is the
* last record in the list. This size includes the module's string
* table.
* Note: for C55x the unit is a 16-bit word. */
u16 next_module_size;
/* version number of the tooling; set to INIT_VERSION for Phase 1 */
u16 version;
/* the verification word; set to VERIFICATION */
u16 verification;
/* Number of sections in the sects array */
u16 num_sects;
/* Module's "unique" id; copy of the timestamp from the host
* COFF file */
u32 timestamp;
/* Array of num_sects elements of the module's section records */
struct dll_sect sects[1];
};
/* for each 32 bits in above structure, a bitmap, LSB first, whose bits are:
* 0 => a 32-bit value, 1 => 2 16-bit values */
#define DLL_MODULE_BITMAP 0x6 /* swapping bitmap for type dll_module */
#endif /* _MODULE_LIST_H_ */

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drivers/staging/tidspbridge/dynload/params.h
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@ -1,226 +0,0 @@
/*
* params.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* This file defines host and target properties for all machines
* supported by the dynamic loader. To be tedious...
*
* host: the machine on which the dynamic loader runs
* target: the machine that the dynamic loader is loading
*
* Host and target may or may not be the same, depending upon the particular
* use.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
/******************************************************************************
*
* Host Properties
*
**************************************************************************** */
#define BITS_PER_BYTE 8 /* bits in the standard PC/SUN byte */
#define LOG_BITS_PER_BYTE 3 /* log base 2 of same */
#define BYTE_MASK ((1U<<BITS_PER_BYTE)-1)
#if defined(__TMS320C55X__) || defined(_TMS320C5XX)
#define BITS_PER_AU 16
#define LOG_BITS_PER_AU 4
/* use this print string in error messages for uint32_t */
#define FMT_UI32 "0x%lx"
#define FMT8_UI32 "%08lx" /* same but no 0x, fixed width field */
#else
/* bits in the smallest addressable data storage unit */
#define BITS_PER_AU 8
/* log base 2 of the same; useful for shift counts */
#define LOG_BITS_PER_AU 3
#define FMT_UI32 "0x%x"
#define FMT8_UI32 "%08x"
#endif
/* generic fastest method for swapping bytes and shorts */
#define SWAP32BY16(zz) (((zz) << 16) | ((zz) >> 16))
#define SWAP16BY8(zz) (((zz) << 8) | ((zz) >> 8))
/* !! don't be tempted to insert type definitions here; use <stdint.h> !! */
/******************************************************************************
*
* Target Properties
*
**************************************************************************** */
/*-------------------------------------------------------------------------- */
/* TMS320C6x Target Specific Parameters (byte-addressable) */
/*-------------------------------------------------------------------------- */
#if TMS32060
#define MEMORG 0x0L /* Size of configured memory */
#define MEMSIZE 0x0L /* (full address space) */
#define CINIT_ALIGN 8 /* alignment of cinit record in TDATA AUs */
#define CINIT_COUNT 4 /* width of count field in TDATA AUs */
#define CINIT_ADDRESS 4 /* width of address field in TDATA AUs */
#define CINIT_PAGE_BITS 0 /* Number of LSBs of address that
* are page number */
#define LENIENT_SIGNED_RELEXPS 0 /* DOES SIGNED ALLOW MAX UNSIGNED */
#undef TARGET_ENDIANNESS /* may be big or little endian */
/* align a target address to a word boundary */
#define TARGET_WORD_ALIGN(zz) (((zz) + 0x3) & -0x4)
#endif
/*--------------------------------------------------------------------------
*
* DEFAULT SETTINGS and DERIVED PROPERTIES
*
* This section establishes defaults for values not specified above
*-------------------------------------------------------------------------- */
#ifndef TARGET_AU_BITS
#define TARGET_AU_BITS 8 /* width of the target addressable unit */
#define LOG_TARGET_AU_BITS 3 /* log2 of same */
#endif
#ifndef CINIT_DEFAULT_PAGE
#define CINIT_DEFAULT_PAGE 0 /* default .cinit page number */
#endif
#ifndef DATA_RUN2LOAD
#define DATA_RUN2LOAD(zz) (zz) /* translate data run address to load address */
#endif
#ifndef DBG_LIST_PAGE
#define DBG_LIST_PAGE 0 /* page number for .dllview section */
#endif
#ifndef TARGET_WORD_ALIGN
/* align a target address to a word boundary */
#define TARGET_WORD_ALIGN(zz) (zz)
#endif
#ifndef TDATA_TO_TADDR
#define TDATA_TO_TADDR(zz) (zz) /* target data address to target AU address */
#define TADDR_TO_TDATA(zz) (zz) /* target AU address to target data address */
#define TDATA_AU_BITS TARGET_AU_BITS /* bits per data AU */
#define LOG_TDATA_AU_BITS LOG_TARGET_AU_BITS
#endif
/*
*
* Useful properties and conversions derived from the above
*
*/
/*
* Conversions between host and target addresses
*/
#if LOG_BITS_PER_AU == LOG_TARGET_AU_BITS
/* translate target addressable unit to host address */
#define TADDR_TO_HOST(x) (x)
/* translate host address to target addressable unit */
#define HOST_TO_TADDR(x) (x)
#elif LOG_BITS_PER_AU > LOG_TARGET_AU_BITS
#define TADDR_TO_HOST(x) ((x) >> (LOG_BITS_PER_AU-LOG_TARGET_AU_BITS))
#define HOST_TO_TADDR(x) ((x) << (LOG_BITS_PER_AU-LOG_TARGET_AU_BITS))
#else
#define TADDR_TO_HOST(x) ((x) << (LOG_TARGET_AU_BITS-LOG_BITS_PER_AU))
#define HOST_TO_TADDR(x) ((x) >> (LOG_TARGET_AU_BITS-LOG_BITS_PER_AU))
#endif
#if LOG_BITS_PER_AU == LOG_TDATA_AU_BITS
/* translate target addressable unit to host address */
#define TDATA_TO_HOST(x) (x)
/* translate host address to target addressable unit */
#define HOST_TO_TDATA(x) (x)
/* translate host address to target addressable unit, round up */
#define HOST_TO_TDATA_ROUND(x) (x)
/* byte offset to host offset, rounded up for TDATA size */
#define BYTE_TO_HOST_TDATA_ROUND(x) BYTE_TO_HOST_ROUND(x)
#elif LOG_BITS_PER_AU > LOG_TDATA_AU_BITS
#define TDATA_TO_HOST(x) ((x) >> (LOG_BITS_PER_AU-LOG_TDATA_AU_BITS))
#define HOST_TO_TDATA(x) ((x) << (LOG_BITS_PER_AU-LOG_TDATA_AU_BITS))
#define HOST_TO_TDATA_ROUND(x) ((x) << (LOG_BITS_PER_AU-LOG_TDATA_AU_BITS))
#define BYTE_TO_HOST_TDATA_ROUND(x) BYTE_TO_HOST_ROUND(x)
#else
#define TDATA_TO_HOST(x) ((x) << (LOG_TDATA_AU_BITS-LOG_BITS_PER_AU))
#define HOST_TO_TDATA(x) ((x) >> (LOG_TDATA_AU_BITS-LOG_BITS_PER_AU))
#define HOST_TO_TDATA_ROUND(x) (((x) +\
(1<<(LOG_TDATA_AU_BITS-LOG_BITS_PER_AU))-1) >>\
(LOG_TDATA_AU_BITS-LOG_BITS_PER_AU))
#define BYTE_TO_HOST_TDATA_ROUND(x) (BYTE_TO_HOST((x) +\
(1<<(LOG_TDATA_AU_BITS-LOG_BITS_PER_BYTE))-1) &\
-(TDATA_AU_BITS/BITS_PER_AU))
#endif
/*
* Input in DOFF format is always expresed in bytes, regardless of loading host
* so we wind up converting from bytes to target and host units even when the
* host is not a byte machine.
*/
#if LOG_BITS_PER_AU == LOG_BITS_PER_BYTE
#define BYTE_TO_HOST(x) (x)
#define BYTE_TO_HOST_ROUND(x) (x)
#define HOST_TO_BYTE(x) (x)
#elif LOG_BITS_PER_AU >= LOG_BITS_PER_BYTE
#define BYTE_TO_HOST(x) ((x) >> (LOG_BITS_PER_AU - LOG_BITS_PER_BYTE))
#define BYTE_TO_HOST_ROUND(x) ((x + (BITS_PER_AU/BITS_PER_BYTE-1)) >>\
(LOG_BITS_PER_AU - LOG_BITS_PER_BYTE))
#define HOST_TO_BYTE(x) ((x) << (LOG_BITS_PER_AU - LOG_BITS_PER_BYTE))
#else
/* lets not try to deal with sub-8-bit byte machines */
#endif
#if LOG_TARGET_AU_BITS == LOG_BITS_PER_BYTE
/* translate target addressable unit to byte address */
#define TADDR_TO_BYTE(x) (x)
/* translate byte address to target addressable unit */
#define BYTE_TO_TADDR(x) (x)
#elif LOG_TARGET_AU_BITS > LOG_BITS_PER_BYTE
#define TADDR_TO_BYTE(x) ((x) << (LOG_TARGET_AU_BITS-LOG_BITS_PER_BYTE))
#define BYTE_TO_TADDR(x) ((x) >> (LOG_TARGET_AU_BITS-LOG_BITS_PER_BYTE))
#else
/* lets not try to deal with sub-8-bit byte machines */
#endif
#ifdef _BIG_ENDIAN
#define HOST_ENDIANNESS 1
#else
#define HOST_ENDIANNESS 0
#endif
#ifdef TARGET_ENDIANNESS
#define TARGET_ENDIANNESS_DIFFERS(rtend) (HOST_ENDIANNESS^TARGET_ENDIANNESS)
#elif HOST_ENDIANNESS
#define TARGET_ENDIANNESS_DIFFERS(rtend) (!(rtend))
#else
#define TARGET_ENDIANNESS_DIFFERS(rtend) (rtend)
#endif
/* the unit in which we process target image data */
#if TARGET_AU_BITS <= 8
typedef u8 tgt_au_t;
#elif TARGET_AU_BITS <= 16
typedef u16 tgt_au_t;
#else
typedef u32 tgt_au_t;
#endif
/* size of that unit */
#if TARGET_AU_BITS < BITS_PER_AU
#define TGTAU_BITS BITS_PER_AU
#define LOG_TGTAU_BITS LOG_BITS_PER_AU
#else
#define TGTAU_BITS TARGET_AU_BITS
#define LOG_TGTAU_BITS LOG_TARGET_AU_BITS
#endif

486
drivers/staging/tidspbridge/dynload/reloc.c
View File

@ -1,486 +0,0 @@
/*
* reloc.c
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#include "header.h"
#if TMS32060
/* the magic symbol for the start of BSS */
static const char bsssymbol[] = { ".bss" };
#endif
#if TMS32060
#include "reloc_table_c6000.c"
#endif
#if TMS32060
/* From coff.h - ignore these relocation operations */
#define R_C60ALIGN 0x76 /* C60: Alignment info for compressor */
#define R_C60FPHEAD 0x77 /* C60: Explicit assembly directive */
#define R_C60NOCMP 0x100 /* C60: Don't compress this code scn */
#endif
/**************************************************************************
* Procedure dload_unpack
*
* Parameters:
* data pointer to storage unit containing lowest host address of
* image data
* fieldsz Size of bit field, 0 < fieldsz <= sizeof(rvalue)*BITS_PER_AU
* offset Offset from LSB, 0 <= offset < BITS_PER_AU
* sgn Signedness of the field (ROP_SGN, ROP_UNS, ROP_MAX, ROP_ANY)
*
* Effect:
* Extracts the specified field and returns it.
************************************************************************* */
rvalue dload_unpack(struct dload_state *dlthis, tgt_au_t *data, int fieldsz,
int offset, unsigned sgn)
{
register rvalue objval;
register int shift, direction;
register tgt_au_t *dp = data;
fieldsz -= 1; /* avoid nastiness with 32-bit shift of 32-bit value */
/* * collect up enough bits to contain the desired field */
if (TARGET_BIG_ENDIAN) {
dp += (fieldsz + offset) >> LOG_TGTAU_BITS;
direction = -1;
} else
direction = 1;
objval = *dp >> offset;
shift = TGTAU_BITS - offset;
while (shift <= fieldsz) {
dp += direction;
objval += (rvalue) *dp << shift;
shift += TGTAU_BITS;
}
/* * sign or zero extend the value appropriately */
if (sgn == ROP_UNS)
objval &= (2 << fieldsz) - 1;
else {
shift = sizeof(rvalue) * BITS_PER_AU - 1 - fieldsz;
objval = (objval << shift) >> shift;
}
return objval;
} /* dload_unpack */
/**************************************************************************
* Procedure dload_repack
*
* Parameters:
* val Value to insert
* data Pointer to storage unit containing lowest host address of
* image data
* fieldsz Size of bit field, 0 < fieldsz <= sizeof(rvalue)*BITS_PER_AU
* offset Offset from LSB, 0 <= offset < BITS_PER_AU
* sgn Signedness of the field (ROP_SGN, ROP_UNS, ROP_MAX, ROP_ANY)
*
* Effect:
* Stuffs the specified value in the specified field. Returns 0 for
* success
* or 1 if the value will not fit in the specified field according to the
* specified signedness rule.
************************************************************************* */
static const unsigned char ovf_limit[] = { 1, 2, 2 };
int dload_repack(struct dload_state *dlthis, rvalue val, tgt_au_t *data,
int fieldsz, int offset, unsigned sgn)
{
register urvalue objval, mask;
register int shift, direction;
register tgt_au_t *dp = data;
fieldsz -= 1; /* avoid nastiness with 32-bit shift of 32-bit value */
/* clip the bits */
mask = (2UL << fieldsz) - 1;
objval = (val & mask);
/* * store the bits through the specified mask */
if (TARGET_BIG_ENDIAN) {
dp += (fieldsz + offset) >> LOG_TGTAU_BITS;
direction = -1;
} else
direction = 1;
/* insert LSBs */
*dp = (*dp & ~(mask << offset)) + (objval << offset);
shift = TGTAU_BITS - offset;
/* align mask and objval with AU boundary */
objval >>= shift;
mask >>= shift;
while (mask) {
dp += direction;
*dp = (*dp & ~mask) + objval;
objval >>= TGTAU_BITS;
mask >>= TGTAU_BITS;
}
/*
* check for overflow
*/
if (sgn) {
unsigned tmp = (val >> fieldsz) + (sgn & 0x1);
if (tmp > ovf_limit[sgn - 1])
return 1;
}
return 0;
} /* dload_repack */
/* lookup table for the scaling amount in a C6x instruction */
#if TMS32060
#define SCALE_BITS 4 /* there are 4 bits in the scale field */
#define SCALE_MASK 0x7 /* we really only use the bottom 3 bits */
static const u8 c60_scale[SCALE_MASK + 1] = {
1, 0, 0, 0, 1, 1, 2, 2
};
#endif
/**************************************************************************
* Procedure dload_relocate
*
* Parameters:
* data Pointer to base of image data
* rp Pointer to relocation operation
*
* Effect:
* Performs the specified relocation operation
************************************************************************* */
void dload_relocate(struct dload_state *dlthis, tgt_au_t *data,
struct reloc_record_t *rp, bool *tramps_generated,
bool second_pass)
{
rvalue val, reloc_amt, orig_val = 0;
unsigned int fieldsz = 0;
unsigned int offset = 0;
unsigned int reloc_info = 0;
unsigned int reloc_action = 0;
register int rx = 0;
rvalue *stackp = NULL;
int top;
struct local_symbol *svp = NULL;
#ifdef RFV_SCALE
unsigned int scale = 0;
#endif
struct image_packet_t *img_pkt = NULL;
/* The image packet data struct is only used during first pass
* relocation in the event that a trampoline is needed. 2nd pass
* relocation doesn't guarantee that data is coming from an
* image_packet_t structure. See cload.c, dload_data for how img_data is
* set. If that changes this needs to be updated!!! */
if (second_pass == false)
img_pkt = (struct image_packet_t *)((u8 *) data -
sizeof(struct
image_packet_t));
rx = HASH_FUNC(rp->TYPE);
while (rop_map1[rx] != rp->TYPE) {
rx = HASH_L(rop_map2[rx]);
if (rx < 0) {
#if TMS32060
switch (rp->TYPE) {
case R_C60ALIGN:
case R_C60NOCMP:
case R_C60FPHEAD:
/* Ignore these reloc types and return */
break;
default:
/* Unknown reloc type, print error and return */
dload_error(dlthis, "Bad coff operator 0x%x",
rp->TYPE);
}
#else
dload_error(dlthis, "Bad coff operator 0x%x", rp->TYPE);
#endif
return;
}
}
rx = HASH_I(rop_map2[rx]);
if ((rx < (sizeof(rop_action) / sizeof(u16)))
&& (rx < (sizeof(rop_info) / sizeof(u16))) && (rx > 0)) {
reloc_action = rop_action[rx];
reloc_info = rop_info[rx];
} else {
dload_error(dlthis, "Buffer Overflow - Array Index Out "
"of Bounds");
}
/* Compute the relocation amount for the referenced symbol, if any */
reloc_amt = rp->UVAL;
if (RFV_SYM(reloc_info)) { /* relocation uses a symbol reference */
/* If this is first pass, use the module local symbol table,
* else use the trampoline symbol table. */
if (second_pass == false) {
if ((u32) rp->SYMNDX < dlthis->dfile_hdr.df_no_syms) {
/* real symbol reference */
svp = &dlthis->local_symtab[rp->SYMNDX];
reloc_amt = (RFV_SYM(reloc_info) == ROP_SYMD) ?
svp->delta : svp->value;
}
/* reloc references current section */
else if (rp->SYMNDX == -1) {
reloc_amt = (RFV_SYM(reloc_info) == ROP_SYMD) ?
dlthis->delta_runaddr :
dlthis->image_secn->run_addr;
}
}
}
/* relocation uses a symbol reference */
/* Handle stack adjustment */
val = 0;
top = RFV_STK(reloc_info);
if (top) {
top += dlthis->relstkidx - RSTK_UOP;
if (top >= STATIC_EXPR_STK_SIZE) {
dload_error(dlthis,
"Expression stack overflow in %s at offset "
FMT_UI32, dlthis->image_secn->name,
rp->vaddr + dlthis->image_offset);
return;
}
val = dlthis->relstk[dlthis->relstkidx];
dlthis->relstkidx = top;
stackp = &dlthis->relstk[top];
}
/* Derive field position and size, if we need them */
if (reloc_info & ROP_RW) { /* read or write action in our future */
fieldsz = RFV_WIDTH(reloc_action);
if (fieldsz) { /* field info from table */
offset = RFV_POSN(reloc_action);
if (TARGET_BIG_ENDIAN)
/* make sure vaddr is the lowest target
* address containing bits */
rp->vaddr += RFV_BIGOFF(reloc_info);
} else { /* field info from relocation op */
fieldsz = rp->FIELDSZ;
offset = rp->OFFSET;
if (TARGET_BIG_ENDIAN)
/* make sure vaddr is the lowest target
address containing bits */
rp->vaddr += (rp->WORDSZ - offset - fieldsz)
>> LOG_TARGET_AU_BITS;
}
data = (tgt_au_t *) ((char *)data + TADDR_TO_HOST(rp->vaddr));
/* compute lowest host location of referenced data */
#if BITS_PER_AU > TARGET_AU_BITS
/* conversion from target address to host address may lose
address bits; add loss to offset */
if (TARGET_BIG_ENDIAN) {
offset += -((rp->vaddr << LOG_TARGET_AU_BITS) +
offset + fieldsz) &
(BITS_PER_AU - TARGET_AU_BITS);
} else {
offset += (rp->vaddr << LOG_TARGET_AU_BITS) &
(BITS_PER_AU - 1);
}
#endif
#ifdef RFV_SCALE
scale = RFV_SCALE(reloc_info);
#endif
}
/* read the object value from the current image, if so ordered */
if (reloc_info & ROP_R) {
/* relocation reads current image value */
val = dload_unpack(dlthis, data, fieldsz, offset,
RFV_SIGN(reloc_info));
/* Save off the original value in case the relo overflows and
* we can trampoline it. */
orig_val = val;
#ifdef RFV_SCALE
val <<= scale;
#endif
}
/* perform the necessary arithmetic */
switch (RFV_ACTION(reloc_action)) { /* relocation actions */
case RACT_VAL:
break;
case RACT_ASGN:
val = reloc_amt;
break;
case RACT_ADD:
val += reloc_amt;
break;
case RACT_PCR:
/*-----------------------------------------------------------
* Handle special cases of jumping from absolute sections
* (special reloc type) or to absolute destination
* (symndx == -1). In either case, set the appropriate
* relocation amount to 0.
*----------------------------------------------------------- */
if (rp->SYMNDX == -1)
reloc_amt = 0;
val += reloc_amt - dlthis->delta_runaddr;
break;
case RACT_ADDISP:
val += rp->R_DISP + reloc_amt;
break;
case RACT_ASGPC:
val = dlthis->image_secn->run_addr + reloc_amt;
break;
case RACT_PLUS:
if (stackp != NULL)
val += *stackp;
break;
case RACT_SUB:
if (stackp != NULL)
val = *stackp - val;
break;
case RACT_NEG:
val = -val;
break;
case RACT_MPY:
if (stackp != NULL)
val *= *stackp;
break;
case RACT_DIV:
if (stackp != NULL)
val = *stackp / val;
break;
case RACT_MOD:
if (stackp != NULL)
val = *stackp % val;
break;
case RACT_SR:
if (val >= sizeof(rvalue) * BITS_PER_AU)
val = 0;
else if (stackp != NULL)
val = (urvalue) *stackp >> val;
break;
case RACT_ASR:
if (val >= sizeof(rvalue) * BITS_PER_AU)
val = sizeof(rvalue) * BITS_PER_AU - 1;
else if (stackp != NULL)
val = *stackp >> val;
break;
case RACT_SL:
if (val >= sizeof(rvalue) * BITS_PER_AU)
val = 0;
else if (stackp != NULL)
val = *stackp << val;
break;
case RACT_AND:
if (stackp != NULL)
val &= *stackp;
break;
case RACT_OR:
if (stackp != NULL)
val |= *stackp;
break;
case RACT_XOR:
if (stackp != NULL)
val ^= *stackp;
break;
case RACT_NOT:
val = ~val;
break;
#if TMS32060
case RACT_C6SECT:
/* actually needed address of secn containing symbol */
if (svp != NULL) {
if (rp->SYMNDX >= 0)
if (svp->secnn > 0)
reloc_amt = dlthis->ldr_sections
[svp->secnn - 1].run_addr;
}
/* !!! FALL THRU !!! */
case RACT_C6BASE:
if (dlthis->bss_run_base == 0) {
struct dynload_symbol *symp;
symp = dlthis->mysym->find_matching_symbol
(dlthis->mysym, bsssymbol);
/* lookup value of global BSS base */
if (symp)
dlthis->bss_run_base = symp->value;
else
dload_error(dlthis,
"Global BSS base referenced in %s "
"offset" FMT_UI32 " but not "
"defined",
dlthis->image_secn->name,
rp->vaddr + dlthis->image_offset);
}
reloc_amt -= dlthis->bss_run_base;
/* !!! FALL THRU !!! */
case RACT_C6DSPL:
/* scale factor determined by 3 LSBs of field */
scale = c60_scale[val & SCALE_MASK];
offset += SCALE_BITS;
fieldsz -= SCALE_BITS;
val >>= SCALE_BITS; /* ignore the scale field hereafter */
val <<= scale;
val += reloc_amt; /* do the usual relocation */
if (((1 << scale) - 1) & val)
dload_error(dlthis,
"Unaligned reference in %s offset "
FMT_UI32, dlthis->image_secn->name,
rp->vaddr + dlthis->image_offset);
break;
#endif
} /* relocation actions */
/* * Put back result as required */
if (reloc_info & ROP_W) { /* relocation writes image value */
#ifdef RFV_SCALE
val >>= scale;
#endif
if (dload_repack(dlthis, val, data, fieldsz, offset,
RFV_SIGN(reloc_info))) {
/* Check to see if this relo can be trampolined,
* but only in first phase relocation. 2nd phase
* relocation cannot trampoline. */
if ((second_pass == false) &&
(dload_tramp_avail(dlthis, rp) == true)) {
/* Before generating the trampoline, restore
* the value to its original so the 2nd pass
* relo will work. */
dload_repack(dlthis, orig_val, data, fieldsz,
offset, RFV_SIGN(reloc_info));
if (!dload_tramp_generate(dlthis,
(dlthis->image_secn -
dlthis->ldr_sections),
dlthis->image_offset,
img_pkt, rp)) {
dload_error(dlthis,
"Failed to "
"generate trampoline for "
"bit overflow");
dload_error(dlthis,
"Relocation val " FMT_UI32
" overflows %d bits in %s "
"offset " FMT_UI32, val,
fieldsz,
dlthis->image_secn->name,
dlthis->image_offset +
rp->vaddr);
} else
*tramps_generated = true;
} else {
dload_error(dlthis, "Relocation value "
FMT_UI32 " overflows %d bits in %s"
" offset " FMT_UI32, val, fieldsz,
dlthis->image_secn->name,
dlthis->image_offset + rp->vaddr);
}
}
} else if (top)
*stackp = val;
} /* reloc_value */

102
drivers/staging/tidspbridge/dynload/reloc_table.h
View File

@ -1,102 +0,0 @@
/*
* reloc_table.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef _RELOC_TABLE_H_
#define _RELOC_TABLE_H_
/*
* Table of relocation operator properties
*/
#include <linux/types.h>
/* How does this relocation operation access the program image? */
#define ROP_N 0 /* does not access image */
#define ROP_R 1 /* read from image */
#define ROP_W 2 /* write to image */
#define ROP_RW 3 /* read from and write to image */
/* For program image access, what are the overflow rules for the bit field? */
/* Beware! Procedure repack depends on this encoding */
#define ROP_ANY 0 /* no overflow ever, just truncate the value */
#define ROP_SGN 1 /* signed field */
#define ROP_UNS 2 /* unsigned field */
#define ROP_MAX 3 /* allow maximum range of either signed or unsigned */
/* How does the relocation operation use the symbol reference */
#define ROP_IGN 0 /* no symbol is referenced */
#define ROP_LIT 0 /* use rp->UVAL literal field */
#define ROP_SYM 1 /* symbol value is used in relocation */
#define ROP_SYMD 2 /* delta value vs last link is used */
/* How does the reloc op use the stack? */
#define RSTK_N 0 /* Does not use */
#define RSTK_POP 1 /* Does a POP */
#define RSTK_UOP 2 /* Unary op, stack position unaffected */
#define RSTK_PSH 3 /* Does a push */
/*
* Computational actions performed by the dynamic loader
*/
enum dload_actions {
/* don't alter the current val (from stack or mem fetch) */
RACT_VAL,
/* set value to reference amount (from symbol reference) */
RACT_ASGN,
RACT_ADD, /* add reference to value */
RACT_PCR, /* add reference minus PC delta to value */
RACT_ADDISP, /* add reference plus R_DISP */
RACT_ASGPC, /* set value to section addr plus reference */
RACT_PLUS, /* stack + */
RACT_SUB, /* stack - */
RACT_NEG, /* stack unary - */
RACT_MPY, /* stack * */
RACT_DIV, /* stack / */
RACT_MOD, /* stack % */
RACT_SR, /* stack unsigned >> */
RACT_ASR, /* stack signed >> */
RACT_SL, /* stack << */
RACT_AND, /* stack & */
RACT_OR, /* stack | */
RACT_XOR, /* stack ^ */
RACT_NOT, /* stack ~ */
RACT_C6SECT, /* for C60 R_SECT op */
RACT_C6BASE, /* for C60 R_BASE op */
RACT_C6DSPL, /* for C60 scaled 15-bit displacement */
RACT_PCR23T /* for ARM Thumb long branch */
};
/*
* macros used to extract values
*/
#define RFV_POSN(aaa) ((aaa) & 0xF)
#define RFV_WIDTH(aaa) (((aaa) >> 4) & 0x3F)
#define RFV_ACTION(aaa) ((aaa) >> 10)
#define RFV_SIGN(iii) (((iii) >> 2) & 0x3)
#define RFV_SYM(iii) (((iii) >> 4) & 0x3)
#define RFV_STK(iii) (((iii) >> 6) & 0x3)
#define RFV_ACCS(iii) ((iii) & 0x3)
#if (TMS32060)
#define RFV_SCALE(iii) ((iii) >> 11)
#define RFV_BIGOFF(iii) (((iii) >> 8) & 0x7)
#else
#define RFV_BIGOFF(iii) ((iii) >> 8)
#endif
#endif /* _RELOC_TABLE_H_ */

257
drivers/staging/tidspbridge/dynload/reloc_table_c6000.c
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@ -1,257 +0,0 @@
/*
* reloc_table_c6000.c
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
/* Tables generated for c6000 */
#define HASH_FUNC(zz) (((((zz) + 1) * 1845UL) >> 11) & 63)
#define HASH_L(zz) ((zz) >> 8)
#define HASH_I(zz) ((zz) & 0xFF)
static const u16 rop_map1[] = {
0,
1,
2,
20,
4,
5,
6,
15,
80,
81,
82,
83,
84,
85,
86,
87,
17,
18,
19,
21,
16,
16394,
16404,
65535,
65535,
65535,
65535,
65535,
65535,
32,
65535,
65535,
65535,
65535,
65535,
65535,
40,
112,
113,
65535,
16384,
16385,
16386,
16387,
16388,
16389,
16390,
16391,
16392,
16393,
16395,
16396,
16397,
16398,
16399,
16400,
16401,
16402,
16403,
16405,
16406,
65535,
65535,
65535
};
static const s16 rop_map2[] = {
-256,
-255,
-254,
-245,
-253,
-252,
-251,
-250,
-241,
-240,
-239,
-238,
-237,
-236,
1813,
5142,
-248,
-247,
778,
-244,
-249,
-221,
-211,
-1,
-1,
-1,
-1,
-1,
-1,
-243,
-1,
-1,
-1,
-1,
-1,
-1,
-242,
-233,
-232,
-1,
-231,
-230,
-229,
-228,
-227,
-226,
-225,
-224,
-223,
5410,
-220,
-219,
-218,
-217,
-216,
-215,
-214,
-213,
5676,
-210,
-209,
-1,
-1,
-1
};
static const u16 rop_action[] = {
2560,
2304,
2304,
2432,
2432,
2560,
2176,
2304,
2560,
3200,
3328,
3584,
3456,
2304,
4208,
20788,
21812,
3415,
3245,
2311,
4359,
19764,
2311,
3191,
3280,
6656,
7680,
8704,
9728,
10752,
11776,
12800,
13824,
14848,
15872,
16896,
17920,
18944,
0,
0,
0,
0,
1536,
1536,
1536,
5632,
512,
0
};
static const u16 rop_info[] = {
0,
35,
35,
35,
35,
35,
35,
35,
35,
39,
39,
39,
39,
35,
34,
283,
299,
4135,
4391,
291,
33059,
283,
295,
4647,
4135,
64,
64,
128,
64,
64,
64,
64,
64,
64,
64,
64,
64,
128,
201,
197,
74,
70,
208,
196,
200,
192,
192,
66
};

1143
drivers/staging/tidspbridge/dynload/tramp.c
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File diff suppressed because it is too large Load Diff

164
drivers/staging/tidspbridge/dynload/tramp_table_c6000.c
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@ -1,164 +0,0 @@
/*
* tramp_table_c6000.c
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#include "dload_internal.h"
/* These are defined in coff.h, but may not be available on all platforms
so we'll go ahead and define them here. */
#ifndef R_C60LO16
#define R_C60LO16 0x54 /* C60: MVK Low Half Register */
#define R_C60HI16 0x55 /* C60: MVKH/MVKLH High Half Register */
#endif
#define C6X_TRAMP_WORD_COUNT 8
#define C6X_TRAMP_MAX_RELOS 8
/* THIS HASH FUNCTION MUST MATCH THE ONE reloc_table_c6000.c */
#define HASH_FUNC(zz) (((((zz) + 1) * 1845UL) >> 11) & 63)
/* THIS MUST MATCH reloc_record_t FOR A SYMBOL BASED RELO */
struct c6000_relo_record {
s32 vaddr;
s32 symndx;
#ifndef _BIG_ENDIAN
u16 disp;
u16 type;
#else
u16 type;
u16 disp;
#endif
};
struct c6000_gen_code {
struct tramp_gen_code_hdr hdr;
u32 tramp_instrs[C6X_TRAMP_WORD_COUNT];
struct c6000_relo_record relos[C6X_TRAMP_MAX_RELOS];
};
/* Hash mapping for relos that can cause trampolines. */
static const u16 tramp_map[] = {
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
0,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535
};
static const struct c6000_gen_code tramp_gen_info[] = {
/* Tramp caused by R_C60PCR21 */
{
/* Header - 8 instructions, 2 relos */
{
sizeof(u32) * C6X_TRAMP_WORD_COUNT,
2,
FIELD_OFFSET(struct c6000_gen_code, relos)
},
/* Trampoline instructions */
{
0x053C54F7, /* STW.D2T2 B10, *sp--[2] */
0x0500002A, /* || MVK.S2 <blank>, B10 */
0x0500006A, /* MVKH.S2 <blank>, B10 */
0x00280362, /* B.S2 B10 */
0x053C52E6, /* LDW.D2T2 *++sp[2], B10 */
0x00006000, /* NOP 4 */
0x00000000, /* NOP */
0x00000000 /* NOP */
},
/* Relocations */
{
{4, 0, 0, R_C60LO16},
{8, 0, 0, R_C60HI16},
{0, 0, 0, 0x0000},
{0, 0, 0, 0x0000},
{0, 0, 0, 0x0000},
{0, 0, 0, 0x0000},
{0, 0, 0, 0x0000},
{0, 0, 0, 0x0000}
}
}
};
/* TARGET SPECIFIC FUNCTIONS THAT MUST BE DEFINED */
static u32 tramp_size_get(void)
{
return sizeof(u32) * C6X_TRAMP_WORD_COUNT;
}
static u32 tramp_img_pkt_size_get(void)
{
return sizeof(struct c6000_gen_code);
}

141
drivers/staging/tidspbridge/gen/gh.c
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@ -1,141 +0,0 @@
/*
* gh.c
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#include <linux/err.h>
#include <linux/hashtable.h>
#include <linux/slab.h>
struct gh_node {
struct hlist_node hl;
u8 data[0];
};
#define GH_HASH_ORDER 8
struct gh_t_hash_tab {
u32 val_size;
DECLARE_HASHTABLE(hash_table, GH_HASH_ORDER);
u32 (*hash)(const void *key);
bool (*match)(const void *key, const void *value);
void (*delete)(void *key);
};
/*
* ======== gh_create ========
*/
struct gh_t_hash_tab *gh_create(u32 val_size, u32 (*hash)(const void *),
bool (*match)(const void *, const void *),
void (*delete)(void *))
{
struct gh_t_hash_tab *hash_tab;
hash_tab = kzalloc(sizeof(struct gh_t_hash_tab), GFP_KERNEL);
if (!hash_tab)
return ERR_PTR(-ENOMEM);
hash_init(hash_tab->hash_table);
hash_tab->val_size = val_size;
hash_tab->hash = hash;
hash_tab->match = match;
hash_tab->delete = delete;
return hash_tab;
}
/*
* ======== gh_delete ========
*/
void gh_delete(struct gh_t_hash_tab *hash_tab)
{
struct gh_node *n;
struct hlist_node *tmp;
u32 i;
if (hash_tab) {
hash_for_each_safe(hash_tab->hash_table, i, tmp, n, hl) {
hash_del(&n->hl);
if (hash_tab->delete)
hash_tab->delete(n->data);
kfree(n);
}
kfree(hash_tab);
}
}
/*
* ======== gh_find ========
*/
void *gh_find(struct gh_t_hash_tab *hash_tab, const void *key)
{
struct gh_node *n;
u32 key_hash = hash_tab->hash(key);
hash_for_each_possible(hash_tab->hash_table, n, hl, key_hash) {
if (hash_tab->match(key, n->data))
return n->data;
}
return ERR_PTR(-ENODATA);
}
/*
* ======== gh_insert ========
*/
void *gh_insert(struct gh_t_hash_tab *hash_tab, const void *key,
const void *value)
{
struct gh_node *n;
n = kmalloc(sizeof(struct gh_node) + hash_tab->val_size,
GFP_KERNEL);
if (!n)
return ERR_PTR(-ENOMEM);
INIT_HLIST_NODE(&n->hl);
hash_add(hash_tab->hash_table, &n->hl, hash_tab->hash(key));
memcpy(n->data, value, hash_tab->val_size);
return n->data;
}
#ifdef CONFIG_TIDSPBRIDGE_BACKTRACE
/**
* gh_iterate() - This function goes through all the elements in the hash table
* looking for the dsp symbols.
* @hash_tab: Hash table
* @callback: pointer to callback function
* @user_data: User data, contains the find_symbol_context pointer
*
*/
void gh_iterate(struct gh_t_hash_tab *hash_tab,
void (*callback)(void *, void *), void *user_data)
{
struct gh_node *n;
u32 i;
if (!hash_tab)
return;
hash_for_each(hash_tab->hash_table, i, n, hl)
callback(&n->data, user_data);
}
#endif

41
drivers/staging/tidspbridge/hw/EasiGlobal.h
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@ -1,41 +0,0 @@
/*
* EasiGlobal.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Copyright (C) 2007 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef _EASIGLOBAL_H
#define _EASIGLOBAL_H
#include <linux/types.h>
/*
* DEFINE: READ_ONLY, WRITE_ONLY & READ_WRITE
*
* DESCRIPTION: Defines used to describe register types for EASI-checker tests.
*/
#define READ_ONLY 1
#define WRITE_ONLY 2
#define READ_WRITE 3
/*
* MACRO: _DEBUG_LEVEL1_EASI
*
* DESCRIPTION: A MACRO which can be used to indicate that a particular beach
* register access function was called.
*
* NOTE: We currently dont use this functionality.
*/
#define _DEBUG_LEVEL1_EASI(easi_num) ((void)0)
#endif /* _EASIGLOBAL_H */

76
drivers/staging/tidspbridge/hw/MMUAccInt.h
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@ -1,76 +0,0 @@
/*
* MMUAccInt.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Copyright (C) 2007 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef _MMU_ACC_INT_H
#define _MMU_ACC_INT_H
/* Mappings of level 1 EASI function numbers to function names */
#define EASIL1_MMUMMU_SYSCONFIG_READ_REGISTER32 (MMU_BASE_EASIL1 + 3)
#define EASIL1_MMUMMU_SYSCONFIG_IDLE_MODE_WRITE32 (MMU_BASE_EASIL1 + 17)
#define EASIL1_MMUMMU_SYSCONFIG_AUTO_IDLE_WRITE32 (MMU_BASE_EASIL1 + 39)
#define EASIL1_MMUMMU_IRQSTATUS_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 51)
#define EASIL1_MMUMMU_IRQENABLE_READ_REGISTER32 (MMU_BASE_EASIL1 + 102)
#define EASIL1_MMUMMU_IRQENABLE_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 103)
#define EASIL1_MMUMMU_WALKING_STTWL_RUNNING_READ32 (MMU_BASE_EASIL1 + 156)
#define EASIL1_MMUMMU_CNTLTWL_ENABLE_READ32 (MMU_BASE_EASIL1 + 174)
#define EASIL1_MMUMMU_CNTLTWL_ENABLE_WRITE32 (MMU_BASE_EASIL1 + 180)
#define EASIL1_MMUMMU_CNTLMMU_ENABLE_WRITE32 (MMU_BASE_EASIL1 + 190)
#define EASIL1_MMUMMU_FAULT_AD_READ_REGISTER32 (MMU_BASE_EASIL1 + 194)
#define EASIL1_MMUMMU_TTB_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 198)
#define EASIL1_MMUMMU_LOCK_READ_REGISTER32 (MMU_BASE_EASIL1 + 203)
#define EASIL1_MMUMMU_LOCK_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 204)
#define EASIL1_MMUMMU_LOCK_BASE_VALUE_READ32 (MMU_BASE_EASIL1 + 205)
#define EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_READ32 (MMU_BASE_EASIL1 + 209)
#define EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_WRITE32 (MMU_BASE_EASIL1 + 211)
#define EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_SET32 (MMU_BASE_EASIL1 + 212)
#define EASIL1_MMUMMU_LD_TLB_READ_REGISTER32 (MMU_BASE_EASIL1 + 213)
#define EASIL1_MMUMMU_LD_TLB_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 214)
#define EASIL1_MMUMMU_CAM_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 226)
#define EASIL1_MMUMMU_RAM_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 268)
#define EASIL1_MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 322)
/* Register offset address definitions */
#define MMU_MMU_SYSCONFIG_OFFSET 0x10
#define MMU_MMU_IRQSTATUS_OFFSET 0x18
#define MMU_MMU_IRQENABLE_OFFSET 0x1c
#define MMU_MMU_WALKING_ST_OFFSET 0x40
#define MMU_MMU_CNTL_OFFSET 0x44
#define MMU_MMU_FAULT_AD_OFFSET 0x48
#define MMU_MMU_TTB_OFFSET 0x4c
#define MMU_MMU_LOCK_OFFSET 0x50
#define MMU_MMU_LD_TLB_OFFSET 0x54
#define MMU_MMU_CAM_OFFSET 0x58
#define MMU_MMU_RAM_OFFSET 0x5c
#define MMU_MMU_GFLUSH_OFFSET 0x60
#define MMU_MMU_FLUSH_ENTRY_OFFSET 0x64
/* Bitfield mask and offset declarations */
#define MMU_MMU_SYSCONFIG_IDLE_MODE_MASK 0x18
#define MMU_MMU_SYSCONFIG_IDLE_MODE_OFFSET 3
#define MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK 0x1
#define MMU_MMU_SYSCONFIG_AUTO_IDLE_OFFSET 0
#define MMU_MMU_WALKING_ST_TWL_RUNNING_MASK 0x1
#define MMU_MMU_WALKING_ST_TWL_RUNNING_OFFSET 0
#define MMU_MMU_CNTL_TWL_ENABLE_MASK 0x4
#define MMU_MMU_CNTL_TWL_ENABLE_OFFSET 2
#define MMU_MMU_CNTL_MMU_ENABLE_MASK 0x2
#define MMU_MMU_CNTL_MMU_ENABLE_OFFSET 1
#define MMU_MMU_LOCK_BASE_VALUE_MASK 0xfc00
#define MMU_MMU_LOCK_BASE_VALUE_OFFSET 10
#define MMU_MMU_LOCK_CURRENT_VICTIM_MASK 0x3f0
#define MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET 4
#endif /* _MMU_ACC_INT_H */

225
drivers/staging/tidspbridge/hw/MMURegAcM.h
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@ -1,225 +0,0 @@
/*
* MMURegAcM.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Copyright (C) 2007 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef _MMU_REG_ACM_H
#define _MMU_REG_ACM_H
#include <linux/io.h>
#include <EasiGlobal.h>
#include "MMUAccInt.h"
#if defined(USE_LEVEL_1_MACROS)
#define MMUMMU_SYSCONFIG_READ_REGISTER32(base_address)\
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_SYSCONFIG_READ_REGISTER32),\
__raw_readl((base_address)+MMU_MMU_SYSCONFIG_OFFSET))
#define MMUMMU_SYSCONFIG_IDLE_MODE_WRITE32(base_address, value)\
{\
const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\
register u32 data = __raw_readl((base_address)+offset);\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_SYSCONFIG_IDLE_MODE_WRITE32);\
data &= ~(MMU_MMU_SYSCONFIG_IDLE_MODE_MASK);\
new_value <<= MMU_MMU_SYSCONFIG_IDLE_MODE_OFFSET;\
new_value &= MMU_MMU_SYSCONFIG_IDLE_MODE_MASK;\
new_value |= data;\
__raw_writel(new_value, base_address+offset);\
}
#define MMUMMU_SYSCONFIG_AUTO_IDLE_WRITE32(base_address, value)\
{\
const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\
register u32 data = __raw_readl((base_address)+offset);\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_SYSCONFIG_AUTO_IDLE_WRITE32);\
data &= ~(MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK);\
new_value <<= MMU_MMU_SYSCONFIG_AUTO_IDLE_OFFSET;\
new_value &= MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK;\
new_value |= data;\
__raw_writel(new_value, base_address+offset);\
}
#define MMUMMU_IRQSTATUS_READ_REGISTER32(base_address)\
(_DEBUG_LEVEL1_EASI(easil1_mmummu_irqstatus_read_register32),\
__raw_readl((base_address)+MMU_MMU_IRQSTATUS_OFFSET))
#define MMUMMU_IRQSTATUS_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_IRQSTATUS_OFFSET;\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQSTATUS_WRITE_REGISTER32);\
__raw_writel(new_value, (base_address)+offset);\
}
#define MMUMMU_IRQENABLE_READ_REGISTER32(base_address)\
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQENABLE_READ_REGISTER32),\
__raw_readl((base_address)+MMU_MMU_IRQENABLE_OFFSET))
#define MMUMMU_IRQENABLE_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQENABLE_WRITE_REGISTER32);\
__raw_writel(new_value, (base_address)+offset);\
}
#define MMUMMU_WALKING_STTWL_RUNNING_READ32(base_address)\
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_WALKING_STTWL_RUNNING_READ32),\
(((__raw_readl(((base_address)+(MMU_MMU_WALKING_ST_OFFSET))))\
& MMU_MMU_WALKING_ST_TWL_RUNNING_MASK) >>\
MMU_MMU_WALKING_ST_TWL_RUNNING_OFFSET))
#define MMUMMU_CNTLTWL_ENABLE_READ32(base_address)\
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CNTLTWL_ENABLE_READ32),\
(((__raw_readl(((base_address)+(MMU_MMU_CNTL_OFFSET)))) &\
MMU_MMU_CNTL_TWL_ENABLE_MASK) >>\
MMU_MMU_CNTL_TWL_ENABLE_OFFSET))
#define MMUMMU_CNTLTWL_ENABLE_WRITE32(base_address, value)\
{\
const u32 offset = MMU_MMU_CNTL_OFFSET;\
register u32 data = __raw_readl((base_address)+offset);\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CNTLTWL_ENABLE_WRITE32);\
data &= ~(MMU_MMU_CNTL_TWL_ENABLE_MASK);\
new_value <<= MMU_MMU_CNTL_TWL_ENABLE_OFFSET;\
new_value &= MMU_MMU_CNTL_TWL_ENABLE_MASK;\
new_value |= data;\
__raw_writel(new_value, base_address+offset);\
}
#define MMUMMU_CNTLMMU_ENABLE_WRITE32(base_address, value)\
{\
const u32 offset = MMU_MMU_CNTL_OFFSET;\
register u32 data = __raw_readl((base_address)+offset);\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CNTLMMU_ENABLE_WRITE32);\
data &= ~(MMU_MMU_CNTL_MMU_ENABLE_MASK);\
new_value <<= MMU_MMU_CNTL_MMU_ENABLE_OFFSET;\
new_value &= MMU_MMU_CNTL_MMU_ENABLE_MASK;\
new_value |= data;\
__raw_writel(new_value, base_address+offset);\
}
#define MMUMMU_FAULT_AD_READ_REGISTER32(base_address)\
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_FAULT_AD_READ_REGISTER32),\
__raw_readl((base_address)+MMU_MMU_FAULT_AD_OFFSET))
#define MMUMMU_TTB_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_TTB_OFFSET;\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_TTB_WRITE_REGISTER32);\
__raw_writel(new_value, (base_address)+offset);\
}
#define MMUMMU_LOCK_READ_REGISTER32(base_address)\
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_READ_REGISTER32),\
__raw_readl((base_address)+MMU_MMU_LOCK_OFFSET))
#define MMUMMU_LOCK_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_LOCK_OFFSET;\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_WRITE_REGISTER32);\
__raw_writel(new_value, (base_address)+offset);\
}
#define MMUMMU_LOCK_BASE_VALUE_READ32(base_address)\
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_BASE_VALUE_READ32),\
(((__raw_readl(((base_address)+(MMU_MMU_LOCK_OFFSET)))) &\
MMU_MMU_LOCK_BASE_VALUE_MASK) >>\
MMU_MMU_LOCK_BASE_VALUE_OFFSET))
#define MMUMMU_LOCK_BASE_VALUE_WRITE32(base_address, value)\
{\
const u32 offset = MMU_MMU_LOCK_OFFSET;\
register u32 data = __raw_readl((base_address)+offset);\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(easil1_mmummu_lock_base_value_write32);\
data &= ~(MMU_MMU_LOCK_BASE_VALUE_MASK);\
new_value <<= MMU_MMU_LOCK_BASE_VALUE_OFFSET;\
new_value &= MMU_MMU_LOCK_BASE_VALUE_MASK;\
new_value |= data;\
__raw_writel(new_value, base_address+offset);\
}
#define MMUMMU_LOCK_CURRENT_VICTIM_READ32(base_address)\
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_READ32),\
(((__raw_readl(((base_address)+(MMU_MMU_LOCK_OFFSET)))) &\
MMU_MMU_LOCK_CURRENT_VICTIM_MASK) >>\
MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET))
#define MMUMMU_LOCK_CURRENT_VICTIM_WRITE32(base_address, value)\
{\
const u32 offset = MMU_MMU_LOCK_OFFSET;\
register u32 data = __raw_readl((base_address)+offset);\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_WRITE32);\
data &= ~(MMU_MMU_LOCK_CURRENT_VICTIM_MASK);\
new_value <<= MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET;\
new_value &= MMU_MMU_LOCK_CURRENT_VICTIM_MASK;\
new_value |= data;\
__raw_writel(new_value, base_address+offset);\
}
#define MMUMMU_LOCK_CURRENT_VICTIM_SET32(var, value)\
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_SET32),\
(((var) & ~(MMU_MMU_LOCK_CURRENT_VICTIM_MASK)) |\
(((value) << MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET) &\
MMU_MMU_LOCK_CURRENT_VICTIM_MASK)))
#define MMUMMU_LD_TLB_READ_REGISTER32(base_address)\
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LD_TLB_READ_REGISTER32),\
__raw_readl((base_address)+MMU_MMU_LD_TLB_OFFSET))
#define MMUMMU_LD_TLB_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_LD_TLB_OFFSET;\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LD_TLB_WRITE_REGISTER32);\
__raw_writel(new_value, (base_address)+offset);\
}
#define MMUMMU_CAM_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_CAM_OFFSET;\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CAM_WRITE_REGISTER32);\
__raw_writel(new_value, (base_address)+offset);\
}
#define MMUMMU_RAM_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_RAM_OFFSET;\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_RAM_WRITE_REGISTER32);\
__raw_writel(new_value, (base_address)+offset);\
}
#define MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_FLUSH_ENTRY_OFFSET;\
register u32 new_value = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32);\
__raw_writel(new_value, (base_address)+offset);\
}
#endif /* USE_LEVEL_1_MACROS */
#endif /* _MMU_REG_ACM_H */

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drivers/staging/tidspbridge/hw/hw_defs.h
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@ -1,58 +0,0 @@
/*
* hw_defs.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Global HW definitions
*
* Copyright (C) 2007 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef _HW_DEFS_H
#define _HW_DEFS_H
/* Page size */
#define HW_PAGE_SIZE4KB 0x1000
#define HW_PAGE_SIZE64KB 0x10000
#define HW_PAGE_SIZE1MB 0x100000
#define HW_PAGE_SIZE16MB 0x1000000
/* hw_status: return type for HW API */
typedef long hw_status;
/* Macro used to set and clear any bit */
#define HW_CLEAR 0
#define HW_SET 1
/* hw_endianism_t: Enumerated Type used to specify the endianism
* Do NOT change these values. They are used as bit fields. */
enum hw_endianism_t {
HW_LITTLE_ENDIAN,
HW_BIG_ENDIAN
};
/* hw_element_size_t: Enumerated Type used to specify the element size
* Do NOT change these values. They are used as bit fields. */
enum hw_element_size_t {
HW_ELEM_SIZE8BIT,
HW_ELEM_SIZE16BIT,
HW_ELEM_SIZE32BIT,
HW_ELEM_SIZE64BIT
};
/* hw_idle_mode_t: Enumerated Type used to specify Idle modes */
enum hw_idle_mode_t {
HW_FORCE_IDLE,
HW_NO_IDLE,
HW_SMART_IDLE
};
#endif /* _HW_DEFS_H */

487
drivers/staging/tidspbridge/hw/hw_mmu.c
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@ -1,487 +0,0 @@
/*
* hw_mmu.c
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* API definitions to setup MMU TLB and PTE
*
* Copyright (C) 2007 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#include <linux/io.h>
#include "MMURegAcM.h"
#include <hw_defs.h>
#include <hw_mmu.h>
#include <linux/types.h>
#include <linux/err.h>
#define MMU_BASE_VAL_MASK 0xFC00
#define MMU_PAGE_MAX 3
#define MMU_ELEMENTSIZE_MAX 3
#define MMU_ADDR_MASK 0xFFFFF000
#define MMU_TTB_MASK 0xFFFFC000
#define MMU_SECTION_ADDR_MASK 0xFFF00000
#define MMU_SSECTION_ADDR_MASK 0xFF000000
#define MMU_PAGE_TABLE_MASK 0xFFFFFC00
#define MMU_LARGE_PAGE_MASK 0xFFFF0000
#define MMU_SMALL_PAGE_MASK 0xFFFFF000
#define MMU_LOAD_TLB 0x00000001
#define MMU_GFLUSH 0x60
/*
* hw_mmu_page_size_t: Enumerated Type used to specify the MMU Page Size(SLSS)
*/
enum hw_mmu_page_size_t {
HW_MMU_SECTION,
HW_MMU_LARGE_PAGE,
HW_MMU_SMALL_PAGE,
HW_MMU_SUPERSECTION
};
/*
* FUNCTION : mmu_set_cam_entry
*
* INPUTS:
*
* Identifier : base_address
* Type : void __iomem *
* Description : Base Address of instance of MMU module
*
* Identifier : page_sz
* TypE : const u32
* Description : It indicates the page size
*
* Identifier : preserved_bit
* Type : const u32
* Description : It indicates the TLB entry is preserved entry
* or not
*
* Identifier : valid_bit
* Type : const u32
* Description : It indicates the TLB entry is valid entry or not
*
*
* Identifier : virtual_addr_tag
* Type : const u32
* Description : virtual Address
*
* RETURNS:
*
* Type : hw_status
* Description : 0 -- No errors occurred
* RET_BAD_NULL_PARAM -- A Pointer Parameter
* was set to NULL
* RET_PARAM_OUT_OF_RANGE -- Input Parameter out
* of Range
*
* PURPOSE: : Set MMU_CAM reg
*
* METHOD: : Check the Input parameters and set the CAM entry.
*/
static hw_status mmu_set_cam_entry(void __iomem *base_address,
const u32 page_sz,
const u32 preserved_bit,
const u32 valid_bit,
const u32 virtual_addr_tag);
/*
* FUNCTION : mmu_set_ram_entry
*
* INPUTS:
*
* Identifier : base_address
* Type : void __iomem *
* Description : Base Address of instance of MMU module
*
* Identifier : physical_addr
* Type : const u32
* Description : Physical Address to which the corresponding
* virtual Address shouldpoint
*
* Identifier : endianism
* Type : hw_endianism_t
* Description : endianism for the given page
*
* Identifier : element_size
* Type : hw_element_size_t
* Description : The element size ( 8,16, 32 or 64 bit)
*
* Identifier : mixed_size
* Type : hw_mmu_mixed_size_t
* Description : Element Size to follow CPU or TLB
*
* RETURNS:
*
* Type : hw_status
* Description : 0 -- No errors occurred
* RET_BAD_NULL_PARAM -- A Pointer Parameter
* was set to NULL
* RET_PARAM_OUT_OF_RANGE -- Input Parameter
* out of Range
*
* PURPOSE: : Set MMU_CAM reg
*
* METHOD: : Check the Input parameters and set the RAM entry.
*/
static hw_status mmu_set_ram_entry(void __iomem *base_address,
const u32 physical_addr,
enum hw_endianism_t endianism,
enum hw_element_size_t element_size,
enum hw_mmu_mixed_size_t mixed_size);
/* HW FUNCTIONS */
hw_status hw_mmu_enable(void __iomem *base_address)
{
hw_status status = 0;
MMUMMU_CNTLMMU_ENABLE_WRITE32(base_address, HW_SET);
return status;
}
hw_status hw_mmu_disable(void __iomem *base_address)
{
hw_status status = 0;
MMUMMU_CNTLMMU_ENABLE_WRITE32(base_address, HW_CLEAR);
return status;
}
hw_status hw_mmu_num_locked_set(void __iomem *base_address,
u32 num_locked_entries)
{
hw_status status = 0;
MMUMMU_LOCK_BASE_VALUE_WRITE32(base_address, num_locked_entries);
return status;
}
hw_status hw_mmu_victim_num_set(void __iomem *base_address,
u32 victim_entry_num)
{
hw_status status = 0;
MMUMMU_LOCK_CURRENT_VICTIM_WRITE32(base_address, victim_entry_num);
return status;
}
hw_status hw_mmu_event_ack(void __iomem *base_address, u32 irq_mask)
{
hw_status status = 0;
MMUMMU_IRQSTATUS_WRITE_REGISTER32(base_address, irq_mask);
return status;
}
hw_status hw_mmu_event_disable(void __iomem *base_address, u32 irq_mask)
{
hw_status status = 0;
u32 irq_reg;
irq_reg = MMUMMU_IRQENABLE_READ_REGISTER32(base_address);
MMUMMU_IRQENABLE_WRITE_REGISTER32(base_address, irq_reg & ~irq_mask);
return status;
}
hw_status hw_mmu_event_enable(void __iomem *base_address, u32 irq_mask)
{
hw_status status = 0;
u32 irq_reg;
irq_reg = MMUMMU_IRQENABLE_READ_REGISTER32(base_address);
MMUMMU_IRQENABLE_WRITE_REGISTER32(base_address, irq_reg | irq_mask);
return status;
}
hw_status hw_mmu_event_status(void __iomem *base_address, u32 *irq_mask)
{
hw_status status = 0;
*irq_mask = MMUMMU_IRQSTATUS_READ_REGISTER32(base_address);
return status;
}
hw_status hw_mmu_fault_addr_read(void __iomem *base_address, u32 *addr)
{
hw_status status = 0;
/* read values from register */
*addr = MMUMMU_FAULT_AD_READ_REGISTER32(base_address);
return status;
}
hw_status hw_mmu_ttb_set(void __iomem *base_address, u32 ttb_phys_addr)
{
hw_status status = 0;
u32 load_ttb;
load_ttb = ttb_phys_addr & ~0x7FUL;
/* write values to register */
MMUMMU_TTB_WRITE_REGISTER32(base_address, load_ttb);
return status;
}
hw_status hw_mmu_twl_enable(void __iomem *base_address)
{
hw_status status = 0;
MMUMMU_CNTLTWL_ENABLE_WRITE32(base_address, HW_SET);
return status;
}
hw_status hw_mmu_twl_disable(void __iomem *base_address)
{
hw_status status = 0;
MMUMMU_CNTLTWL_ENABLE_WRITE32(base_address, HW_CLEAR);
return status;
}
hw_status hw_mmu_tlb_add(void __iomem *base_address,
u32 physical_addr,
u32 virtual_addr,
u32 page_sz,
u32 entry_num,
struct hw_mmu_map_attrs_t *map_attrs,
s8 preserved_bit, s8 valid_bit)
{
hw_status status = 0;
u32 lock_reg;
u32 virtual_addr_tag;
enum hw_mmu_page_size_t mmu_pg_size;
/*Check the input Parameters */
switch (page_sz) {
case HW_PAGE_SIZE4KB:
mmu_pg_size = HW_MMU_SMALL_PAGE;
break;
case HW_PAGE_SIZE64KB:
mmu_pg_size = HW_MMU_LARGE_PAGE;
break;
case HW_PAGE_SIZE1MB:
mmu_pg_size = HW_MMU_SECTION;
break;
case HW_PAGE_SIZE16MB:
mmu_pg_size = HW_MMU_SUPERSECTION;
break;
default:
return -EINVAL;
}
lock_reg = MMUMMU_LOCK_READ_REGISTER32(base_address);
/* Generate the 20-bit tag from virtual address */
virtual_addr_tag = ((virtual_addr & MMU_ADDR_MASK) >> 12);
/* Write the fields in the CAM Entry Register */
mmu_set_cam_entry(base_address, mmu_pg_size, preserved_bit, valid_bit,
virtual_addr_tag);
/* Write the different fields of the RAM Entry Register */
/* endianism of the page,Element Size of the page (8, 16, 32, 64 bit) */
mmu_set_ram_entry(base_address, physical_addr, map_attrs->endianism,
map_attrs->element_size, map_attrs->mixed_size);
/* Update the MMU Lock Register */
/* currentVictim between lockedBaseValue and (MMU_Entries_Number - 1) */
MMUMMU_LOCK_CURRENT_VICTIM_WRITE32(base_address, entry_num);
/* Enable loading of an entry in TLB by writing 1
into LD_TLB_REG register */
MMUMMU_LD_TLB_WRITE_REGISTER32(base_address, MMU_LOAD_TLB);
MMUMMU_LOCK_WRITE_REGISTER32(base_address, lock_reg);
return status;
}
hw_status hw_mmu_pte_set(const u32 pg_tbl_va,
u32 physical_addr,
u32 virtual_addr,
u32 page_sz, struct hw_mmu_map_attrs_t *map_attrs)
{
hw_status status = 0;
u32 pte_addr, pte_val;
s32 num_entries = 1;
switch (page_sz) {
case HW_PAGE_SIZE4KB:
pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va,
virtual_addr &
MMU_SMALL_PAGE_MASK);
pte_val =
((physical_addr & MMU_SMALL_PAGE_MASK) |
(map_attrs->endianism << 9) | (map_attrs->
element_size << 4) |
(map_attrs->mixed_size << 11) | 2);
break;
case HW_PAGE_SIZE64KB:
num_entries = 16;
pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va,
virtual_addr &
MMU_LARGE_PAGE_MASK);
pte_val =
((physical_addr & MMU_LARGE_PAGE_MASK) |
(map_attrs->endianism << 9) | (map_attrs->
element_size << 4) |
(map_attrs->mixed_size << 11) | 1);
break;
case HW_PAGE_SIZE1MB:
pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va,
virtual_addr &
MMU_SECTION_ADDR_MASK);
pte_val =
((((physical_addr & MMU_SECTION_ADDR_MASK) |
(map_attrs->endianism << 15) | (map_attrs->
element_size << 10) |
(map_attrs->mixed_size << 17)) & ~0x40000) | 0x2);
break;
case HW_PAGE_SIZE16MB:
num_entries = 16;
pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va,
virtual_addr &
MMU_SSECTION_ADDR_MASK);
pte_val =
(((physical_addr & MMU_SSECTION_ADDR_MASK) |
(map_attrs->endianism << 15) | (map_attrs->
element_size << 10) |
(map_attrs->mixed_size << 17)
) | 0x40000 | 0x2);
break;
case HW_MMU_COARSE_PAGE_SIZE:
pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va,
virtual_addr &
MMU_SECTION_ADDR_MASK);
pte_val = (physical_addr & MMU_PAGE_TABLE_MASK) | 1;
break;
default:
return -EINVAL;
}
while (--num_entries >= 0)
((u32 *) pte_addr)[num_entries] = pte_val;
return status;
}
hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, u32 virtual_addr, u32 page_size)
{
hw_status status = 0;
u32 pte_addr;
s32 num_entries = 1;
switch (page_size) {
case HW_PAGE_SIZE4KB:
pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va,
virtual_addr &
MMU_SMALL_PAGE_MASK);
break;
case HW_PAGE_SIZE64KB:
num_entries = 16;
pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va,
virtual_addr &
MMU_LARGE_PAGE_MASK);
break;
case HW_PAGE_SIZE1MB:
case HW_MMU_COARSE_PAGE_SIZE:
pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va,
virtual_addr &
MMU_SECTION_ADDR_MASK);
break;
case HW_PAGE_SIZE16MB:
num_entries = 16;
pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va,
virtual_addr &
MMU_SSECTION_ADDR_MASK);
break;
default:
return -EINVAL;
}
while (--num_entries >= 0)
((u32 *) pte_addr)[num_entries] = 0;
return status;
}
/* mmu_set_cam_entry */
static hw_status mmu_set_cam_entry(void __iomem *base_address,
const u32 page_sz,
const u32 preserved_bit,
const u32 valid_bit,
const u32 virtual_addr_tag)
{
hw_status status = 0;
u32 mmu_cam_reg;
mmu_cam_reg = (virtual_addr_tag << 12);
mmu_cam_reg = (mmu_cam_reg) | (page_sz) | (valid_bit << 2) |
(preserved_bit << 3);
/* write values to register */
MMUMMU_CAM_WRITE_REGISTER32(base_address, mmu_cam_reg);
return status;
}
/* mmu_set_ram_entry */
static hw_status mmu_set_ram_entry(void __iomem *base_address,
const u32 physical_addr,
enum hw_endianism_t endianism,
enum hw_element_size_t element_size,
enum hw_mmu_mixed_size_t mixed_size)
{
hw_status status = 0;
u32 mmu_ram_reg;
mmu_ram_reg = (physical_addr & MMU_ADDR_MASK);
mmu_ram_reg = (mmu_ram_reg) | ((endianism << 9) | (element_size << 7) |
(mixed_size << 6));
/* write values to register */
MMUMMU_RAM_WRITE_REGISTER32(base_address, mmu_ram_reg);
return status;
}
void hw_mmu_tlb_flush_all(void __iomem *base)
{
__raw_writel(1, base + MMU_GFLUSH);
}

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drivers/staging/tidspbridge/hw/hw_mmu.h
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/*
* hw_mmu.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* MMU types and API declarations
*
* Copyright (C) 2007 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef _HW_MMU_H
#define _HW_MMU_H
#include <linux/types.h>
/* Bitmasks for interrupt sources */
#define HW_MMU_TRANSLATION_FAULT 0x2
#define HW_MMU_ALL_INTERRUPTS 0x1F
#define HW_MMU_COARSE_PAGE_SIZE 0x400
/* hw_mmu_mixed_size_t: Enumerated Type used to specify whether to follow
CPU/TLB Element size */
enum hw_mmu_mixed_size_t {
HW_MMU_TLBES,
HW_MMU_CPUES
};
/* hw_mmu_map_attrs_t: Struct containing MMU mapping attributes */
struct hw_mmu_map_attrs_t {
enum hw_endianism_t endianism;
enum hw_element_size_t element_size;
enum hw_mmu_mixed_size_t mixed_size;
bool donotlockmpupage;
};
extern hw_status hw_mmu_enable(void __iomem *base_address);
extern hw_status hw_mmu_disable(void __iomem *base_address);
extern hw_status hw_mmu_num_locked_set(void __iomem *base_address,
u32 num_locked_entries);
extern hw_status hw_mmu_victim_num_set(void __iomem *base_address,
u32 victim_entry_num);
/* For MMU faults */
extern hw_status hw_mmu_event_ack(void __iomem *base_address,
u32 irq_mask);
extern hw_status hw_mmu_event_disable(void __iomem *base_address,
u32 irq_mask);
extern hw_status hw_mmu_event_enable(void __iomem *base_address,
u32 irq_mask);
extern hw_status hw_mmu_event_status(void __iomem *base_address,
u32 *irq_mask);
extern hw_status hw_mmu_fault_addr_read(void __iomem *base_address,
u32 *addr);
/* Set the TT base address */
extern hw_status hw_mmu_ttb_set(void __iomem *base_address,
u32 ttb_phys_addr);
extern hw_status hw_mmu_twl_enable(void __iomem *base_address);
extern hw_status hw_mmu_twl_disable(void __iomem *base_address);
extern hw_status hw_mmu_tlb_add(void __iomem *base_address,
u32 physical_addr,
u32 virtual_addr,
u32 page_sz,
u32 entry_num,
struct hw_mmu_map_attrs_t *map_attrs,
s8 preserved_bit, s8 valid_bit);
/* For PTEs */
extern hw_status hw_mmu_pte_set(const u32 pg_tbl_va,
u32 physical_addr,
u32 virtual_addr,
u32 page_sz,
struct hw_mmu_map_attrs_t *map_attrs);
extern hw_status hw_mmu_pte_clear(const u32 pg_tbl_va,
u32 virtual_addr, u32 page_size);
void hw_mmu_tlb_flush_all(void __iomem *base);
static inline u32 hw_mmu_pte_addr_l1(u32 l1_base, u32 va)
{
u32 pte_addr;
u32 va31_to20;
va31_to20 = va >> (20 - 2); /* Left-shift by 2 here itself */
va31_to20 &= 0xFFFFFFFCUL;
pte_addr = l1_base + va31_to20;
return pte_addr;
}
static inline u32 hw_mmu_pte_addr_l2(u32 l2_base, u32 va)
{
u32 pte_addr;
pte_addr = (l2_base & 0xFFFFFC00) | ((va >> 10) & 0x3FC);
return pte_addr;
}
static inline u32 hw_mmu_pte_coarse_l1(u32 pte_val)
{
u32 pte_coarse;
pte_coarse = pte_val & 0xFFFFFC00;
return pte_coarse;
}
static inline u32 hw_mmu_pte_size_l1(u32 pte_val)
{
u32 pte_size = 0;
if ((pte_val & 0x3) == 0x1) {
/* Points to L2 PT */
pte_size = HW_MMU_COARSE_PAGE_SIZE;
}
if ((pte_val & 0x3) == 0x2) {
if (pte_val & (1 << 18))
pte_size = HW_PAGE_SIZE16MB;
else
pte_size = HW_PAGE_SIZE1MB;
}
return pte_size;
}
static inline u32 hw_mmu_pte_size_l2(u32 pte_val)
{
u32 pte_size = 0;
if (pte_val & 0x2)
pte_size = HW_PAGE_SIZE4KB;
else if (pte_val & 0x1)
pte_size = HW_PAGE_SIZE64KB;
return pte_size;
}
#endif /* _HW_MMU_H */

177
drivers/staging/tidspbridge/include/dspbridge/_chnl_sm.h
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@ -1,177 +0,0 @@
/*
* _chnl_sm.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Private header file defining channel manager and channel objects for
* a shared memory channel driver.
*
* Shared between the modules implementing the shared memory channel class
* library.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef _CHNL_SM_
#define _CHNL_SM_
#include <dspbridge/dspapi.h>
#include <dspbridge/dspdefs.h>
#include <linux/list.h>
#include <dspbridge/ntfy.h>
/*
* These target side symbols define the beginning and ending addresses
* of shared memory buffer. They are defined in the *cfg.cmd file by
* cdb code.
*/
#define CHNL_SHARED_BUFFER_BASE_SYM "_SHM_BEG"
#define CHNL_SHARED_BUFFER_LIMIT_SYM "_SHM_END"
#define BRIDGEINIT_BIOSGPTIMER "_BRIDGEINIT_BIOSGPTIMER"
#define BRIDGEINIT_LOADMON_GPTIMER "_BRIDGEINIT_LOADMON_GPTIMER"
#ifndef _CHNL_WORDSIZE
#define _CHNL_WORDSIZE 4 /* default _CHNL_WORDSIZE is 2 bytes/word */
#endif
#define MAXOPPS 16
/* Shared memory config options */
#define SHM_CURROPP 0 /* Set current OPP in shm */
#define SHM_OPPINFO 1 /* Set dsp voltage and freq table values */
#define SHM_GETOPP 2 /* Get opp requested by DSP */
struct opp_table_entry {
u32 voltage;
u32 frequency;
u32 min_freq;
u32 max_freq;
};
struct opp_struct {
u32 curr_opp_pt;
u32 num_opp_pts;
struct opp_table_entry opp_point[MAXOPPS];
};
/* Request to MPU */
struct opp_rqst_struct {
u32 rqst_dsp_freq;
u32 rqst_opp_pt;
};
/* Info to MPU */
struct load_mon_struct {
u32 curr_dsp_load;
u32 curr_dsp_freq;
u32 pred_dsp_load;
u32 pred_dsp_freq;
};
/* Structure in shared between DSP and PC for communication. */
struct shm {
u32 dsp_free_mask; /* Written by DSP, read by PC. */
u32 host_free_mask; /* Written by PC, read by DSP */
u32 input_full; /* Input channel has unread data. */
u32 input_id; /* Channel for which input is available. */
u32 input_size; /* Size of data block (in DSP words). */
u32 output_full; /* Output channel has unread data. */
u32 output_id; /* Channel for which output is available. */
u32 output_size; /* Size of data block (in DSP words). */
u32 arg; /* Arg for Issue/Reclaim (23 bits for 55x). */
u32 resvd; /* Keep structure size even for 32-bit DSPs */
/* Operating Point structure */
struct opp_struct opp_table_struct;
/* Operating Point Request structure */
struct opp_rqst_struct opp_request;
/* load monitor information structure */
struct load_mon_struct load_mon_info;
/* Flag for WDT enable/disable F/I clocks */
u32 wdt_setclocks;
u32 wdt_overflow; /* WDT overflow time */
char dummy[176]; /* padding to 256 byte boundary */
u32 shm_dbg_var[64]; /* shared memory debug variables */
};
/* Channel Manager: only one created per board: */
struct chnl_mgr {
/* Function interface to Bridge driver */
struct bridge_drv_interface *intf_fxns;
struct io_mgr *iomgr; /* IO manager */
/* Device this board represents */
struct dev_object *dev_obj;
/* These fields initialized in bridge_chnl_create(): */
u32 output_mask; /* Host output channels w/ full buffers */
u32 last_output; /* Last output channel fired from DPC */
/* Critical section object handle */
spinlock_t chnl_mgr_lock;
u32 word_size; /* Size in bytes of DSP word */
u8 max_channels; /* Total number of channels */
u8 open_channels; /* Total number of open channels */
struct chnl_object **channels; /* Array of channels */
u8 type; /* Type of channel class library */
/* If no shm syms, return for CHNL_Open */
int chnl_open_status;
};
/*
* Channel: up to CHNL_MAXCHANNELS per board or if DSP-DMA supported then
* up to CHNL_MAXCHANNELS + CHNL_MAXDDMACHNLS per board.
*/
struct chnl_object {
/* Pointer back to channel manager */
struct chnl_mgr *chnl_mgr_obj;
u32 chnl_id; /* Channel id */
u8 state; /* Current channel state */
s8 chnl_mode; /* Chnl mode and attributes */
/* Chnl I/O completion event (user mode) */
void *user_event;
/* Abstract synchronization object */
struct sync_object *sync_event;
u32 process; /* Process which created this channel */
u32 cb_arg; /* Argument to use with callback */
struct list_head io_requests; /* List of IOR's to driver */
s32 cio_cs; /* Number of IOC's in queue */
s32 cio_reqs; /* Number of IORequests in queue */
s32 chnl_packets; /* Initial number of free Irps */
/* List of IOC's from driver */
struct list_head io_completions;
struct list_head free_packets_list; /* List of free Irps */
struct ntfy_object *ntfy_obj;
u32 bytes_moved; /* Total number of bytes transferred */
/* For DSP-DMA */
/* Type of chnl transport:CHNL_[PCPY][DDMA] */
u32 chnl_type;
};
/* I/O Request/completion packet: */
struct chnl_irp {
struct list_head link; /* Link to next CHIRP in queue. */
/* Buffer to be filled/emptied. (User) */
u8 *host_user_buf;
/* Buffer to be filled/emptied. (System) */
u8 *host_sys_buf;
u32 arg; /* Issue/Reclaim argument. */
u32 dsp_tx_addr; /* Transfer address on DSP side. */
u32 byte_size; /* Bytes transferred. */
u32 buf_size; /* Actual buffer size when allocated. */
u32 status; /* Status of IO completion. */
};
#endif /* _CHNL_SM_ */

37
drivers/staging/tidspbridge/include/dspbridge/brddefs.h
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@ -1,37 +0,0 @@
/*
* brddefs.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Global BRD constants and types, shared between DSP API and Bridge driver.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef BRDDEFS_
#define BRDDEFS_
/* platform status values */
#define BRD_STOPPED 0x0 /* No Monitor Loaded, Not running. */
#define BRD_IDLE 0x1 /* Monitor Loaded, but suspended. */
#define BRD_RUNNING 0x2 /* Monitor loaded, and executing. */
#define BRD_UNKNOWN 0x3 /* Board state is indeterminate. */
#define BRD_LOADED 0x5
#define BRD_SLEEP_TRANSITION 0x6 /* Sleep transition in progress */
#define BRD_HIBERNATION 0x7 /* MPU initiated hibernation */
#define BRD_RETENTION 0x8 /* Retention mode */
#define BRD_DSP_HIBERNATION 0x9 /* DSP initiated hibernation */
#define BRD_ERROR 0xA /* Board state is Error */
/* BRD Object */
struct brd_object;
#endif /* BRDDEFS_ */

61
drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h
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@ -1,61 +0,0 @@
/*
* cfgdefs.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Global CFG constants and types, shared between DSP API and Bridge driver.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef CFGDEFS_
#define CFGDEFS_
/* Host Resources: */
#define CFG_MAXMEMREGISTERS 9
/* IRQ flag */
#define CFG_IRQSHARED 0x01 /* IRQ can be shared */
/* A platform-related device handle: */
struct cfg_devnode;
/*
* Host resource structure.
*/
struct cfg_hostres {
u32 num_mem_windows; /* Set to default */
/* This is the base.memory */
u32 mem_base[CFG_MAXMEMREGISTERS]; /* shm virtual address */
u32 mem_length[CFG_MAXMEMREGISTERS]; /* Length of the Base */
u32 mem_phys[CFG_MAXMEMREGISTERS]; /* shm Physical address */
u8 birq_registers; /* IRQ Number */
u8 birq_attrib; /* IRQ Attribute */
u32 offset_for_monitor; /* The Shared memory starts from
* mem_base + this offset */
/*
* Info needed by NODE for allocating channels to communicate with RMS:
* chnl_offset: Offset of RMS channels. Lower channels are
* reserved.
* chnl_buf_size: Size of channel buffer to send to RMS
* num_chnls: Total number of channels
* (including reserved).
*/
u32 chnl_offset;
u32 chnl_buf_size;
u32 num_chnls;
void __iomem *per_base;
void __iomem *per_pm_base;
void __iomem *core_pm_base;
void __iomem *dmmu_base;
};
#endif /* CFGDEFS_ */

80
drivers/staging/tidspbridge/include/dspbridge/chnl.h
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@ -1,80 +0,0 @@
/*
* chnl.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* DSP API channel interface: multiplexes data streams through the single
* physical link managed by a Bridge driver.
*
* See DSP API chnl.h for more details.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef CHNL_
#define CHNL_
#include <dspbridge/chnlpriv.h>
/*
* ======== chnl_create ========
* Purpose:
* Create a channel manager object, responsible for opening new channels
* and closing old ones for a given board.
* Parameters:
* channel_mgr: Location to store a channel manager object on output.
* hdev_obj: Handle to a device object.
* mgr_attrts: Channel manager attributes.
* mgr_attrts->max_channels: Max channels
* mgr_attrts->birq: Channel's I/O IRQ number.
* mgr_attrts->irq_shared: TRUE if the IRQ is shareable.
* mgr_attrts->word_size: DSP Word size in equivalent PC bytes..
* Returns:
* 0: Success;
* -EFAULT: hdev_obj is invalid.
* -EINVAL: max_channels is 0.
* Invalid DSP word size (must be > 0).
* Invalid base address for DSP communications.
* -ENOMEM: Insufficient memory for requested resources.
* -EIO: Unable to plug channel ISR for configured IRQ.
* -ECHRNG: This manager cannot handle this many channels.
* -EEXIST: Channel manager already exists for this device.
* Requires:
* channel_mgr != NULL.
* mgr_attrts != NULL.
* Ensures:
* 0: Subsequent calls to chnl_create() for the same
* board without an intervening call to
* chnl_destroy() will fail.
*/
extern int chnl_create(struct chnl_mgr **channel_mgr,
struct dev_object *hdev_obj,
const struct chnl_mgrattrs *mgr_attrts);
/*
* ======== chnl_destroy ========
* Purpose:
* Close all open channels, and destroy the channel manager.
* Parameters:
* hchnl_mgr: Channel manager object.
* Returns:
* 0: Success.
* -EFAULT: hchnl_mgr was invalid.
* Requires:
* Ensures:
* 0: Cancels I/O on each open channel.
* Closes each open channel.
* chnl_create may subsequently be called for the
* same board.
*/
extern int chnl_destroy(struct chnl_mgr *hchnl_mgr);
#endif /* CHNL_ */

63
drivers/staging/tidspbridge/include/dspbridge/chnldefs.h
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@ -1,63 +0,0 @@
/*
* chnldefs.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* System-wide channel objects and constants.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef CHNLDEFS_
#define CHNLDEFS_
/* Channel id option. */
#define CHNL_PICKFREE (~0UL) /* Let manager pick a free channel. */
/* Channel modes */
#define CHNL_MODETODSP 0 /* Data streaming to the DSP. */
#define CHNL_MODEFROMDSP 1 /* Data streaming from the DSP. */
/* GetIOCompletion flags */
#define CHNL_IOCINFINITE 0xffffffff /* Wait forever for IO completion. */
#define CHNL_IOCNOWAIT 0x0 /* Dequeue an IOC, if available. */
/* IO Completion Record status: */
#define CHNL_IOCSTATCOMPLETE 0x0000 /* IO Completed. */
#define CHNL_IOCSTATCANCEL 0x0002 /* IO was cancelled */
#define CHNL_IOCSTATTIMEOUT 0x0008 /* Wait for IOC timed out. */
#define CHNL_IOCSTATEOS 0x8000 /* End Of Stream reached. */
/* Macros for checking I/O Completion status: */
#define CHNL_IS_IO_COMPLETE(ioc) (!(ioc.status & ~CHNL_IOCSTATEOS))
#define CHNL_IS_IO_CANCELLED(ioc) (ioc.status & CHNL_IOCSTATCANCEL)
#define CHNL_IS_TIMED_OUT(ioc) (ioc.status & CHNL_IOCSTATTIMEOUT)
/* Channel attributes: */
struct chnl_attr {
u32 uio_reqs; /* Max # of preallocated I/O requests. */
void *event_obj; /* User supplied auto-reset event object. */
char *str_event_name; /* Ptr to name of user event object. */
void *reserved1; /* Reserved for future use. */
u32 reserved2; /* Reserved for future use. */
};
/* I/O completion record: */
struct chnl_ioc {
void *buf; /* Buffer to be filled/emptied. */
u32 byte_size; /* Bytes transferred. */
u32 buf_size; /* Actual buffer size in bytes */
u32 status; /* Status of IO completion. */
u32 arg; /* User argument associated with buf. */
};
#endif /* CHNLDEFS_ */

85
drivers/staging/tidspbridge/include/dspbridge/chnlpriv.h
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@ -1,85 +0,0 @@
/*
* chnlpriv.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Private channel header shared between DSPSYS, DSPAPI and
* Bridge driver modules.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef CHNLPRIV_
#define CHNLPRIV_
#include <dspbridge/chnldefs.h>
#include <dspbridge/devdefs.h>
#include <dspbridge/sync.h>
/* Channel manager limits: */
#define CHNL_MAXCHANNELS 32 /* Max channels available per transport */
/*
* Trans port channel Id definitions:(must match dsp-side).
*
* For CHNL_MAXCHANNELS = 16:
*
* ChnlIds:
* 0-15 (PCPY) - transport 0)
* 16-31 (DDMA) - transport 1)
* 32-47 (ZCPY) - transport 2)
*/
#define CHNL_PCPY 0 /* Proc-copy transport 0 */
/* Higher level channel states: */
#define CHNL_STATEREADY 0 /* Channel ready for I/O. */
#define CHNL_STATECANCEL 1 /* I/O was cancelled. */
#define CHNL_STATEEOS 2 /* End Of Stream reached. */
/* Macros for checking mode: */
#define CHNL_IS_INPUT(mode) (mode & CHNL_MODEFROMDSP)
#define CHNL_IS_OUTPUT(mode) (!CHNL_IS_INPUT(mode))
/* Types of channel class libraries: */
#define CHNL_TYPESM 1 /* Shared memory driver. */
/* Channel info. */
struct chnl_info {
struct chnl_mgr *chnl_mgr; /* Owning channel manager. */
u32 cnhl_id; /* Channel ID. */
void *event_obj; /* Channel I/O completion event. */
/*Abstraction of I/O completion event. */
struct sync_object *sync_event;
s8 mode; /* Channel mode. */
u8 state; /* Current channel state. */
u32 bytes_tx; /* Total bytes transferred. */
u32 cio_cs; /* Number of IOCs in queue. */
u32 cio_reqs; /* Number of IO Requests in queue. */
u32 process; /* Process owning this channel. */
};
/* Channel manager info: */
struct chnl_mgrinfo {
u8 type; /* Type of channel class library. */
/* Channel handle, given the channel id. */
struct chnl_object *chnl_obj;
u8 open_channels; /* Number of open channels. */
u8 max_channels; /* total # of chnls supported */
};
/* Channel Manager Attrs: */
struct chnl_mgrattrs {
/* Max number of channels this manager can use. */
u8 max_channels;
u32 word_size; /* DSP Word size. */
};
#endif /* CHNLPRIV_ */

101
drivers/staging/tidspbridge/include/dspbridge/clk.h
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@ -1,101 +0,0 @@
/*
* clk.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Provides Clock functions.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef _CLK_H
#define _CLK_H
enum dsp_clk_id {
DSP_CLK_IVA2 = 0,
DSP_CLK_GPT5,
DSP_CLK_GPT6,
DSP_CLK_GPT7,
DSP_CLK_GPT8,
DSP_CLK_WDT3,
DSP_CLK_MCBSP1,
DSP_CLK_MCBSP2,
DSP_CLK_MCBSP3,
DSP_CLK_MCBSP4,
DSP_CLK_MCBSP5,
DSP_CLK_SSI,
DSP_CLK_NOT_DEFINED
};
/*
* ======== dsp_clk_exit ========
* Purpose:
* Discontinue usage of module; free resources when reference count
* reaches 0.
* Parameters:
* Returns:
* Requires:
* CLK initialized.
* Ensures:
* Resources used by module are freed when cRef reaches zero.
*/
extern void dsp_clk_exit(void);
/*
* ======== dsp_clk_init ========
* Purpose:
* Initializes private state of CLK module.
* Parameters:
* Returns:
* TRUE if initialized; FALSE if error occurred.
* Requires:
* Ensures:
* CLK initialized.
*/
extern void dsp_clk_init(void);
void dsp_gpt_wait_overflow(short int clk_id, unsigned int load);
/*
* ======== dsp_clk_enable ========
* Purpose:
* Enables the clock requested.
* Parameters:
* Returns:
* 0: Success.
* -EPERM: Error occurred while enabling the clock.
* Requires:
* Ensures:
*/
extern int dsp_clk_enable(enum dsp_clk_id clk_id);
u32 dsp_clock_enable_all(u32 dsp_per_clocks);
/*
* ======== dsp_clk_disable ========
* Purpose:
* Disables the clock requested.
* Parameters:
* Returns:
* 0: Success.
* -EPERM: Error occurred while disabling the clock.
* Requires:
* Ensures:
*/
extern int dsp_clk_disable(enum dsp_clk_id clk_id);
extern u32 dsp_clk_get_iva2_rate(void);
u32 dsp_clock_disable_all(u32 dsp_per_clocks);
extern void ssi_clk_prepare(bool FLAG);
#endif /* _SYNC_H */

337
drivers/staging/tidspbridge/include/dspbridge/cmm.h
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@ -1,337 +0,0 @@
/*
* cmm.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* The Communication Memory Management(CMM) module provides shared memory
* management services for DSP/BIOS Bridge data streaming and messaging.
* Multiple shared memory segments can be registered with CMM. Memory is
* coelesced back to the appropriate pool when a buffer is freed.
*
* The CMM_Xlator[xxx] functions are used for node messaging and data
* streaming address translation to perform zero-copy inter-processor
* data transfer(GPP<->DSP). A "translator" object is created for a node or
* stream object that contains per thread virtual address information. This
* translator info is used at runtime to perform SM address translation
* to/from the DSP address space.
*
* Notes:
* cmm_xlator_alloc_buf - Used by Node and Stream modules for SM address
* translation.
*
* Copyright (C) 2008 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef CMM_
#define CMM_
#include <dspbridge/devdefs.h>
#include <dspbridge/cmmdefs.h>
#include <dspbridge/host_os.h>
/*
* ======== cmm_calloc_buf ========
* Purpose:
* Allocate memory buffers that can be used for data streaming or
* messaging.
* Parameters:
* hcmm_mgr: Cmm Mgr handle.
* usize: Number of bytes to allocate.
* pattr: Attributes of memory to allocate.
* pp_buf_va: Address of where to place VA.
* Returns:
* Pointer to a zero'd block of SM memory;
* NULL if memory couldn't be allocated,
* or if byte_size == 0,
* Requires:
* Valid hcmm_mgr.
* CMM initialized.
* Ensures:
* The returned pointer, if not NULL, points to a valid memory block of
* the size requested.
*
*/
extern void *cmm_calloc_buf(struct cmm_object *hcmm_mgr,
u32 usize, struct cmm_attrs *pattrs,
void **pp_buf_va);
/*
* ======== cmm_create ========
* Purpose:
* Create a communication memory manager object.
* Parameters:
* ph_cmm_mgr: Location to store a communication manager handle on
* output.
* hdev_obj: Handle to a device object.
* mgr_attrts: Comm mem manager attributes.
* Returns:
* 0: Success;
* -ENOMEM: Insufficient memory for requested resources.
* -EPERM: Failed to initialize critical sect sync object.
*
* Requires:
* ph_cmm_mgr != NULL.
* mgr_attrts->min_block_size >= 4 bytes.
* Ensures:
*
*/
extern int cmm_create(struct cmm_object **ph_cmm_mgr,
struct dev_object *hdev_obj,
const struct cmm_mgrattrs *mgr_attrts);
/*
* ======== cmm_destroy ========
* Purpose:
* Destroy the communication memory manager object.
* Parameters:
* hcmm_mgr: Cmm Mgr handle.
* force: Force deallocation of all cmm memory immediately if set TRUE.
* If FALSE, and outstanding allocations will return -EPERM
* status.
* Returns:
* 0: CMM object & resources deleted.
* -EPERM: Unable to free CMM object due to outstanding allocation.
* -EFAULT: Unable to free CMM due to bad handle.
* Requires:
* CMM is initialized.
* hcmm_mgr != NULL.
* Ensures:
* Memory resources used by Cmm Mgr are freed.
*/
extern int cmm_destroy(struct cmm_object *hcmm_mgr, bool force);
/*
* ======== cmm_free_buf ========
* Purpose:
* Free the given buffer.
* Parameters:
* hcmm_mgr: Cmm Mgr handle.
* pbuf: Pointer to memory allocated by cmm_calloc_buf().
* ul_seg_id: SM segment Id used in CMM_Calloc() attrs.
* Set to 0 to use default segment.
* Returns:
* 0
* -EPERM
* Requires:
* CMM initialized.
* buf_pa != NULL
* Ensures:
*
*/
extern int cmm_free_buf(struct cmm_object *hcmm_mgr,
void *buf_pa, u32 ul_seg_id);
/*
* ======== cmm_get_handle ========
* Purpose:
* Return the handle to the cmm mgr for the given device obj.
* Parameters:
* hprocessor: Handle to a Processor.
* ph_cmm_mgr: Location to store the shared memory mgr handle on
* output.
*
* Returns:
* 0: Cmm Mgr opaque handle returned.
* -EFAULT: Invalid handle.
* Requires:
* ph_cmm_mgr != NULL
* hdev_obj != NULL
* Ensures:
*/
extern int cmm_get_handle(void *hprocessor,
struct cmm_object **ph_cmm_mgr);
/*
* ======== cmm_get_info ========
* Purpose:
* Return the current SM and VM utilization information.
* Parameters:
* hcmm_mgr: Handle to a Cmm Mgr.
* cmm_info_obj: Location to store the Cmm information on output.
*
* Returns:
* 0: Success.
* -EFAULT: Invalid handle.
* -EINVAL Invalid input argument.
* Requires:
* Ensures:
*
*/
extern int cmm_get_info(struct cmm_object *hcmm_mgr,
struct cmm_info *cmm_info_obj);
/*
* ======== cmm_register_gppsm_seg ========
* Purpose:
* Register a block of SM with the CMM.
* Parameters:
* hcmm_mgr: Handle to a Cmm Mgr.
* lpGPPBasePA: GPP Base Physical address.
* ul_size: Size in GPP bytes.
* dsp_addr_offset GPP PA to DSP PA Offset.
* c_factor: Add offset if CMM_ADDTODSPPA, sub if CMM_SUBFROMDSPPA.
* dw_dsp_base: DSP virtual base byte address.
* ul_dsp_size: Size of DSP segment in bytes.
* sgmt_id: Address to store segment Id.
*
* Returns:
* 0: Success.
* -EFAULT: Invalid hcmm_mgr handle.
* -EINVAL: Invalid input argument.
* -EPERM: Unable to register.
* - On success *sgmt_id is a valid SM segment ID.
* Requires:
* ul_size > 0
* sgmt_id != NULL
* dw_gpp_base_pa != 0
* c_factor = CMM_ADDTODSPPA || c_factor = CMM_SUBFROMDSPPA
* Ensures:
*
*/
extern int cmm_register_gppsm_seg(struct cmm_object *hcmm_mgr,
unsigned int dw_gpp_base_pa,
u32 ul_size,
u32 dsp_addr_offset,
s8 c_factor,
unsigned int dw_dsp_base,
u32 ul_dsp_size,
u32 *sgmt_id, u32 gpp_base_va);
/*
* ======== cmm_un_register_gppsm_seg ========
* Purpose:
* Unregister the given memory segment that was previously registered
* by cmm_register_gppsm_seg.
* Parameters:
* hcmm_mgr: Handle to a Cmm Mgr.
* ul_seg_id Segment identifier returned by cmm_register_gppsm_seg.
* Returns:
* 0: Success.
* -EFAULT: Invalid handle.
* -EINVAL: Invalid ul_seg_id.
* -EPERM: Unable to unregister for unknown reason.
* Requires:
* Ensures:
*
*/
extern int cmm_un_register_gppsm_seg(struct cmm_object *hcmm_mgr,
u32 ul_seg_id);
/*
* ======== cmm_xlator_alloc_buf ========
* Purpose:
* Allocate the specified SM buffer and create a local memory descriptor.
* Place on the descriptor on the translator's HaQ (Host Alloc'd Queue).
* Parameters:
* xlator: Handle to a Xlator object.
* va_buf: Virtual address ptr(client context)
* pa_size: Size of SM memory to allocate.
* Returns:
* Ptr to valid physical address(Pa) of pa_size bytes, NULL if failed.
* Requires:
* va_buf != 0.
* pa_size != 0.
* Ensures:
*
*/
extern void *cmm_xlator_alloc_buf(struct cmm_xlatorobject *xlator,
void *va_buf, u32 pa_size);
/*
* ======== cmm_xlator_create ========
* Purpose:
* Create a translator(xlator) object used for process specific Va<->Pa
* address translation. Node messaging and streams use this to perform
* inter-processor(GPP<->DSP) zero-copy data transfer.
* Parameters:
* xlator: Address to place handle to a new Xlator handle.
* hcmm_mgr: Handle to Cmm Mgr associated with this translator.
* xlator_attrs: Translator attributes used for the client NODE or STREAM.
* Returns:
* 0: Success.
* -EINVAL: Bad input Attrs.
* -ENOMEM: Insufficient memory(local) for requested resources.
* Requires:
* xlator != NULL
* hcmm_mgr != NULL
* xlator_attrs != NULL
* Ensures:
*
*/
extern int cmm_xlator_create(struct cmm_xlatorobject **xlator,
struct cmm_object *hcmm_mgr,
struct cmm_xlatorattrs *xlator_attrs);
/*
* ======== cmm_xlator_free_buf ========
* Purpose:
* Free SM buffer and descriptor.
* Does not free client process VM.
* Parameters:
* xlator: handle to translator.
* buf_va Virtual address of PA to free.
* Returns:
* 0: Success.
* -EFAULT: Bad translator handle.
* Requires:
* Ensures:
*
*/
extern int cmm_xlator_free_buf(struct cmm_xlatorobject *xlator,
void *buf_va);
/*
* ======== cmm_xlator_info ========
* Purpose:
* Set/Get process specific "translator" address info.
* This is used to perform fast virtual address translation
* for shared memory buffers between the GPP and DSP.
* Parameters:
* xlator: handle to translator.
* paddr: Virtual base address of segment.
* ul_size: Size in bytes.
* segm_id: Segment identifier of SM segment(s)
* set_info Set xlator fields if TRUE, else return base addr
* Returns:
* 0: Success.
* -EFAULT: Bad translator handle.
* Requires:
* (paddr != NULL)
* (ul_size > 0)
* Ensures:
*
*/
extern int cmm_xlator_info(struct cmm_xlatorobject *xlator,
u8 **paddr,
u32 ul_size, u32 segm_id, bool set_info);
/*
* ======== cmm_xlator_translate ========
* Purpose:
* Perform address translation VA<->PA for the specified stream or
* message shared memory buffer.
* Parameters:
* xlator: handle to translator.
* paddr address of buffer to translate.
* xtype Type of address xlation. CMM_PA2VA or CMM_VA2PA.
* Returns:
* Valid address on success, else NULL.
* Requires:
* paddr != NULL
* xtype >= CMM_VA2PA) && (xtype <= CMM_DSPPA2PA)
* Ensures:
*
*/
extern void *cmm_xlator_translate(struct cmm_xlatorobject *xlator,
void *paddr, enum cmm_xlatetype xtype);
#endif /* CMM_ */

104
drivers/staging/tidspbridge/include/dspbridge/cmmdefs.h
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@ -1,104 +0,0 @@
/*
* cmmdefs.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Global MEM constants and types.
*
* Copyright (C) 2008 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef CMMDEFS_
#define CMMDEFS_
/* Cmm attributes used in cmm_create() */
struct cmm_mgrattrs {
/* Minimum SM allocation; default 32 bytes. */
u32 min_block_size;
};
/* Attributes for CMM_AllocBuf() & CMM_AllocDesc() */
struct cmm_attrs {
u32 seg_id; /* 1,2... are SM segments. 0 is not. */
u32 alignment; /* 0,1,2,4....min_block_size */
};
/*
* DSPPa to GPPPa Conversion Factor.
*
* For typical platforms:
* converted Address = PaDSP + ( c_factor * addressToConvert).
*/
#define CMM_SUBFROMDSPPA -1
#define CMM_ADDTODSPPA 1
#define CMM_ALLSEGMENTS 0xFFFFFF /* All SegIds */
#define CMM_MAXGPPSEGS 1 /* Maximum # of SM segs */
/*
* SMSEGs are SM segments the DSP allocates from.
*
* This info is used by the GPP to xlate DSP allocated PAs.
*/
struct cmm_seginfo {
u32 seg_base_pa; /* Start Phys address of SM segment */
/* Total size in bytes of segment: DSP+GPP */
u32 total_seg_size;
u32 gpp_base_pa; /* Start Phys addr of Gpp SM seg */
u32 gpp_size; /* Size of Gpp SM seg in bytes */
u32 dsp_base_va; /* DSP virt base byte address */
u32 dsp_size; /* DSP seg size in bytes */
/* # of current GPP allocations from this segment */
u32 in_use_cnt;
u32 seg_base_va; /* Start Virt address of SM seg */
};
/* CMM useful information */
struct cmm_info {
/* # of SM segments registered with this Cmm. */
u32 num_gppsm_segs;
/* Total # of allocations outstanding for CMM */
u32 total_in_use_cnt;
/* Min SM block size allocation from cmm_create() */
u32 min_block_size;
/* Info per registered SM segment. */
struct cmm_seginfo seg_info[CMM_MAXGPPSEGS];
};
/* XlatorCreate attributes */
struct cmm_xlatorattrs {
u32 seg_id; /* segment Id used for SM allocations */
u32 dsp_bufs; /* # of DSP-side bufs */
u32 dsp_buf_size; /* size of DSP-side bufs in GPP bytes */
/* Vm base address alloc'd in client process context */
void *vm_base;
/* vm_size must be >= (dwMaxNumBufs * dwMaxSize) */
u32 vm_size;
};
/*
* Cmm translation types. Use to map SM addresses to process context.
*/
enum cmm_xlatetype {
CMM_VA2PA = 0, /* Virtual to GPP physical address xlation */
CMM_PA2VA = 1, /* GPP Physical to virtual */
CMM_VA2DSPPA = 2, /* Va to DSP Pa */
CMM_PA2DSPPA = 3, /* GPP Pa to DSP Pa */
CMM_DSPPA2PA = 4, /* DSP Pa to GPP Pa */
};
struct cmm_object;
struct cmm_xlatorobject;
#endif /* CMMDEFS_ */

329
drivers/staging/tidspbridge/include/dspbridge/cod.h
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@ -1,329 +0,0 @@
/*
* cod.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Code management module for DSPs. This module provides an interface
* interface for loading both static and dynamic code objects onto DSP
* systems.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef COD_
#define COD_
#include <dspbridge/dblldefs.h>
#define COD_MAXPATHLENGTH 255
#define COD_TRACEBEG "SYS_PUTCBEG"
#define COD_TRACEEND "SYS_PUTCEND"
#define COD_TRACECURPOS "BRIDGE_SYS_PUTC_current"
#define COD_NOLOAD DBLL_NOLOAD
#define COD_SYMB DBLL_SYMB
/* COD code manager handle */
struct cod_manager;
/* COD library handle */
struct cod_libraryobj;
/*
* Function prototypes for writing memory to a DSP system, allocating
* and freeing DSP memory.
*/
typedef u32(*cod_writefxn) (void *priv_ref, u32 dsp_add,
void *pbuf, u32 ul_num_bytes, u32 mem_space);
/*
* ======== cod_close ========
* Purpose:
* Close a library opened with cod_open().
* Parameters:
* lib - Library handle returned by cod_open().
* Returns:
* None.
* Requires:
* COD module initialized.
* valid lib.
* Ensures:
*
*/
extern void cod_close(struct cod_libraryobj *lib);
/*
* ======== cod_create ========
* Purpose:
* Create an object to manage code on a DSP system. This object can be
* used to load an initial program image with arguments that can later
* be expanded with dynamically loaded object files.
* Symbol table information is managed by this object and can be retrieved
* using the cod_get_sym_value() function.
* Parameters:
* manager: created manager object
* str_zl_file: ZL DLL filename, of length < COD_MAXPATHLENGTH.
* Returns:
* 0: Success.
* -ESPIPE: ZL_Create failed.
* -ENOSYS: attrs was not NULL. We don't yet support
* non default values of attrs.
* Requires:
* COD module initialized.
* str_zl_file != NULL
* Ensures:
*/
extern int cod_create(struct cod_manager **mgr,
char *str_zl_file);
/*
* ======== cod_delete ========
* Purpose:
* Delete a code manager object.
* Parameters:
* cod_mgr_obj: handle of manager to be deleted
* Returns:
* None.
* Requires:
* COD module initialized.
* valid cod_mgr_obj.
* Ensures:
*/
extern void cod_delete(struct cod_manager *cod_mgr_obj);
/*
* ======== cod_get_base_lib ========
* Purpose:
* Get handle to the base image DBL library.
* Parameters:
* cod_mgr_obj: handle of manager to be deleted
* plib: location to store library handle on output.
* Returns:
* 0: Success.
* Requires:
* COD module initialized.
* valid cod_mgr_obj.
* plib != NULL.
* Ensures:
*/
extern int cod_get_base_lib(struct cod_manager *cod_mgr_obj,
struct dbll_library_obj **plib);
/*
* ======== cod_get_base_name ========
* Purpose:
* Get the name of the base image DBL library.
* Parameters:
* cod_mgr_obj: handle of manager to be deleted
* sz_name: location to store library name on output.
* usize: size of name buffer.
* Returns:
* 0: Success.
* -EPERM: Buffer too small.
* Requires:
* COD module initialized.
* valid cod_mgr_obj.
* sz_name != NULL.
* Ensures:
*/
extern int cod_get_base_name(struct cod_manager *cod_mgr_obj,
char *sz_name, u32 usize);
/*
* ======== cod_get_entry ========
* Purpose:
* Retrieve the entry point of a loaded DSP program image
* Parameters:
* cod_mgr_obj: handle of manager to be deleted
* entry_pt: pointer to location for entry point
* Returns:
* 0: Success.
* Requires:
* COD module initialized.
* valid cod_mgr_obj.
* entry_pt != NULL.
* Ensures:
*/
extern int cod_get_entry(struct cod_manager *cod_mgr_obj,
u32 *entry_pt);
/*
* ======== cod_get_loader ========
* Purpose:
* Get handle to the DBL loader.
* Parameters:
* cod_mgr_obj: handle of manager to be deleted
* loader: location to store loader handle on output.
* Returns:
* 0: Success.
* Requires:
* COD module initialized.
* valid cod_mgr_obj.
* loader != NULL.
* Ensures:
*/
extern int cod_get_loader(struct cod_manager *cod_mgr_obj,
struct dbll_tar_obj **loader);
/*
* ======== cod_get_section ========
* Purpose:
* Retrieve the starting address and length of a section in the COFF file
* given the section name.
* Parameters:
* lib Library handle returned from cod_open().
* str_sect: name of the section, with or without leading "."
* addr: Location to store address.
* len: Location to store length.
* Returns:
* 0: Success
* -ESPIPE: Symbols could not be found or have not been loaded onto
* the board.
* Requires:
* COD module initialized.
* valid cod_mgr_obj.
* str_sect != NULL;
* addr != NULL;
* len != NULL;
* Ensures:
* 0: *addr and *len contain the address and length of the
* section.
* else: *addr == 0 and *len == 0;
*
*/
extern int cod_get_section(struct cod_libraryobj *lib,
char *str_sect,
u32 *addr, u32 *len);
/*
* ======== cod_get_sym_value ========
* Purpose:
* Retrieve the value for the specified symbol. The symbol is first
* searched for literally and then, if not found, searched for as a
* C symbol.
* Parameters:
* lib: library handle returned from cod_open().
* pstrSymbol: name of the symbol
* value: value of the symbol
* Returns:
* 0: Success.
* -ESPIPE: Symbols could not be found or have not been loaded onto
* the board.
* Requires:
* COD module initialized.
* Valid cod_mgr_obj.
* str_sym != NULL.
* pul_value != NULL.
* Ensures:
*/
extern int cod_get_sym_value(struct cod_manager *cod_mgr_obj,
char *str_sym, u32 * pul_value);
/*
* ======== cod_load_base ========
* Purpose:
* Load the initial program image, optionally with command-line arguments,
* on the DSP system managed by the supplied handle. The program to be
* loaded must be the first element of the args array and must be a fully
* qualified pathname.
* Parameters:
* hmgr: manager to load the code with
* num_argc: number of arguments in the args array
* args: array of strings for arguments to DSP program
* write_fxn: board-specific function to write data to DSP system
* arb: arbitrary pointer to be passed as first arg to write_fxn
* envp: array of environment strings for DSP exec.
* Returns:
* 0: Success.
* -EBADF: Failed to open target code.
* Requires:
* COD module initialized.
* hmgr is valid.
* num_argc > 0.
* args != NULL.
* args[0] != NULL.
* pfn_write != NULL.
* Ensures:
*/
extern int cod_load_base(struct cod_manager *cod_mgr_obj,
u32 num_argc, char *args[],
cod_writefxn pfn_write, void *arb,
char *envp[]);
/*
* ======== cod_open ========
* Purpose:
* Open a library for reading sections. Does not load or set the base.
* Parameters:
* hmgr: manager to load the code with
* sz_coff_path: Coff file to open.
* flags: COD_NOLOAD (don't load symbols) or COD_SYMB (load
* symbols).
* lib_obj: Handle returned that can be used in calls to cod_close
* and cod_get_section.
* Returns:
* S_OK: Success.
* -EBADF: Failed to open target code.
* Requires:
* COD module initialized.
* hmgr is valid.
* flags == COD_NOLOAD || flags == COD_SYMB.
* sz_coff_path != NULL.
* Ensures:
*/
extern int cod_open(struct cod_manager *hmgr,
char *sz_coff_path,
u32 flags, struct cod_libraryobj **lib_obj);
/*
* ======== cod_open_base ========
* Purpose:
* Open base image for reading sections. Does not load the base.
* Parameters:
* hmgr: manager to load the code with
* sz_coff_path: Coff file to open.
* flags: Specifies whether to load symbols.
* Returns:
* 0: Success.
* -EBADF: Failed to open target code.
* Requires:
* COD module initialized.
* hmgr is valid.
* sz_coff_path != NULL.
* Ensures:
*/
extern int cod_open_base(struct cod_manager *hmgr, char *sz_coff_path,
dbll_flags flags);
/*
* ======== cod_read_section ========
* Purpose:
* Retrieve the content of a code section given the section name.
* Parameters:
* cod_mgr_obj - manager in which to search for the symbol
* str_sect - name of the section, with or without leading "."
* str_content - buffer to store content of the section.
* Returns:
* 0: on success, error code on failure
* -ESPIPE: Symbols have not been loaded onto the board.
* Requires:
* COD module initialized.
* valid cod_mgr_obj.
* str_sect != NULL;
* str_content != NULL;
* Ensures:
* 0: *str_content stores the content of the named section.
*/
extern int cod_read_section(struct cod_libraryobj *lib,
char *str_sect,
char *str_content, u32 content_size);
#endif /* COD_ */

358
drivers/staging/tidspbridge/include/dspbridge/dbdcd.h
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@ -1,358 +0,0 @@
/*
* dbdcd.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Defines the DSP/BIOS Bridge Configuration Database (DCD) API.
*
* Copyright (C) 2008 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef DBDCD_
#define DBDCD_
#include <dspbridge/dbdcddef.h>
#include <dspbridge/host_os.h>
#include <dspbridge/nldrdefs.h>
/*
* ======== dcd_auto_register ========
* Purpose:
* This function automatically registers DCD objects specified in a
* special COFF section called ".dcd_register"
* Parameters:
* hdcd_mgr: A DCD manager handle.
* sz_coff_path: Pointer to name of COFF file containing DCD
* objects to be registered.
* Returns:
* 0: Success.
* -EACCES: Unable to find auto-registration/read/load section.
* -EFAULT: Invalid DCD_HMANAGER handle..
* Requires:
* DCD initialized.
* Ensures:
* Note:
* Due to the DCD database construction, it is essential for a DCD-enabled
* COFF file to contain the right COFF sections, especially
* ".dcd_register", which is used for auto registration.
*/
extern int dcd_auto_register(struct dcd_manager *hdcd_mgr,
char *sz_coff_path);
/*
* ======== dcd_auto_unregister ========
* Purpose:
* This function automatically unregisters DCD objects specified in a
* special COFF section called ".dcd_register"
* Parameters:
* hdcd_mgr: A DCD manager handle.
* sz_coff_path: Pointer to name of COFF file containing
* DCD objects to be unregistered.
* Returns:
* 0: Success.
* -EACCES: Unable to find auto-registration/read/load section.
* -EFAULT: Invalid DCD_HMANAGER handle..
* Requires:
* DCD initialized.
* Ensures:
* Note:
* Due to the DCD database construction, it is essential for a DCD-enabled
* COFF file to contain the right COFF sections, especially
* ".dcd_register", which is used for auto unregistration.
*/
extern int dcd_auto_unregister(struct dcd_manager *hdcd_mgr,
char *sz_coff_path);
/*
* ======== dcd_create_manager ========
* Purpose:
* This function creates a DCD module manager.
* Parameters:
* sz_zl_dll_name: Pointer to a DLL name string.
* dcd_mgr: A pointer to a DCD manager handle.
* Returns:
* 0: Success.
* -ENOMEM: Unable to allocate memory for DCD manager handle.
* -EPERM: General failure.
* Requires:
* DCD initialized.
* sz_zl_dll_name is non-NULL.
* dcd_mgr is non-NULL.
* Ensures:
* A DCD manager handle is created.
*/
extern int dcd_create_manager(char *sz_zl_dll_name,
struct dcd_manager **dcd_mgr);
/*
* ======== dcd_destroy_manager ========
* Purpose:
* This function destroys a DCD module manager.
* Parameters:
* hdcd_mgr: A DCD manager handle.
* Returns:
* 0: Success.
* -EFAULT: Invalid DCD manager handle.
* Requires:
* DCD initialized.
* Ensures:
*/
extern int dcd_destroy_manager(struct dcd_manager *hdcd_mgr);
/*
* ======== dcd_enumerate_object ========
* Purpose:
* This function enumerates currently visible DSP/BIOS Bridge objects
* and returns the UUID and type of each enumerated object.
* Parameters:
* index: The object enumeration index.
* obj_type: Type of object to enumerate.
* uuid_obj: Pointer to a dsp_uuid object.
* Returns:
* 0: Success.
* -EPERM: Unable to enumerate through the DCD database.
* ENODATA: Enumeration completed. This is not an error code.
* Requires:
* DCD initialized.
* uuid_obj is a valid pointer.
* Ensures:
* Details:
* This function can be used in conjunction with dcd_get_object_def to
* retrieve object properties.
*/
extern int dcd_enumerate_object(s32 index,
enum dsp_dcdobjtype obj_type,
struct dsp_uuid *uuid_obj);
/*
* ======== dcd_exit ========
* Purpose:
* This function cleans up the DCD module.
* Parameters:
* Returns:
* Requires:
* DCD initialized.
* Ensures:
*/
extern void dcd_exit(void);
/*
* ======== dcd_get_dep_libs ========
* Purpose:
* Given the uuid of a library and size of array of uuids, this function
* fills the array with the uuids of all dependent libraries of the input
* library.
* Parameters:
* hdcd_mgr: A DCD manager handle.
* uuid_obj: Pointer to a dsp_uuid for a library.
* num_libs: Size of uuid array (number of library uuids).
* dep_lib_uuids: Array of dependent library uuids to be filled in.
* prstnt_dep_libs: Array indicating if corresponding lib is persistent.
* phase: phase to obtain correct input library
* Returns:
* 0: Success.
* -ENOMEM: Memory allocation failure.
* -EACCES: Failure to read section containing library info.
* -EPERM: General failure.
* Requires:
* DCD initialized.
* Valid hdcd_mgr.
* uuid_obj != NULL
* dep_lib_uuids != NULL.
* Ensures:
*/
extern int dcd_get_dep_libs(struct dcd_manager *hdcd_mgr,
struct dsp_uuid *uuid_obj,
u16 num_libs,
struct dsp_uuid *dep_lib_uuids,
bool *prstnt_dep_libs,
enum nldr_phase phase);
/*
* ======== dcd_get_num_dep_libs ========
* Purpose:
* Given the uuid of a library, determine its number of dependent
* libraries.
* Parameters:
* hdcd_mgr: A DCD manager handle.
* uuid_obj: Pointer to a dsp_uuid for a library.
* num_libs: Size of uuid array (number of library uuids).
* num_pers_libs: number of persistent dependent library.
* phase: Phase to obtain correct input library
* Returns:
* 0: Success.
* -ENOMEM: Memory allocation failure.
* -EACCES: Failure to read section containing library info.
* -EPERM: General failure.
* Requires:
* DCD initialized.
* Valid hdcd_mgr.
* uuid_obj != NULL
* num_libs != NULL.
* Ensures:
*/
extern int dcd_get_num_dep_libs(struct dcd_manager *hdcd_mgr,
struct dsp_uuid *uuid_obj,
u16 *num_libs,
u16 *num_pers_libs,
enum nldr_phase phase);
/*
* ======== dcd_get_library_name ========
* Purpose:
* This function returns the name of a (dynamic) library for a given
* UUID.
* Parameters:
* hdcd_mgr: A DCD manager handle.
* uuid_obj: Pointer to a dsp_uuid that represents a unique DSP/BIOS
* Bridge object.
* str_lib_name: Buffer to hold library name.
* buff_size: Contains buffer size. Set to string size on output.
* phase: Which phase to load
* phase_split: Are phases in multiple libraries
* Returns:
* 0: Success.
* -EPERM: General failure.
* Requires:
* DCD initialized.
* Valid hdcd_mgr.
* str_lib_name != NULL.
* uuid_obj != NULL
* buff_size != NULL.
* Ensures:
*/
extern int dcd_get_library_name(struct dcd_manager *hdcd_mgr,
struct dsp_uuid *uuid_obj,
char *str_lib_name,
u32 *buff_size,
enum nldr_phase phase,
bool *phase_split);
/*
* ======== dcd_get_object_def ========
* Purpose:
* This function returns the properties/attributes of a DSP/BIOS Bridge
* object.
* Parameters:
* hdcd_mgr: A DCD manager handle.
* uuid_obj: Pointer to a dsp_uuid that represents a unique
* DSP/BIOS Bridge object.
* obj_type: The type of DSP/BIOS Bridge object to be
* referenced (node, processor, etc).
* obj_def: Pointer to an object definition structure. A
* union of various possible DCD object types.
* Returns:
* 0: Success.
* -EACCES: Unable to access/read/parse/load content of object code
* section.
* -EPERM: General failure.
* -EFAULT: Invalid DCD_HMANAGER handle.
* Requires:
* DCD initialized.
* obj_uuid is non-NULL.
* obj_def is non-NULL.
* Ensures:
*/
extern int dcd_get_object_def(struct dcd_manager *hdcd_mgr,
struct dsp_uuid *obj_uuid,
enum dsp_dcdobjtype obj_type,
struct dcd_genericobj *obj_def);
/*
* ======== dcd_get_objects ========
* Purpose:
* This function finds all DCD objects specified in a special
* COFF section called ".dcd_register", and for each object,
* call a "register" function. The "register" function may perform
* various actions, such as 1) register nodes in the node database, 2)
* unregister nodes from the node database, and 3) add overlay nodes.
* Parameters:
* hdcd_mgr: A DCD manager handle.
* sz_coff_path: Pointer to name of COFF file containing DCD
* objects.
* register_fxn: Callback fxn to be applied on each located
* DCD object.
* handle: Handle to pass to callback.
* Returns:
* 0: Success.
* -EACCES: Unable to access/read/parse/load content of object code
* section.
* -EFAULT: Invalid DCD_HMANAGER handle..
* Requires:
* DCD initialized.
* Ensures:
* Note:
* Due to the DCD database construction, it is essential for a DCD-enabled
* COFF file to contain the right COFF sections, especially
* ".dcd_register", which is used for auto registration.
*/
extern int dcd_get_objects(struct dcd_manager *hdcd_mgr,
char *sz_coff_path,
dcd_registerfxn register_fxn, void *handle);
/*
* ======== dcd_init ========
* Purpose:
* This function initializes DCD.
* Parameters:
* Returns:
* FALSE: Initialization failed.
* TRUE: Initialization succeeded.
* Requires:
* Ensures:
* DCD initialized.
*/
extern bool dcd_init(void);
/*
* ======== dcd_register_object ========
* Purpose:
* This function registers a DSP/BIOS Bridge object in the DCD database.
* Parameters:
* uuid_obj: Pointer to a dsp_uuid that identifies a DSP/BIOS
* Bridge object.
* obj_type: Type of object.
* psz_path_name: Path to the object's COFF file.
* Returns:
* 0: Success.
* -EPERM: Failed to register object.
* Requires:
* DCD initialized.
* uuid_obj and szPathName are non-NULL values.
* obj_type is a valid type value.
* Ensures:
*/
extern int dcd_register_object(struct dsp_uuid *uuid_obj,
enum dsp_dcdobjtype obj_type,
char *psz_path_name);
/*
* ======== dcd_unregister_object ========
* Purpose:
* This function de-registers a valid DSP/BIOS Bridge object from the DCD
* database.
* Parameters:
* uuid_obj: Pointer to a dsp_uuid that identifies a DSP/BIOS Bridge
* object.
* obj_type: Type of object.
* Returns:
* 0: Success.
* -EPERM: Unable to de-register the specified object.
* Requires:
* DCD initialized.
* uuid_obj is a non-NULL value.
* obj_type is a valid type value.
* Ensures:
*/
extern int dcd_unregister_object(struct dsp_uuid *uuid_obj,
enum dsp_dcdobjtype obj_type);
#endif /* _DBDCD_H */

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drivers/staging/tidspbridge/include/dspbridge/dbdcddef.h
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/*
* dbdcddef.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* DCD (DSP/BIOS Bridge Configuration Database) constants and types.
*
* Copyright (C) 2008 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef DBDCDDEF_
#define DBDCDDEF_
#include <dspbridge/dbdefs.h>
#include <dspbridge/mgrpriv.h> /* for mgr_processorextinfo */
/*
* The following defines are critical elements for the DCD module:
*
* - DCD_REGKEY enables DCD functions to locate registered DCD objects.
* - DCD_REGISTER_SECTION identifies the COFF section where the UUID of
* registered DCD objects are stored.
*/
#define DCD_REGKEY "Software\\TexasInstruments\\DspBridge\\DCD"
#define DCD_REGISTER_SECTION ".dcd_register"
#define DCD_MAXPATHLENGTH 255
/* DCD Manager Object */
struct dcd_manager;
struct dcd_key_elem {
struct list_head link; /* Make it linked to a list */
char name[DCD_MAXPATHLENGTH]; /* Name of a given value entry */
char *path; /* Pointer to the actual data */
};
/* DCD Node Properties */
struct dcd_nodeprops {
struct dsp_ndbprops ndb_props;
u32 msg_segid;
u32 msg_notify_type;
char *str_create_phase_fxn;
char *str_delete_phase_fxn;
char *str_execute_phase_fxn;
char *str_i_alg_name;
/* Dynamic load properties */
u16 load_type; /* Static, dynamic, overlay */
u32 data_mem_seg_mask; /* Data memory requirements */
u32 code_mem_seg_mask; /* Code memory requirements */
};
/* DCD Generic Object Type */
struct dcd_genericobj {
union dcd_obj {
struct dcd_nodeprops node_obj; /* node object. */
/* processor object. */
struct dsp_processorinfo proc_info;
/* extended proc object (private) */
struct mgr_processorextinfo ext_proc_obj;
} obj_data;
};
/* DCD Internal Callback Type */
typedef int(*dcd_registerfxn) (struct dsp_uuid *uuid_obj,
enum dsp_dcdobjtype obj_type,
void *handle);
#endif /* DBDCDDEF_ */

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drivers/staging/tidspbridge/include/dspbridge/dbdefs.h
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/*
* dbdefs.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Global definitions and constants for DSP/BIOS Bridge.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef DBDEFS_
#define DBDEFS_
#include <linux/types.h>
#include <dspbridge/rms_sh.h> /* Types shared between GPP and DSP */
#define PG_SIZE4K 4096
#define PG_MASK(pg_size) (~((pg_size)-1))
#define PG_ALIGN_LOW(addr, pg_size) ((addr) & PG_MASK(pg_size))
#define PG_ALIGN_HIGH(addr, pg_size) (((addr)+(pg_size)-1) & PG_MASK(pg_size))
/* API return value and calling convention */
#define DBAPI int
/* Maximum length of node name, used in dsp_ndbprops */
#define DSP_MAXNAMELEN 32
/* notify_type values for the RegisterNotify() functions. */
#define DSP_SIGNALEVENT 0x00000001
/* Types of events for processors */
#define DSP_PROCESSORSTATECHANGE 0x00000001
#define DSP_PROCESSORATTACH 0x00000002
#define DSP_PROCESSORDETACH 0x00000004
#define DSP_PROCESSORRESTART 0x00000008
/* DSP exception events (DSP/BIOS and DSP MMU fault) */
#define DSP_MMUFAULT 0x00000010
#define DSP_SYSERROR 0x00000020
#define DSP_EXCEPTIONABORT 0x00000300
#define DSP_PWRERROR 0x00000080
#define DSP_WDTOVERFLOW 0x00000040
/* IVA exception events (IVA MMU fault) */
#define IVA_MMUFAULT 0x00000040
/* Types of events for nodes */
#define DSP_NODESTATECHANGE 0x00000100
#define DSP_NODEMESSAGEREADY 0x00000200
/* Types of events for streams */
#define DSP_STREAMDONE 0x00001000
#define DSP_STREAMIOCOMPLETION 0x00002000
/* Handle definition representing the GPP node in DSPNode_Connect() calls */
#define DSP_HGPPNODE 0xFFFFFFFF
/* Node directions used in DSPNode_Connect() */
#define DSP_TONODE 1
#define DSP_FROMNODE 2
/* Define Node Minimum and Maximum Priorities */
#define DSP_NODE_MIN_PRIORITY 1
#define DSP_NODE_MAX_PRIORITY 15
/* msg_ctrl contains SM buffer description */
#define DSP_RMSBUFDESC RMS_BUFDESC
/* Processor ID numbers */
#define DSP_UNIT 0
#define IVA_UNIT 1
#define DSPWORD unsigned char
#define DSPWORDSIZE sizeof(DSPWORD)
#define MAX_PROFILES 16
/* DSP chip type */
#define DSPTYPE64 0x99
/* Handy Macros */
#define VALID_PROC_EVENT (DSP_PROCESSORSTATECHANGE | DSP_PROCESSORATTACH | \
DSP_PROCESSORDETACH | DSP_PROCESSORRESTART | DSP_NODESTATECHANGE | \
DSP_STREAMDONE | DSP_STREAMIOCOMPLETION | DSP_MMUFAULT | \
DSP_SYSERROR | DSP_WDTOVERFLOW | DSP_PWRERROR)
static inline bool is_valid_proc_event(u32 x)
{
return (x == 0 || (x & VALID_PROC_EVENT && !(x & ~VALID_PROC_EVENT)));
}
/* The Node UUID structure */
struct dsp_uuid {
u32 data1;
u16 data2;
u16 data3;
u8 data4;
u8 data5;
u8 data6[6];
};
/* DCD types */
enum dsp_dcdobjtype {
DSP_DCDNODETYPE,
DSP_DCDPROCESSORTYPE,
DSP_DCDLIBRARYTYPE,
DSP_DCDCREATELIBTYPE,
DSP_DCDEXECUTELIBTYPE,
DSP_DCDDELETELIBTYPE,
/* DSP_DCDMAXOBJTYPE is meant to be the last DCD object type */
DSP_DCDMAXOBJTYPE
};
/* Processor states */
enum dsp_procstate {
PROC_STOPPED,
PROC_LOADED,
PROC_RUNNING,
PROC_ERROR
};
/*
* Node types: Message node, task node, xDAIS socket node, and
* device node. _NODE_GPP is used when defining a stream connection
* between a task or socket node and the GPP.
*
*/
enum node_type {
NODE_DEVICE,
NODE_TASK,
NODE_DAISSOCKET,
NODE_MESSAGE,
NODE_GPP
};
/*
* ======== node_state ========
* Internal node states.
*/
enum node_state {
NODE_ALLOCATED,
NODE_CREATED,
NODE_RUNNING,
NODE_PAUSED,
NODE_DONE,
NODE_CREATING,
NODE_STARTING,
NODE_PAUSING,
NODE_TERMINATING,
NODE_DELETING,
};
/* Stream states */
enum dsp_streamstate {
STREAM_IDLE,
STREAM_READY,
STREAM_PENDING,
STREAM_DONE
};
/* Stream connect types */
enum dsp_connecttype {
CONNECTTYPE_NODEOUTPUT,
CONNECTTYPE_GPPOUTPUT,
CONNECTTYPE_NODEINPUT,
CONNECTTYPE_GPPINPUT
};
/* Stream mode types */
enum dsp_strmmode {
STRMMODE_PROCCOPY, /* Processor(s) copy stream data payloads */
STRMMODE_ZEROCOPY, /* Strm buffer ptrs swapped no data copied */
STRMMODE_LDMA, /* Local DMA : OMAP's System-DMA device */
STRMMODE_RDMA /* Remote DMA: OMAP's DSP-DMA device */
};
/* Resource Types */
enum dsp_resourceinfotype {
DSP_RESOURCE_DYNDARAM = 0,
DSP_RESOURCE_DYNSARAM,
DSP_RESOURCE_DYNEXTERNAL,
DSP_RESOURCE_DYNSRAM,
DSP_RESOURCE_PROCLOAD
};
/* Memory Segment Types */
enum dsp_memtype {
DSP_DYNDARAM = 0,
DSP_DYNSARAM,
DSP_DYNEXTERNAL,
DSP_DYNSRAM
};
/* Memory Flush Types */
enum dsp_flushtype {
PROC_INVALIDATE_MEM = 0,
PROC_WRITEBACK_MEM,
PROC_WRITEBACK_INVALIDATE_MEM,
};
/* Memory Segment Status Values */
struct dsp_memstat {
u32 size;
u32 total_free_size;
u32 len_max_free_block;
u32 num_free_blocks;
u32 num_alloc_blocks;
};
/* Processor Load information Values */
struct dsp_procloadstat {
u32 curr_load;
u32 predicted_load;
u32 curr_dsp_freq;
u32 predicted_freq;
};
/* Attributes for STRM connections between nodes */
struct dsp_strmattr {
u32 seg_id; /* Memory segment on DSP to allocate buffers */
u32 buf_size; /* Buffer size (DSP words) */
u32 num_bufs; /* Number of buffers */
u32 buf_alignment; /* Buffer alignment */
u32 timeout; /* Timeout for blocking STRM calls */
enum dsp_strmmode strm_mode; /* mode of stream when opened */
/* DMA chnl id if dsp_strmmode is LDMA or RDMA */
u32 dma_chnl_id;
u32 dma_priority; /* DMA channel priority 0=lowest, >0=high */
};
/* The dsp_cbdata structure */
struct dsp_cbdata {
u32 cb_data;
u8 node_data[1];
};
/* The dsp_msg structure */
struct dsp_msg {
u32 cmd;
u32 arg1;
u32 arg2;
};
/* The dsp_resourcereqmts structure for node's resource requirements */
struct dsp_resourcereqmts {
u32 cb_struct;
u32 static_data_size;
u32 global_data_size;
u32 program_mem_size;
u32 wc_execution_time;
u32 wc_period;
u32 wc_deadline;
u32 avg_exection_time;
u32 minimum_period;
};
/*
* The dsp_streamconnect structure describes a stream connection
* between two nodes, or between a node and the GPP
*/
struct dsp_streamconnect {
u32 cb_struct;
enum dsp_connecttype connect_type;
u32 this_node_stream_index;
void *connected_node;
struct dsp_uuid ui_connected_node_id;
u32 connected_node_stream_index;
};
struct dsp_nodeprofs {
u32 heap_size;
};
/* The dsp_ndbprops structure reports the attributes of a node */
struct dsp_ndbprops {
u32 cb_struct;
struct dsp_uuid ui_node_id;
char ac_name[DSP_MAXNAMELEN];
enum node_type ntype;
u32 cache_on_gpp;
struct dsp_resourcereqmts dsp_resource_reqmts;
s32 prio;
u32 stack_size;
u32 sys_stack_size;
u32 stack_seg;
u32 message_depth;
u32 num_input_streams;
u32 num_output_streams;
u32 timeout;
u32 count_profiles; /* Number of supported profiles */
/* Array of profiles */
struct dsp_nodeprofs node_profiles[MAX_PROFILES];
u32 stack_seg_name; /* Stack Segment Name */
};
/* The dsp_nodeattrin structure describes the attributes of a
* node client */
struct dsp_nodeattrin {
u32 cb_struct;
s32 prio;
u32 timeout;
u32 profile_id;
/* Reserved, for Bridge Internal use only */
u32 heap_size;
void *pgpp_virt_addr; /* Reserved, for Bridge Internal use only */
};
/* The dsp_nodeinfo structure is used to retrieve information
* about a node */
struct dsp_nodeinfo {
u32 cb_struct;
struct dsp_ndbprops nb_node_database_props;
u32 execution_priority;
enum node_state ns_execution_state;
void *device_owner;
u32 number_streams;
struct dsp_streamconnect sc_stream_connection[16];
u32 node_env;
};
/* The dsp_nodeattr structure describes the attributes of a node */
struct dsp_nodeattr {
u32 cb_struct;
struct dsp_nodeattrin in_node_attr_in;
u32 node_attr_inputs;
u32 node_attr_outputs;
struct dsp_nodeinfo node_info;
};
/*
* Notification type: either the name of an opened event, or an event or
* window handle.
*/
struct dsp_notification {
char *name;
void *handle;
};
/* The dsp_processorattrin structure describes the attributes of a processor */
struct dsp_processorattrin {
u32 cb_struct;
u32 timeout;
};
/*
* The dsp_processorinfo structure describes basic capabilities of a
* DSP processor
*/
struct dsp_processorinfo {
u32 cb_struct;
int processor_family;
int processor_type;
u32 clock_rate;
u32 internal_mem_size;
u32 external_mem_size;
u32 processor_id;
int ty_running_rtos;
s32 node_min_priority;
s32 node_max_priority;
};
/* Error information of last DSP exception signalled to the GPP */
struct dsp_errorinfo {
u32 err_mask;
u32 val1;
u32 val2;
u32 val3;
};
/* The dsp_processorstate structure describes the state of a DSP processor */
struct dsp_processorstate {
u32 cb_struct;
enum dsp_procstate proc_state;
};
/*
* The dsp_resourceinfo structure is used to retrieve information about a
* processor's resources
*/
struct dsp_resourceinfo {
u32 cb_struct;
enum dsp_resourceinfotype resource_type;
union {
u32 resource;
struct dsp_memstat mem_stat;
struct dsp_procloadstat proc_load_stat;
} result;
};
/*
* The dsp_streamattrin structure describes the attributes of a stream,
* including segment and alignment of data buffers allocated with
* DSPStream_AllocateBuffers(), if applicable
*/
struct dsp_streamattrin {
u32 cb_struct;
u32 timeout;
u32 segment_id;
u32 buf_alignment;
u32 num_bufs;
enum dsp_strmmode strm_mode;
u32 dma_chnl_id;
u32 dma_priority;
};
/* The dsp_bufferattr structure describes the attributes of a data buffer */
struct dsp_bufferattr {
u32 cb_struct;
u32 segment_id;
u32 buf_alignment;
};
/*
* The dsp_streaminfo structure is used to retrieve information
* about a stream.
*/
struct dsp_streaminfo {
u32 cb_struct;
u32 number_bufs_allowed;
u32 number_bufs_in_stream;
u32 number_bytes;
void *sync_object_handle;
enum dsp_streamstate ss_stream_state;
};
/* DMM MAP attributes
It is a bit mask with each bit value indicating a specific attribute
bit 0 - GPP address type (user virtual=0, physical=1)
bit 1 - MMU Endianism (Big Endian=1, Little Endian=0)
bit 2 - MMU mixed page attribute (Mixed/ CPUES=1, TLBES =0)
bit 3 - MMU element size = 8bit (valid only for non mixed page entries)
bit 4 - MMU element size = 16bit (valid only for non mixed page entries)
bit 5 - MMU element size = 32bit (valid only for non mixed page entries)
bit 6 - MMU element size = 64bit (valid only for non mixed page entries)
bit 14 - Input (read only) buffer
bit 15 - Output (writeable) buffer
*/
/* Types of mapping attributes */
/* MPU address is virtual and needs to be translated to physical addr */
#define DSP_MAPVIRTUALADDR 0x00000000
#define DSP_MAPPHYSICALADDR 0x00000001
/* Mapped data is big endian */
#define DSP_MAPBIGENDIAN 0x00000002
#define DSP_MAPLITTLEENDIAN 0x00000000
/* Element size is based on DSP r/w access size */
#define DSP_MAPMIXEDELEMSIZE 0x00000004
/*
* Element size for MMU mapping (8, 16, 32, or 64 bit)
* Ignored if DSP_MAPMIXEDELEMSIZE enabled
*/
#define DSP_MAPELEMSIZE8 0x00000008
#define DSP_MAPELEMSIZE16 0x00000010
#define DSP_MAPELEMSIZE32 0x00000020
#define DSP_MAPELEMSIZE64 0x00000040
#define DSP_MAPVMALLOCADDR 0x00000080
#define DSP_MAPDONOTLOCK 0x00000100
#define DSP_MAP_DIR_MASK 0x3FFF
#define GEM_CACHE_LINE_SIZE 128
#define GEM_L1P_PREFETCH_SIZE 128
/*
* Definitions from dbreg.h
*/
#define DSPPROCTYPE_C64 6410
#define IVAPROCTYPE_ARM7 470
/* Max registry path length. Also the max registry value length. */
#define MAXREGPATHLENGTH 255
#endif /* DBDEFS_ */

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/*
* dbll.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* DSP/BIOS Bridge Dynamic load library module interface. Function header
* comments are in the file dblldefs.h.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef DBLL_
#define DBLL_
#include <dspbridge/dbdefs.h>
#include <dspbridge/dblldefs.h>
extern bool symbols_reloaded;
extern void dbll_close(struct dbll_library_obj *zl_lib);
extern int dbll_create(struct dbll_tar_obj **target_obj,
struct dbll_attrs *pattrs);
extern void dbll_delete(struct dbll_tar_obj *target);
extern void dbll_exit(void);
extern bool dbll_get_addr(struct dbll_library_obj *zl_lib, char *name,
struct dbll_sym_val **sym_val);
extern void dbll_get_attrs(struct dbll_tar_obj *target,
struct dbll_attrs *pattrs);
extern bool dbll_get_c_addr(struct dbll_library_obj *zl_lib, char *name,
struct dbll_sym_val **sym_val);
extern int dbll_get_sect(struct dbll_library_obj *lib, char *name,
u32 *paddr, u32 *psize);
extern bool dbll_init(void);
extern int dbll_load(struct dbll_library_obj *lib,
dbll_flags flags,
struct dbll_attrs *attrs, u32 * entry);
extern int dbll_open(struct dbll_tar_obj *target, char *file,
dbll_flags flags,
struct dbll_library_obj **lib_obj);
extern int dbll_read_sect(struct dbll_library_obj *lib,
char *name, char *buf, u32 size);
extern void dbll_unload(struct dbll_library_obj *lib, struct dbll_attrs *attrs);
#ifdef CONFIG_TIDSPBRIDGE_BACKTRACE
bool dbll_find_dsp_symbol(struct dbll_library_obj *zl_lib, u32 address,
u32 offset_range, u32 *sym_addr_output, char *name_output);
#endif
#endif /* DBLL_ */

431
drivers/staging/tidspbridge/include/dspbridge/dblldefs.h
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@ -1,431 +0,0 @@
/*
* dblldefs.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef DBLLDEFS_
#define DBLLDEFS_
/*
* Bit masks for dbl_flags.
*/
#define DBLL_NOLOAD 0x0 /* Don't load symbols, code, or data */
#define DBLL_SYMB 0x1 /* load symbols */
#define DBLL_CODE 0x2 /* load code */
#define DBLL_DATA 0x4 /* load data */
#define DBLL_DYNAMIC 0x8 /* dynamic load */
#define DBLL_BSS 0x20 /* Unitialized section */
#define DBLL_MAXPATHLENGTH 255
/*
* ======== DBLL_Target ========
*
*/
struct dbll_tar_obj;
/*
* ======== dbll_flags ========
* Specifies whether to load code, data, or symbols
*/
typedef s32 dbll_flags;
/*
* ======== DBLL_Library ========
*
*/
struct dbll_library_obj;
/*
* ======== dbll_sect_info ========
* For collecting info on overlay sections
*/
struct dbll_sect_info {
const char *name; /* name of section */
u32 sect_run_addr; /* run address of section */
u32 sect_load_addr; /* load address of section */
u32 size; /* size of section (target MAUs) */
dbll_flags type; /* Code, data, or BSS */
};
/*
* ======== dbll_sym_val ========
* (Needed for dynamic load library)
*/
struct dbll_sym_val {
u32 value;
};
/*
* ======== dbll_alloc_fxn ========
* Allocate memory function. Allocate or reserve (if reserved == TRUE)
* "size" bytes of memory from segment "space" and return the address in
* *dsp_address (or starting at *dsp_address if reserve == TRUE). Returns 0 on
* success, or an error code on failure.
*/
typedef s32(*dbll_alloc_fxn) (void *hdl, s32 space, u32 size, u32 align,
u32 *dsp_address, s32 seg_id, s32 req,
bool reserved);
/*
* ======== dbll_close_fxn ========
*/
typedef s32(*dbll_f_close_fxn) (void *);
/*
* ======== dbll_free_fxn ========
* Free memory function. Free, or unreserve (if reserved == TRUE) "size"
* bytes of memory from segment "space"
*/
typedef bool(*dbll_free_fxn) (void *hdl, u32 addr, s32 space, u32 size,
bool reserved);
/*
* ======== dbll_f_open_fxn ========
*/
typedef void *(*dbll_f_open_fxn) (const char *, const char *);
/*
* ======== dbll_log_write_fxn ========
* Function to call when writing data from a section, to log the info.
* Can be NULL if no logging is required.
*/
typedef int(*dbll_log_write_fxn) (void *handle,
struct dbll_sect_info *sect, u32 addr,
u32 bytes);
/*
* ======== dbll_read_fxn ========
*/
typedef s32(*dbll_read_fxn) (void *, size_t, size_t, void *);
/*
* ======== dbll_seek_fxn ========
*/
typedef s32(*dbll_seek_fxn) (void *, long, int);
/*
* ======== dbll_sym_lookup ========
* Symbol lookup function - Find the symbol name and return its value.
*
* Parameters:
* handle - Opaque handle
* parg - Opaque argument.
* name - Name of symbol to lookup.
* sym - Location to store address of symbol structure.
*
* Returns:
* TRUE: Success (symbol was found).
* FALSE: Failed to find symbol.
*/
typedef bool(*dbll_sym_lookup) (void *handle, void *parg, void *rmm_handle,
const char *name, struct dbll_sym_val **sym);
/*
* ======== dbll_tell_fxn ========
*/
typedef s32(*dbll_tell_fxn) (void *);
/*
* ======== dbll_write_fxn ========
* Write memory function. Write "n" HOST bytes of memory to segment "mtype"
* starting at address "dsp_address" from the buffer "buf". The buffer is
* formatted as an array of words appropriate for the DSP.
*/
typedef s32(*dbll_write_fxn) (void *hdl, u32 dsp_address, void *buf,
u32 n, s32 mtype);
/*
* ======== dbll_attrs ========
*/
struct dbll_attrs {
dbll_alloc_fxn alloc;
dbll_free_fxn free;
void *rmm_handle; /* Handle to pass to alloc, free functions */
dbll_write_fxn write;
void *input_params; /* Handle to pass to write, cinit function */
bool base_image;
dbll_log_write_fxn log_write;
void *log_write_handle;
/* Symbol matching function and handle to pass to it */
dbll_sym_lookup sym_lookup;
void *sym_handle;
void *sym_arg;
/*
* These file manipulation functions should be compatible with the
* "C" run time library functions of the same name.
*/
s32 (*fread)(void *ptr, size_t size, size_t count, void *filp);
s32 (*fseek)(void *filp, long offset, int origin);
s32 (*ftell)(void *filp);
s32 (*fclose)(void *filp);
void *(*fopen)(const char *path, const char *mode);
};
/*
* ======== dbll_close ========
* Close library opened with dbll_open.
* Parameters:
* lib - Handle returned from dbll_open().
* Returns:
* Requires:
* DBL initialized.
* Valid lib.
* Ensures:
*/
typedef void (*dbll_close_fxn) (struct dbll_library_obj *library);
/*
* ======== dbll_create ========
* Create a target object, specifying the alloc, free, and write functions.
* Parameters:
* target_obj - Location to store target handle on output.
* pattrs - Attributes.
* Returns:
* 0: Success.
* -ENOMEM: Memory allocation failed.
* Requires:
* DBL initialized.
* pattrs != NULL.
* target_obj != NULL;
* Ensures:
* Success: *target_obj != NULL.
* Failure: *target_obj == NULL.
*/
typedef int(*dbll_create_fxn) (struct dbll_tar_obj **target_obj,
struct dbll_attrs *attrs);
/*
* ======== dbll_delete ========
* Delete target object and free resources for any loaded libraries.
* Parameters:
* target - Handle returned from DBLL_Create().
* Returns:
* Requires:
* DBL initialized.
* Valid target.
* Ensures:
*/
typedef void (*dbll_delete_fxn) (struct dbll_tar_obj *target);
/*
* ======== dbll_exit ========
* Discontinue use of DBL module.
* Parameters:
* Returns:
* Requires:
* refs > 0.
* Ensures:
* refs >= 0.
*/
typedef void (*dbll_exit_fxn) (void);
/*
* ======== dbll_get_addr ========
* Get address of name in the specified library.
* Parameters:
* lib - Handle returned from dbll_open().
* name - Name of symbol
* sym_val - Location to store symbol address on output.
* Returns:
* TRUE: Success.
* FALSE: Symbol not found.
* Requires:
* DBL initialized.
* Valid library.
* name != NULL.
* sym_val != NULL.
* Ensures:
*/
typedef bool(*dbll_get_addr_fxn) (struct dbll_library_obj *lib, char *name,
struct dbll_sym_val **sym_val);
/*
* ======== dbll_get_attrs ========
* Retrieve the attributes of the target.
* Parameters:
* target - Handle returned from DBLL_Create().
* pattrs - Location to store attributes on output.
* Returns:
* Requires:
* DBL initialized.
* Valid target.
* pattrs != NULL.
* Ensures:
*/
typedef void (*dbll_get_attrs_fxn) (struct dbll_tar_obj *target,
struct dbll_attrs *attrs);
/*
* ======== dbll_get_c_addr ========
* Get address of "C" name on the specified library.
* Parameters:
* lib - Handle returned from dbll_open().
* name - Name of symbol
* sym_val - Location to store symbol address on output.
* Returns:
* TRUE: Success.
* FALSE: Symbol not found.
* Requires:
* DBL initialized.
* Valid target.
* name != NULL.
* sym_val != NULL.
* Ensures:
*/
typedef bool(*dbll_get_c_addr_fxn) (struct dbll_library_obj *lib, char *name,
struct dbll_sym_val **sym_val);
/*
* ======== dbll_get_sect ========
* Get address and size of a named section.
* Parameters:
* lib - Library handle returned from dbll_open().
* name - Name of section.
* paddr - Location to store section address on output.
* psize - Location to store section size on output.
* Returns:
* 0: Success.
* -ENXIO: Section not found.
* Requires:
* DBL initialized.
* Valid lib.
* name != NULL.
* paddr != NULL;
* psize != NULL.
* Ensures:
*/
typedef int(*dbll_get_sect_fxn) (struct dbll_library_obj *lib,
char *name, u32 *addr, u32 *size);
/*
* ======== dbll_init ========
* Initialize DBL module.
* Parameters:
* Returns:
* TRUE: Success.
* FALSE: Failure.
* Requires:
* refs >= 0.
* Ensures:
* Success: refs > 0.
* Failure: refs >= 0.
*/
typedef bool(*dbll_init_fxn) (void);
/*
* ======== dbll_load ========
* Load library onto the target.
*
* Parameters:
* lib - Library handle returned from dbll_open().
* flags - Load code, data and/or symbols.
* attrs - May contain alloc, free, and write function.
* entry_pt - Location to store program entry on output.
* Returns:
* 0: Success.
* -EBADF: File read failed.
* -EILSEQ: Failure in dynamic loader library.
* Requires:
* DBL initialized.
* Valid lib.
* entry != NULL.
* Ensures:
*/
typedef int(*dbll_load_fxn) (struct dbll_library_obj *lib,
dbll_flags flags,
struct dbll_attrs *attrs, u32 *entry);
/*
* ======== dbll_open ========
* dbll_open() returns a library handle that can be used to load/unload
* the symbols/code/data via dbll_load()/dbll_unload().
* Parameters:
* target - Handle returned from dbll_create().
* file - Name of file to open.
* flags - If flags & DBLL_SYMB, load symbols.
* lib_obj - Location to store library handle on output.
* Returns:
* 0: Success.
* -ENOMEM: Memory allocation failure.
* -EBADF: File open/read failure.
* Unable to determine target type.
* Requires:
* DBL initialized.
* Valid target.
* file != NULL.
* lib_obj != NULL.
* dbll_attrs fopen function non-NULL.
* Ensures:
* Success: Valid *lib_obj.
* Failure: *lib_obj == NULL.
*/
typedef int(*dbll_open_fxn) (struct dbll_tar_obj *target, char *file,
dbll_flags flags,
struct dbll_library_obj **lib_obj);
/*
* ======== dbll_read_sect ========
* Read COFF section into a character buffer.
* Parameters:
* lib - Library handle returned from dbll_open().
* name - Name of section.
* pbuf - Buffer to write section contents into.
* size - Buffer size
* Returns:
* 0: Success.
* -ENXIO: Named section does not exists.
* Requires:
* DBL initialized.
* Valid lib.
* name != NULL.
* pbuf != NULL.
* size != 0.
* Ensures:
*/
typedef int(*dbll_read_sect_fxn) (struct dbll_library_obj *lib,
char *name, char *content,
u32 cont_size);
/*
* ======== dbll_unload ========
* Unload library loaded with dbll_load().
* Parameters:
* lib - Handle returned from dbll_open().
* attrs - Contains free() function and handle to pass to it.
* Returns:
* Requires:
* DBL initialized.
* Valid lib.
* Ensures:
*/
typedef void (*dbll_unload_fxn) (struct dbll_library_obj *library,
struct dbll_attrs *attrs);
struct dbll_fxns {
dbll_close_fxn close_fxn;
dbll_create_fxn create_fxn;
dbll_delete_fxn delete_fxn;
dbll_exit_fxn exit_fxn;
dbll_get_attrs_fxn get_attrs_fxn;
dbll_get_addr_fxn get_addr_fxn;
dbll_get_c_addr_fxn get_c_addr_fxn;
dbll_get_sect_fxn get_sect_fxn;
dbll_init_fxn init_fxn;
dbll_load_fxn load_fxn;
dbll_open_fxn open_fxn;
dbll_read_sect_fxn read_sect_fxn;
dbll_unload_fxn unload_fxn;
};
#endif /* DBLDEFS_ */

620
drivers/staging/tidspbridge/include/dspbridge/dev.h
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@ -1,620 +0,0 @@
/*
* dev.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Bridge Bridge driver device operations.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef DEV_
#define DEV_
/* ----------------------------------- Module Dependent Headers */
#include <dspbridge/chnldefs.h>
#include <dspbridge/cmm.h>
#include <dspbridge/cod.h>
#include <dspbridge/dspdeh.h>
#include <dspbridge/nodedefs.h>
#include <dspbridge/disp.h>
#include <dspbridge/dspdefs.h>
#include <dspbridge/dmm.h>
#include <dspbridge/host_os.h>
/* ----------------------------------- This */
#include <dspbridge/devdefs.h>
/*
* ======== dev_brd_write_fxn ========
* Purpose:
* Exported function to be used as the COD write function. This function
* is passed a handle to a DEV_hObject by ZL in arb, then calls the
* device's bridge_brd_write() function.
* Parameters:
* arb: Handle to a Device Object.
* dev_ctxt: Handle to Bridge driver defined device info.
* dsp_addr: Address on DSP board (Destination).
* host_buf: Pointer to host buffer (Source).
* ul_num_bytes: Number of bytes to transfer.
* mem_type: Memory space on DSP to which to transfer.
* Returns:
* Number of bytes written. Returns 0 if the DEV_hObject passed in via
* arb is invalid.
* Requires:
* DEV Initialized.
* host_buf != NULL
* Ensures:
*/
extern u32 dev_brd_write_fxn(void *arb,
u32 dsp_add,
void *host_buf, u32 ul_num_bytes, u32 mem_space);
/*
* ======== dev_create_device ========
* Purpose:
* Called by the operating system to load the Bridge Driver for a
* 'Bridge device.
* Parameters:
* device_obj: Ptr to location to receive the device object handle.
* driver_file_name: Name of Bridge driver PE DLL file to load. If the
* absolute path is not provided, the file is loaded
* through 'Bridge's module search path.
* host_config: Host configuration information, to be passed down
* to the Bridge driver when bridge_dev_create() is called.
* pDspConfig: DSP resources, to be passed down to the Bridge driver
* when bridge_dev_create() is called.
* dev_node_obj: Platform specific device node.
* Returns:
* 0: Module is loaded, device object has been created
* -ENOMEM: Insufficient memory to create needed resources.
* -EPERM: Unable to find Bridge driver entry point function.
* -ESPIPE: Unable to load ZL DLL.
* Requires:
* DEV Initialized.
* device_obj != NULL.
* driver_file_name != NULL.
* host_config != NULL.
* pDspConfig != NULL.
* Ensures:
* 0: *device_obj will contain handle to the new device object.
* Otherwise, does not create the device object, ensures the Bridge driver
* module is unloaded, and sets *device_obj to NULL.
*/
extern int dev_create_device(struct dev_object
**device_obj,
const char *driver_file_name,
struct cfg_devnode *dev_node_obj);
/*
* ======== dev_create2 ========
* Purpose:
* After successful loading of the image from api_init_complete2
* (PROC Auto_Start) or proc_load this fxn is called. This creates
* the Node Manager and updates the DEV Object.
* Parameters:
* hdev_obj: Handle to device object created with dev_create_device().
* Returns:
* 0: Successful Creation of Node Manager
* -EPERM: Some Error Occurred.
* Requires:
* DEV Initialized
* Valid hdev_obj
* Ensures:
* 0 and hdev_obj->node_mgr != NULL
* else hdev_obj->node_mgr == NULL
*/
extern int dev_create2(struct dev_object *hdev_obj);
/*
* ======== dev_destroy2 ========
* Purpose:
* Destroys the Node manager for this device.
* Parameters:
* hdev_obj: Handle to device object created with dev_create_device().
* Returns:
* 0: Successful Creation of Node Manager
* -EPERM: Some Error Occurred.
* Requires:
* DEV Initialized
* Valid hdev_obj
* Ensures:
* 0 and hdev_obj->node_mgr == NULL
* else -EPERM.
*/
extern int dev_destroy2(struct dev_object *hdev_obj);
/*
* ======== dev_destroy_device ========
* Purpose:
* Destroys the channel manager for this device, if any, calls
* bridge_dev_destroy(), and then attempts to unload the Bridge module.
* Parameters:
* hdev_obj: Handle to device object created with
* dev_create_device().
* Returns:
* 0: Success.
* -EFAULT: Invalid hdev_obj.
* -EPERM: The Bridge driver failed it's bridge_dev_destroy() function.
* Requires:
* DEV Initialized.
* Ensures:
*/
extern int dev_destroy_device(struct dev_object
*hdev_obj);
/*
* ======== dev_get_chnl_mgr ========
* Purpose:
* Retrieve the handle to the channel manager created for this device.
* Parameters:
* hdev_obj: Handle to device object created with
* dev_create_device().
* *mgr: Ptr to location to store handle.
* Returns:
* 0: Success.
* -EFAULT: Invalid hdev_obj.
* Requires:
* mgr != NULL.
* DEV Initialized.
* Ensures:
* 0: *mgr contains a handle to a channel manager object,
* or NULL.
* else: *mgr is NULL.
*/
extern int dev_get_chnl_mgr(struct dev_object *hdev_obj,
struct chnl_mgr **mgr);
/*
* ======== dev_get_cmm_mgr ========
* Purpose:
* Retrieve the handle to the shared memory manager created for this
* device.
* Parameters:
* hdev_obj: Handle to device object created with
* dev_create_device().
* *mgr: Ptr to location to store handle.
* Returns:
* 0: Success.
* -EFAULT: Invalid hdev_obj.
* Requires:
* mgr != NULL.
* DEV Initialized.
* Ensures:
* 0: *mgr contains a handle to a channel manager object,
* or NULL.
* else: *mgr is NULL.
*/
extern int dev_get_cmm_mgr(struct dev_object *hdev_obj,
struct cmm_object **mgr);
/*
* ======== dev_get_dmm_mgr ========
* Purpose:
* Retrieve the handle to the dynamic memory manager created for this
* device.
* Parameters:
* hdev_obj: Handle to device object created with
* dev_create_device().
* *mgr: Ptr to location to store handle.
* Returns:
* 0: Success.
* -EFAULT: Invalid hdev_obj.
* Requires:
* mgr != NULL.
* DEV Initialized.
* Ensures:
* 0: *mgr contains a handle to a channel manager object,
* or NULL.
* else: *mgr is NULL.
*/
extern int dev_get_dmm_mgr(struct dev_object *hdev_obj,
struct dmm_object **mgr);
/*
* ======== dev_get_cod_mgr ========
* Purpose:
* Retrieve the COD manager create for this device.
* Parameters:
* hdev_obj: Handle to device object created with
* dev_create_device().
* *cod_mgr: Ptr to location to store handle.
* Returns:
* 0: Success.
* -EFAULT: Invalid hdev_obj.
* Requires:
* cod_mgr != NULL.
* DEV Initialized.
* Ensures:
* 0: *cod_mgr contains a handle to a COD manager object.
* else: *cod_mgr is NULL.
*/
extern int dev_get_cod_mgr(struct dev_object *hdev_obj,
struct cod_manager **cod_mgr);
/*
* ======== dev_get_deh_mgr ========
* Purpose:
* Retrieve the DEH manager created for this device.
* Parameters:
* hdev_obj: Handle to device object created with dev_create_device().
* *deh_manager: Ptr to location to store handle.
* Returns:
* 0: Success.
* -EFAULT: Invalid hdev_obj.
* Requires:
* deh_manager != NULL.
* DEH Initialized.
* Ensures:
* 0: *deh_manager contains a handle to a DEH manager object.
* else: *deh_manager is NULL.
*/
extern int dev_get_deh_mgr(struct dev_object *hdev_obj,
struct deh_mgr **deh_manager);
/*
* ======== dev_get_dev_node ========
* Purpose:
* Retrieve the platform specific device ID for this device.
* Parameters:
* hdev_obj: Handle to device object created with
* dev_create_device().
* dev_nde: Ptr to location to get the device node handle.
* Returns:
* 0: Returns a DEVNODE in *dev_node_obj.
* -EFAULT: Invalid hdev_obj.
* Requires:
* dev_nde != NULL.
* DEV Initialized.
* Ensures:
* 0: *dev_nde contains a platform specific device ID;
* else: *dev_nde is NULL.
*/
extern int dev_get_dev_node(struct dev_object *hdev_obj,
struct cfg_devnode **dev_nde);
/*
* ======== dev_get_dev_type ========
* Purpose:
* Retrieve the platform specific device ID for this device.
* Parameters:
* hdev_obj: Handle to device object created with
* dev_create_device().
* dev_nde: Ptr to location to get the device node handle.
* Returns:
* 0: Success
* -EFAULT: Invalid hdev_obj.
* Requires:
* dev_nde != NULL.
* DEV Initialized.
* Ensures:
* 0: *dev_nde contains a platform specific device ID;
* else: *dev_nde is NULL.
*/
extern int dev_get_dev_type(struct dev_object *device_obj,
u8 *dev_type);
/*
* ======== dev_get_first ========
* Purpose:
* Retrieve the first Device Object handle from an internal linked list of
* of DEV_OBJECTs maintained by DEV.
* Parameters:
* Returns:
* NULL if there are no device objects stored; else
* a valid DEV_HOBJECT.
* Requires:
* No calls to dev_create_device or dev_destroy_device (which my modify the
* internal device object list) may occur between calls to dev_get_first
* and dev_get_next.
* Ensures:
* The DEV_HOBJECT returned is valid.
* A subsequent call to dev_get_next will return the next device object in
* the list.
*/
extern struct dev_object *dev_get_first(void);
/*
* ======== dev_get_intf_fxns ========
* Purpose:
* Retrieve the Bridge driver interface function structure for the
* loaded Bridge driver.
* Parameters:
* hdev_obj: Handle to device object created with
* dev_create_device().
* *if_fxns: Ptr to location to store fxn interface.
* Returns:
* 0: Success.
* -EFAULT: Invalid hdev_obj.
* Requires:
* if_fxns != NULL.
* DEV Initialized.
* Ensures:
* 0: *if_fxns contains a pointer to the Bridge
* driver interface;
* else: *if_fxns is NULL.
*/
extern int dev_get_intf_fxns(struct dev_object *hdev_obj,
struct bridge_drv_interface **if_fxns);
/*
* ======== dev_get_io_mgr ========
* Purpose:
* Retrieve the handle to the IO manager created for this device.
* Parameters:
* hdev_obj: Handle to device object created with
* dev_create_device().
* *mgr: Ptr to location to store handle.
* Returns:
* 0: Success.
* -EFAULT: Invalid hdev_obj.
* Requires:
* mgr != NULL.
* DEV Initialized.
* Ensures:
* 0: *mgr contains a handle to an IO manager object.
* else: *mgr is NULL.
*/
extern int dev_get_io_mgr(struct dev_object *hdev_obj,
struct io_mgr **mgr);
/*
* ======== dev_get_next ========
* Purpose:
* Retrieve the next Device Object handle from an internal linked list of
* of DEV_OBJECTs maintained by DEV, after having previously called
* dev_get_first() and zero or more dev_get_next
* Parameters:
* hdev_obj: Handle to the device object returned from a previous
* call to dev_get_first() or dev_get_next().
* Returns:
* NULL if there are no further device objects on the list or hdev_obj
* was invalid;
* else the next valid DEV_HOBJECT in the list.
* Requires:
* No calls to dev_create_device or dev_destroy_device (which my modify the
* internal device object list) may occur between calls to dev_get_first
* and dev_get_next.
* Ensures:
* The DEV_HOBJECT returned is valid.
* A subsequent call to dev_get_next will return the next device object in
* the list.
*/
extern struct dev_object *dev_get_next(struct dev_object
*hdev_obj);
/*
* ========= dev_get_msg_mgr ========
* Purpose:
* Retrieve the msg_ctrl Manager Handle from the DevObject.
* Parameters:
* hdev_obj: Handle to the Dev Object
* msg_man: Location where msg_ctrl Manager handle will be returned.
* Returns:
* Requires:
* DEV Initialized.
* Valid hdev_obj.
* node_man != NULL.
* Ensures:
*/
extern void dev_get_msg_mgr(struct dev_object *hdev_obj,
struct msg_mgr **msg_man);
/*
* ========= dev_get_node_manager ========
* Purpose:
* Retrieve the Node Manager Handle from the DevObject. It is an
* accessor function
* Parameters:
* hdev_obj: Handle to the Dev Object
* node_man: Location where Handle to the Node Manager will be
* returned..
* Returns:
* 0: Success
* -EFAULT: Invalid Dev Object handle.
* Requires:
* DEV Initialized.
* node_man is not null
* Ensures:
* 0: *node_man contains a handle to a Node manager object.
* else: *node_man is NULL.
*/
extern int dev_get_node_manager(struct dev_object
*hdev_obj,
struct node_mgr **node_man);
/*
* ======== dev_get_symbol ========
* Purpose:
* Get the value of a symbol in the currently loaded program.
* Parameters:
* hdev_obj: Handle to device object created with
* dev_create_device().
* str_sym: Name of symbol to look up.
* pul_value: Ptr to symbol value.
* Returns:
* 0: Success.
* -EFAULT: Invalid hdev_obj.
* -ESPIPE: Symbols couldn not be found or have not been loaded onto
* the board.
* Requires:
* str_sym != NULL.
* pul_value != NULL.
* DEV Initialized.
* Ensures:
* 0: *pul_value contains the symbol value;
*/
extern int dev_get_symbol(struct dev_object *hdev_obj,
const char *str_sym, u32 * pul_value);
/*
* ======== dev_get_bridge_context ========
* Purpose:
* Retrieve the Bridge Context handle, as returned by the
* bridge_dev_create fxn.
* Parameters:
* hdev_obj: Handle to device object created with dev_create_device()
* *phbridge_context: Ptr to location to store context handle.
* Returns:
* 0: Success.
* -EFAULT: Invalid hdev_obj.
* Requires:
* phbridge_context != NULL.
* DEV Initialized.
* Ensures:
* 0: *phbridge_context contains context handle;
* else: *phbridge_context is NULL;
*/
extern int dev_get_bridge_context(struct dev_object *hdev_obj,
struct bridge_dev_context
**phbridge_context);
/*
* ======== dev_insert_proc_object ========
* Purpose:
* Inserts the Processor Object into the List of PROC Objects
* kept in the DEV Object
* Parameters:
* proc_obj: Handle to the Proc Object
* hdev_obj Handle to the Dev Object
* bAttachedNew Specifies if there are already processors attached
* Returns:
* 0: Successfully inserted into the list
* Requires:
* proc_obj is not NULL
* hdev_obj is a valid handle to the DEV.
* DEV Initialized.
* List(of Proc object in Dev) Exists.
* Ensures:
* 0 & the PROC Object is inserted and the list is not empty
* Details:
* If the List of Proc Object is empty bAttachedNew is TRUE, it indicated
* this is the first Processor attaching.
* If it is False, there are already processors attached.
*/
extern int dev_insert_proc_object(struct dev_object
*hdev_obj,
u32 proc_obj,
bool *already_attached);
/*
* ======== dev_remove_proc_object ========
* Purpose:
* Search for and remove a Proc object from the given list maintained
* by the DEV
* Parameters:
* p_proc_object: Ptr to ProcObject to insert.
* dev_obj: Ptr to Dev Object where the list is.
* already_attached: Ptr to return the bool
* Returns:
* 0: If successful.
* -EPERM Failure to Remove the PROC Object from the list
* Requires:
* DevObject is Valid
* proc_obj != 0
* dev_obj->proc_list != NULL
* !LST_IS_EMPTY(dev_obj->proc_list)
* already_attached !=NULL
* Ensures:
* Details:
* List will be deleted when the DEV is destroyed.
*
*/
extern int dev_remove_proc_object(struct dev_object
*hdev_obj, u32 proc_obj);
/*
* ======== dev_notify_clients ========
* Purpose:
* Notify all clients of this device of a change in device status.
* Clients may include multiple users of BRD, as well as CHNL.
* This function is asychronous, and may be called by a timer event
* set up by a watchdog timer.
* Parameters:
* hdev_obj: Handle to device object created with dev_create_device().
* ret: A status word, most likely a BRD_STATUS.
* Returns:
* 0: All registered clients were asynchronously notified.
* -EINVAL: Invalid hdev_obj.
* Requires:
* DEV Initialized.
* Ensures:
* 0: Notifications are queued by the operating system to be
* delivered to clients. This function does not ensure that
* the notifications will ever be delivered.
*/
extern int dev_notify_clients(struct dev_object *hdev_obj, u32 ret);
/*
* ======== dev_remove_device ========
* Purpose:
* Destroys the Device Object created by dev_start_device.
* Parameters:
* dev_node_obj: Device node as it is know to OS.
* Returns:
* 0: If success;
* <error code> Otherwise.
* Requires:
* Ensures:
*/
extern int dev_remove_device(struct cfg_devnode *dev_node_obj);
/*
* ======== dev_set_chnl_mgr ========
* Purpose:
* Set the channel manager for this device.
* Parameters:
* hdev_obj: Handle to device object created with
* dev_create_device().
* hmgr: Handle to a channel manager, or NULL.
* Returns:
* 0: Success.
* -EFAULT: Invalid hdev_obj.
* Requires:
* DEV Initialized.
* Ensures:
*/
extern int dev_set_chnl_mgr(struct dev_object *hdev_obj,
struct chnl_mgr *hmgr);
/*
* ======== dev_set_msg_mgr ========
* Purpose:
* Set the Message manager for this device.
* Parameters:
* hdev_obj: Handle to device object created with dev_create_device().
* hmgr: Handle to a message manager, or NULL.
* Returns:
* Requires:
* DEV Initialized.
* Ensures:
*/
extern void dev_set_msg_mgr(struct dev_object *hdev_obj, struct msg_mgr *hmgr);
/*
* ======== dev_start_device ========
* Purpose:
* Initializes the new device with bridge environment. This involves
* querying CM for allocated resources, querying the registry for
* necessary dsp resources (requested in the INF file), and using this
* information to create a bridge device object.
* Parameters:
* dev_node_obj: Device node as it is know to OS.
* Returns:
* 0: If success;
* <error code> Otherwise.
* Requires:
* DEV initialized.
* Ensures:
*/
extern int dev_start_device(struct cfg_devnode *dev_node_obj);
#endif /* DEV_ */

26
drivers/staging/tidspbridge/include/dspbridge/devdefs.h
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@ -1,26 +0,0 @@
/*
* devdefs.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Definition of common include typedef between dspdefs.h and dev.h. Required
* to break circular dependency between Bridge driver and DEV include files.
*
* Copyright (C) 2008 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef DEVDEFS_
#define DEVDEFS_
/* Bridge Device Object */
struct dev_object;
#endif /* DEVDEFS_ */

186
drivers/staging/tidspbridge/include/dspbridge/disp.h
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@ -1,186 +0,0 @@
/*
* disp.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* DSP/BIOS Bridge Node Dispatcher.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef DISP_
#define DISP_
#include <dspbridge/dbdefs.h>
#include <dspbridge/nodedefs.h>
#include <dspbridge/nodepriv.h>
struct disp_object;
/* Node Dispatcher attributes */
struct disp_attr {
u32 chnl_offset; /* Offset of channel ids reserved for RMS */
/* Size of buffer for sending data to RMS */
u32 chnl_buf_size;
int proc_family; /* eg, 5000 */
int proc_type; /* eg, 5510 */
void *reserved1; /* Reserved for future use. */
u32 reserved2; /* Reserved for future use. */
};
/*
* ======== disp_create ========
* Create a NODE Dispatcher object. This object handles the creation,
* deletion, and execution of nodes on the DSP target, through communication
* with the Resource Manager Server running on the target. Each NODE
* Manager object should have exactly one NODE Dispatcher.
*
* Parameters:
* dispatch_obj: Location to store node dispatcher object on output.
* hdev_obj: Device for this processor.
* disp_attrs: Node dispatcher attributes.
* Returns:
* 0: Success;
* -ENOMEM: Insufficient memory for requested resources.
* -EPERM: Unable to create dispatcher.
* Requires:
* disp_attrs != NULL.
* hdev_obj != NULL.
* dispatch_obj != NULL.
* Ensures:
* 0: IS_VALID(*dispatch_obj).
* error: *dispatch_obj == NULL.
*/
extern int disp_create(struct disp_object **dispatch_obj,
struct dev_object *hdev_obj,
const struct disp_attr *disp_attrs);
/*
* ======== disp_delete ========
* Delete the NODE Dispatcher.
*
* Parameters:
* disp_obj: Node Dispatcher object.
* Returns:
* Requires:
* Valid disp_obj.
* Ensures:
* disp_obj is invalid.
*/
extern void disp_delete(struct disp_object *disp_obj);
/*
* ======== disp_node_change_priority ========
* Change the priority of a node currently running on the target.
*
* Parameters:
* disp_obj: Node Dispatcher object.
* hnode: Node object representing a node currently
* allocated or running on the DSP.
* ulFxnAddress: Address of RMS function for changing priority.
* node_env: Address of node's environment structure.
* prio: New priority level to set node's priority to.
* Returns:
* 0: Success.
* -ETIME: A timeout occurred before the DSP responded.
* Requires:
* Valid disp_obj.
* hnode != NULL.
* Ensures:
*/
extern int disp_node_change_priority(struct disp_object
*disp_obj,
struct node_object *hnode,
u32 rms_fxn,
nodeenv node_env, s32 prio);
/*
* ======== disp_node_create ========
* Create a node on the DSP by remotely calling the node's create function.
*
* Parameters:
* disp_obj: Node Dispatcher object.
* hnode: Node handle obtained from node_allocate().
* ul_fxn_addr: Address or RMS create node function.
* ul_create_fxn: Address of node's create function.
* pargs: Arguments to pass to RMS node create function.
* node_env: Location to store node environment pointer on
* output.
* Returns:
* 0: Success.
* -ETIME: A timeout occurred before the DSP responded.
* -EPERM: A failure occurred, unable to create node.
* Requires:
* Valid disp_obj.
* pargs != NULL.
* hnode != NULL.
* node_env != NULL.
* node_get_type(hnode) != NODE_DEVICE.
* Ensures:
*/
extern int disp_node_create(struct disp_object *disp_obj,
struct node_object *hnode,
u32 rms_fxn,
u32 ul_create_fxn,
const struct node_createargs
*pargs, nodeenv *node_env);
/*
* ======== disp_node_delete ========
* Delete a node on the DSP by remotely calling the node's delete function.
*
* Parameters:
* disp_obj: Node Dispatcher object.
* hnode: Node object representing a node currently
* loaded on the DSP.
* ul_fxn_addr: Address or RMS delete node function.
* ul_delete_fxn: Address of node's delete function.
* node_env: Address of node's environment structure.
* Returns:
* 0: Success.
* -ETIME: A timeout occurred before the DSP responded.
* Requires:
* Valid disp_obj.
* hnode != NULL.
* Ensures:
*/
extern int disp_node_delete(struct disp_object *disp_obj,
struct node_object *hnode,
u32 rms_fxn,
u32 ul_delete_fxn, nodeenv node_env);
/*
* ======== disp_node_run ========
* Start execution of a node's execute phase, or resume execution of a node
* that has been suspended (via DISP_NodePause()) on the DSP.
*
* Parameters:
* disp_obj: Node Dispatcher object.
* hnode: Node object representing a node to be executed
* on the DSP.
* ul_fxn_addr: Address or RMS node execute function.
* ul_execute_fxn: Address of node's execute function.
* node_env: Address of node's environment structure.
* Returns:
* 0: Success.
* -ETIME: A timeout occurred before the DSP responded.
* Requires:
* Valid disp_obj.
* hnode != NULL.
* Ensures:
*/
extern int disp_node_run(struct disp_object *disp_obj,
struct node_object *hnode,
u32 rms_fxn,
u32 ul_execute_fxn, nodeenv node_env);
#endif /* DISP_ */

71
drivers/staging/tidspbridge/include/dspbridge/dmm.h
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@ -1,71 +0,0 @@
/*
* dmm.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* The Dynamic Memory Mapping(DMM) module manages the DSP Virtual address
* space that can be directly mapped to any MPU buffer or memory region.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef DMM_
#define DMM_
#include <dspbridge/dbdefs.h>
struct dmm_object;
/* DMM attributes used in dmm_create() */
struct dmm_mgrattrs {
u32 reserved;
};
#define DMMPOOLSIZE 0x4000000
/*
* ======== dmm_get_handle ========
* Purpose:
* Return the dynamic memory manager object for this device.
* This is typically called from the client process.
*/
extern int dmm_get_handle(void *hprocessor,
struct dmm_object **dmm_manager);
extern int dmm_reserve_memory(struct dmm_object *dmm_mgr,
u32 size, u32 *prsv_addr);
extern int dmm_un_reserve_memory(struct dmm_object *dmm_mgr,
u32 rsv_addr);
extern int dmm_map_memory(struct dmm_object *dmm_mgr, u32 addr,
u32 size);
extern int dmm_un_map_memory(struct dmm_object *dmm_mgr,
u32 addr, u32 *psize);
extern int dmm_destroy(struct dmm_object *dmm_mgr);
extern int dmm_delete_tables(struct dmm_object *dmm_mgr);
extern int dmm_create(struct dmm_object **dmm_manager,
struct dev_object *hdev_obj,
const struct dmm_mgrattrs *mgr_attrts);
extern int dmm_create_tables(struct dmm_object *dmm_mgr,
u32 addr, u32 size);
#ifdef DSP_DMM_DEBUG
u32 dmm_mem_map_dump(struct dmm_object *dmm_mgr);
#endif
#endif /* DMM_ */

468
drivers/staging/tidspbridge/include/dspbridge/drv.h
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@ -1,468 +0,0 @@
/*
* drv.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* DRV Resource allocation module. Driver Object gets Created
* at the time of Loading. It holds the List of Device Objects
* in the system.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef DRV_
#define DRV_
#include <dspbridge/devdefs.h>
#include <linux/idr.h>
/* Bridge Driver Object */
struct drv_object;
/* Provide the DSP Internal memory windows that can be accessed from L3 address
* space */
#define OMAP_GEM_BASE 0x107F8000
#define OMAP_DSP_SIZE 0x00720000
/* MEM1 is L2 RAM + L2 Cache space */
#define OMAP_DSP_MEM1_BASE 0x5C7F8000
#define OMAP_DSP_MEM1_SIZE 0x18000
/* MEM2 is L1P RAM/CACHE space */
#define OMAP_DSP_MEM2_BASE 0x5CE00000
#define OMAP_DSP_MEM2_SIZE 0x8000
/* MEM3 is L1D RAM/CACHE space */
#define OMAP_DSP_MEM3_BASE 0x5CF04000
#define OMAP_DSP_MEM3_SIZE 0x14000
#define OMAP_PER_CM_BASE 0x48005000
#define OMAP_PER_CM_SIZE 0x1000
#define OMAP_PER_PRM_BASE 0x48307000
#define OMAP_PER_PRM_SIZE 0x1000
#define OMAP_CORE_PRM_BASE 0x48306A00
#define OMAP_CORE_PRM_SIZE 0x1000
#define OMAP_DMMU_BASE 0x5D000000
#define OMAP_DMMU_SIZE 0x1000
/* GPP PROCESS CLEANUP Data structures */
/* New structure (member of process context) abstracts NODE resource info */
struct node_res_object {
void *node;
s32 node_allocated; /* Node status */
s32 heap_allocated; /* Heap status */
s32 streams_allocated; /* Streams status */
int id;
};
/* used to cache dma mapping information */
struct bridge_dma_map_info {
/* direction of DMA in action, or DMA_NONE */
enum dma_data_direction dir;
/* number of elements requested by us */
int num_pages;
/* number of elements returned from dma_map_sg */
int sg_num;
/* list of buffers used in this DMA action */
struct scatterlist *sg;
};
/* Used for DMM mapped memory accounting */
struct dmm_map_object {
struct list_head link;
u32 dsp_addr;
u32 mpu_addr;
u32 size;
u32 num_usr_pgs;
struct page **pages;
struct bridge_dma_map_info dma_info;
};
/* Used for DMM reserved memory accounting */
struct dmm_rsv_object {
struct list_head link;
u32 dsp_reserved_addr;
};
/* New structure (member of process context) abstracts stream resource info */
struct strm_res_object {
s32 stream_allocated; /* Stream status */
void *stream;
u32 num_bufs;
u32 dir;
int id;
};
/* Overall Bridge process resource usage state */
enum gpp_proc_res_state {
PROC_RES_ALLOCATED,
PROC_RES_FREED
};
/* Bridge Data */
struct drv_data {
char *base_img;
s32 shm_size;
int tc_wordswapon;
void *drv_object;
void *dev_object;
void *mgr_object;
};
/* Process Context */
struct process_context {
/* Process State */
enum gpp_proc_res_state res_state;
/* Handle to Processor */
void *processor;
/* DSP Node resources */
struct idr *node_id;
/* DMM mapped memory resources */
struct list_head dmm_map_list;
spinlock_t dmm_map_lock;
/* DMM reserved memory resources */
struct list_head dmm_rsv_list;
spinlock_t dmm_rsv_lock;
/* Stream resources */
struct idr *stream_id;
};
/*
* ======== drv_create ========
* Purpose:
* Creates the Driver Object. This is done during the driver loading.
* There is only one Driver Object in the DSP/BIOS Bridge.
* Parameters:
* drv_obj: Location to store created DRV Object handle.
* Returns:
* 0: Success
* -ENOMEM: Failed in Memory allocation
* -EPERM: General Failure
* Requires:
* DRV Initialized (refs > 0 )
* drv_obj != NULL.
* Ensures:
* 0: - *drv_obj is a valid DRV interface to the device.
* - List of DevObject Created and Initialized.
* - List of dev_node String created and initialized.
* - Registry is updated with the DRV Object.
* !0: DRV Object not created
* Details:
* There is one Driver Object for the Driver representing
* the driver itself. It contains the list of device
* Objects and the list of Device Extensions in the system.
* Also it can hold other necessary
* information in its storage area.
*/
extern int drv_create(struct drv_object **drv_obj);
/*
* ======== drv_destroy ========
* Purpose:
* destroys the Dev Object list, DrvExt list
* and destroy the DRV object
* Called upon driver unLoading.or unsuccessful loading of the driver.
* Parameters:
* driver_obj: Handle to Driver object .
* Returns:
* 0: Success.
* -EPERM: Failed to destroy DRV Object
* Requires:
* DRV Initialized (cRegs > 0 )
* hdrv_obj is not NULL and a valid DRV handle .
* List of DevObject is Empty.
* List of DrvExt is Empty
* Ensures:
* 0: - DRV Object destroyed and hdrv_obj is not a valid
* DRV handle.
* - Registry is updated with "0" as the DRV Object.
*/
extern int drv_destroy(struct drv_object *driver_obj);
/*
* ======== drv_get_first_dev_object ========
* Purpose:
* Returns the Ptr to the FirstDev Object in the List
* Parameters:
* Requires:
* DRV Initialized
* Returns:
* dw_dev_object: Ptr to the First Dev Object as a u32
* 0 if it fails to retrieve the First Dev Object
* Ensures:
*/
extern u32 drv_get_first_dev_object(void);
/*
* ======== drv_get_first_dev_extension ========
* Purpose:
* Returns the Ptr to the First Device Extension in the List
* Parameters:
* Requires:
* DRV Initialized
* Returns:
* dw_dev_extension: Ptr to the First Device Extension as a u32
* 0: Failed to Get the Device Extension
* Ensures:
*/
extern u32 drv_get_first_dev_extension(void);
/*
* ======== drv_get_dev_object ========
* Purpose:
* Given a index, returns a handle to DevObject from the list
* Parameters:
* hdrv_obj: Handle to the Manager
* device_obj: Location to store the Dev Handle
* Requires:
* DRV Initialized
* index >= 0
* hdrv_obj is not NULL and Valid DRV Object
* device_obj is not NULL
* Device Object List not Empty
* Returns:
* 0: Success
* -EPERM: Failed to Get the Dev Object
* Ensures:
* 0: *device_obj != NULL
* -EPERM: *device_obj = NULL
*/
extern int drv_get_dev_object(u32 index,
struct drv_object *hdrv_obj,
struct dev_object **device_obj);
/*
* ======== drv_get_next_dev_object ========
* Purpose:
* Returns the Ptr to the Next Device Object from the the List
* Parameters:
* hdev_obj: Handle to the Device Object
* Requires:
* DRV Initialized
* hdev_obj != 0
* Returns:
* dw_dev_object: Ptr to the Next Dev Object as a u32
* 0: If it fail to get the next Dev Object.
* Ensures:
*/
extern u32 drv_get_next_dev_object(u32 hdev_obj);
/*
* ======== drv_get_next_dev_extension ========
* Purpose:
* Returns the Ptr to the Next Device Extension from the the List
* Parameters:
* dev_extension: Handle to the Device Extension
* Requires:
* DRV Initialized
* dev_extension != 0.
* Returns:
* dw_dev_extension: Ptr to the Next Dev Extension
* 0: If it fail to Get the next Dev Extension
* Ensures:
*/
extern u32 drv_get_next_dev_extension(u32 dev_extension);
/*
* ======== drv_insert_dev_object ========
* Purpose:
* Insert a DeviceObject into the list of Driver object.
* Parameters:
* driver_obj: Handle to DrvObject
* hdev_obj: Handle to DeviceObject to insert.
* Returns:
* 0: If successful.
* -EPERM: General Failure:
* Requires:
* hdrv_obj != NULL and Valid DRV Handle.
* hdev_obj != NULL.
* Ensures:
* 0: Device Object is inserted and the List is not empty.
*/
extern int drv_insert_dev_object(struct drv_object *driver_obj,
struct dev_object *hdev_obj);
/*
* ======== drv_remove_dev_object ========
* Purpose:
* Search for and remove a Device object from the given list of Device Obj
* objects.
* Parameters:
* driver_obj: Handle to DrvObject
* hdev_obj: Handle to DevObject to Remove
* Returns:
* 0: Success.
* -EPERM: Unable to find dev_obj.
* Requires:
* hdrv_obj != NULL and a Valid DRV Handle.
* hdev_obj != NULL.
* List exists and is not empty.
* Ensures:
* List either does not exist (NULL), or is not empty if it does exist.
*/
extern int drv_remove_dev_object(struct drv_object *driver_obj,
struct dev_object *hdev_obj);
/*
* ======== drv_request_resources ========
* Purpose:
* Assigns the Resources or Releases them.
* Parameters:
* dw_context: Path to the driver Registry Key.
* dev_node_strg: Ptr to dev_node String stored in the Device Ext.
* Returns:
* TRUE if success; FALSE otherwise.
* Requires:
* Ensures:
* The Resources are assigned based on Bus type.
* The hardware is initialized. Resource information is
* gathered from the Registry(ISA, PCMCIA)or scanned(PCI)
* Resource structure is stored in the registry which will be
* later used by the CFG module.
*/
extern int drv_request_resources(u32 dw_context,
u32 *dev_node_strg);
/*
* ======== drv_release_resources ========
* Purpose:
* Assigns the Resources or Releases them.
* Parameters:
* dw_context: Path to the driver Registry Key.
* hdrv_obj: Handle to the Driver Object.
* Returns:
* TRUE if success; FALSE otherwise.
* Requires:
* Ensures:
* The Resources are released based on Bus type.
* Resource structure is deleted from the registry
*/
extern int drv_release_resources(u32 dw_context,
struct drv_object *hdrv_obj);
/**
* drv_request_bridge_res_dsp() - Reserves shared memory for bridge.
* @phost_resources: pointer to host resources.
*/
int drv_request_bridge_res_dsp(void **phost_resources);
#ifdef CONFIG_TIDSPBRIDGE_RECOVERY
void bridge_recover_schedule(void);
#endif
/*
* ======== mem_ext_phys_pool_init ========
* Purpose:
* Uses the physical memory chunk passed for internal consistent memory
* allocations.
* physical address based on the page frame address.
* Parameters:
* pool_phys_base starting address of the physical memory pool.
* pool_size size of the physical memory pool.
* Returns:
* none.
* Requires:
* - MEM initialized.
* - valid physical address for the base and size > 0
*/
extern void mem_ext_phys_pool_init(u32 pool_phys_base, u32 pool_size);
/*
* ======== mem_ext_phys_pool_release ========
*/
extern void mem_ext_phys_pool_release(void);
/* ======== mem_alloc_phys_mem ========
* Purpose:
* Allocate physically contiguous, uncached memory
* Parameters:
* byte_size: Number of bytes to allocate.
* align_mask: Alignment Mask.
* physical_address: Physical address of allocated memory.
* Returns:
* Pointer to a block of memory;
* NULL if memory couldn't be allocated, or if byte_size == 0.
* Requires:
* MEM initialized.
* Ensures:
* The returned pointer, if not NULL, points to a valid memory block of
* the size requested. Returned physical address refers to physical
* location of memory.
*/
extern void *mem_alloc_phys_mem(u32 byte_size,
u32 align_mask, u32 *physical_address);
/*
* ======== mem_free_phys_mem ========
* Purpose:
* Free the given block of physically contiguous memory.
* Parameters:
* virtual_address: Pointer to virtual memory region allocated
* by mem_alloc_phys_mem().
* physical_address: Pointer to physical memory region allocated
* by mem_alloc_phys_mem().
* byte_size: Size of the memory region allocated by mem_alloc_phys_mem().
* Returns:
* Requires:
* MEM initialized.
* virtual_address is a valid memory address returned by
* mem_alloc_phys_mem()
* Ensures:
* virtual_address is no longer a valid pointer to memory.
*/
extern void mem_free_phys_mem(void *virtual_address,
u32 physical_address, u32 byte_size);
/*
* ======== MEM_LINEAR_ADDRESS ========
* Purpose:
* Get the linear address corresponding to the given physical address.
* Parameters:
* phys_addr: Physical address to be mapped.
* byte_size: Number of bytes in physical range to map.
* Returns:
* The corresponding linear address, or NULL if unsuccessful.
* Requires:
* MEM initialized.
* Ensures:
* Notes:
* If valid linear address is returned, be sure to call
* MEM_UNMAP_LINEAR_ADDRESS().
*/
#define MEM_LINEAR_ADDRESS(phy_addr, byte_size) phy_addr
/*
* ======== MEM_UNMAP_LINEAR_ADDRESS ========
* Purpose:
* Unmap the linear address mapped in MEM_LINEAR_ADDRESS.
* Parameters:
* base_addr: Ptr to mapped memory (as returned by MEM_LINEAR_ADDRESS()).
* Returns:
* Requires:
* - MEM initialized.
* - base_addr is a valid linear address mapped in MEM_LINEAR_ADDRESS.
* Ensures:
* - base_addr no longer points to a valid linear address.
*/
#define MEM_UNMAP_LINEAR_ADDRESS(base_addr) {}
#endif /* DRV_ */

467
drivers/staging/tidspbridge/include/dspbridge/dspapi-ioctl.h
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@ -1,467 +0,0 @@
/*
* dspapi-ioctl.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Contains structures and commands that are used for interaction
* between the DDSP API and Bridge driver.
*
* Copyright (C) 2008 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef DSPAPIIOCTL_
#define DSPAPIIOCTL_
#include <dspbridge/cmm.h>
#include <dspbridge/strmdefs.h>
#include <dspbridge/dbdcd.h>
union trapped_args {
/* MGR Module */
struct {
u32 node_id;
struct dsp_ndbprops __user *ndb_props;
u32 ndb_props_size;
u32 __user *num_nodes;
} args_mgr_enumnode_info;
struct {
u32 processor_id;
struct dsp_processorinfo __user *processor_info;
u32 processor_info_size;
u32 __user *num_procs;
} args_mgr_enumproc_info;
struct {
struct dsp_uuid *uuid_obj;
enum dsp_dcdobjtype obj_type;
char *sz_path_name;
} args_mgr_registerobject;
struct {
struct dsp_uuid *uuid_obj;
enum dsp_dcdobjtype obj_type;
} args_mgr_unregisterobject;
struct {
struct dsp_notification __user *__user *anotifications;
u32 count;
u32 __user *index;
u32 timeout;
} args_mgr_wait;
/* PROC Module */
struct {
u32 processor_id;
struct dsp_processorattrin __user *attr_in;
void *__user *ph_processor;
} args_proc_attach;
struct {
void *processor;
u32 cmd;
struct dsp_cbdata __user *args;
} args_proc_ctrl;
struct {
void *processor;
} args_proc_detach;
struct {
void *processor;
void *__user *node_tab;
u32 node_tab_size;
u32 __user *num_nodes;
u32 __user *allocated;
} args_proc_enumnode_info;
struct {
void *processor;
u32 resource_type;
struct dsp_resourceinfo *resource_info;
u32 resource_info_size;
} args_proc_enumresources;
struct {
void *processor;
struct dsp_processorstate __user *proc_state_obj;
u32 state_info_size;
} args_proc_getstate;
struct {
void *processor;
u8 __user *buf;
u8 __user *size;
u32 max_size;
} args_proc_gettrace;
struct {
void *processor;
s32 argc_index;
char __user *__user *user_args;
char *__user *user_envp;
} args_proc_load;
struct {
void *processor;
u32 event_mask;
u32 notify_type;
struct dsp_notification __user *notification;
} args_proc_register_notify;
struct {
void *processor;
u32 size;
void *__user *rsv_addr;
} args_proc_rsvmem;
struct {
void *processor;
u32 size;
void *rsv_addr;
} args_proc_unrsvmem;
struct {
void *processor;
void *mpu_addr;
u32 size;
void *req_addr;
void *__user *map_addr;
u32 map_attr;
} args_proc_mapmem;
struct {
void *processor;
u32 size;
void *map_addr;
} args_proc_unmapmem;
struct {
void *processor;
void *mpu_addr;
u32 size;
u32 dir;
} args_proc_dma;
struct {
void *processor;
void *mpu_addr;
u32 size;
u32 flags;
} args_proc_flushmemory;
struct {
void *processor;
void *mpu_addr;
u32 size;
} args_proc_invalidatememory;
/* NODE Module */
struct {
void *processor;
struct dsp_uuid __user *node_id_ptr;
struct dsp_cbdata __user *args;
struct dsp_nodeattrin __user *attr_in;
void *__user *node;
} args_node_allocate;
struct {
void *node;
u32 size;
struct dsp_bufferattr __user *attr;
u8 *__user *buffer;
} args_node_allocmsgbuf;
struct {
void *node;
s32 prio;
} args_node_changepriority;
struct {
void *node;
u32 stream_id;
void *other_node;
u32 other_stream;
struct dsp_strmattr __user *attrs;
struct dsp_cbdata __user *conn_param;
} args_node_connect;
struct {
void *node;
} args_node_create;
struct {
void *node;
} args_node_delete;
struct {
void *node;
struct dsp_bufferattr __user *attr;
u8 *buffer;
} args_node_freemsgbuf;
struct {
void *node;
struct dsp_nodeattr __user *attr;
u32 attr_size;
} args_node_getattr;
struct {
void *node;
struct dsp_msg __user *message;
u32 timeout;
} args_node_getmessage;
struct {
void *node;
} args_node_pause;
struct {
void *node;
struct dsp_msg __user *message;
u32 timeout;
} args_node_putmessage;
struct {
void *node;
u32 event_mask;
u32 notify_type;
struct dsp_notification __user *notification;
} args_node_registernotify;
struct {
void *node;
} args_node_run;
struct {
void *node;
int __user *status;
} args_node_terminate;
struct {
void *processor;
struct dsp_uuid __user *node_id_ptr;
struct dsp_ndbprops __user *node_props;
} args_node_getuuidprops;
/* STRM module */
struct {
void *stream;
u32 size;
u8 *__user *ap_buffer;
u32 num_bufs;
} args_strm_allocatebuffer;
struct {
void *stream;
} args_strm_close;
struct {
void *stream;
u8 *__user *ap_buffer;
u32 num_bufs;
} args_strm_freebuffer;
struct {
void *stream;
void **event;
} args_strm_geteventhandle;
struct {
void *stream;
struct stream_info __user *stream_info;
u32 stream_info_size;
} args_strm_getinfo;
struct {
void *stream;
bool flush_flag;
} args_strm_idle;
struct {
void *stream;
u8 *buffer;
u32 bytes;
u32 buf_size;
u32 arg;
} args_strm_issue;
struct {
void *node;
u32 direction;
u32 index;
struct strm_attr __user *attr_in;
void *__user *stream;
} args_strm_open;
struct {
void *stream;
u8 *__user *buf_ptr;
u32 __user *bytes;
u32 __user *buf_size_ptr;
u32 __user *arg;
} args_strm_reclaim;
struct {
void *stream;
u32 event_mask;
u32 notify_type;
struct dsp_notification __user *notification;
} args_strm_registernotify;
struct {
void *__user *stream_tab;
u32 strm_num;
u32 __user *mask;
u32 timeout;
} args_strm_select;
/* CMM Module */
struct {
struct cmm_object *cmm_mgr;
u32 size;
struct cmm_attrs *attrs;
void **buf_va;
} args_cmm_allocbuf;
struct {
struct cmm_object *cmm_mgr;
void *buf_pa;
u32 seg_id;
} args_cmm_freebuf;
struct {
void *processor;
struct cmm_object *__user *cmm_mgr;
} args_cmm_gethandle;
struct {
struct cmm_object *cmm_mgr;
struct cmm_info __user *cmm_info_obj;
} args_cmm_getinfo;
/* UTIL module */
struct {
s32 util_argc;
char **argv;
} args_util_testdll;
};
/*
* Dspbridge Ioctl numbering scheme
*
* 7 0
* ---------------------------------
* | Module | Ioctl Number |
* ---------------------------------
* | x | x | x | 0 | 0 | 0 | 0 | 0 |
* ---------------------------------
*/
/* Ioctl driver identifier */
#define DB 0xDB
/*
* Following are used to distinguish between module ioctls, this is needed
* in case new ioctls are introduced.
*/
#define DB_MODULE_MASK 0xE0
#define DB_IOC_MASK 0x1F
/* Ioctl module masks */
#define DB_MGR 0x0
#define DB_PROC 0x20
#define DB_NODE 0x40
#define DB_STRM 0x60
#define DB_CMM 0x80
#define DB_MODULE_SHIFT 5
/* Used to calculate the ioctl per dspbridge module */
#define DB_IOC(module, num) \
(((module) & DB_MODULE_MASK) | ((num) & DB_IOC_MASK))
/* Used to get dspbridge ioctl module */
#define DB_GET_MODULE(cmd) ((cmd) & DB_MODULE_MASK)
/* Used to get dspbridge ioctl number */
#define DB_GET_IOC(cmd) ((cmd) & DB_IOC_MASK)
/* TODO: Remove deprecated and not implemented */
/* MGR Module */
#define MGR_ENUMNODE_INFO _IOWR(DB, DB_IOC(DB_MGR, 0), unsigned long)
#define MGR_ENUMPROC_INFO _IOWR(DB, DB_IOC(DB_MGR, 1), unsigned long)
#define MGR_REGISTEROBJECT _IOWR(DB, DB_IOC(DB_MGR, 2), unsigned long)
#define MGR_UNREGISTEROBJECT _IOWR(DB, DB_IOC(DB_MGR, 3), unsigned long)
#define MGR_WAIT _IOWR(DB, DB_IOC(DB_MGR, 4), unsigned long)
/* MGR_GET_PROC_RES Deprecated */
#define MGR_GET_PROC_RES _IOR(DB, DB_IOC(DB_MGR, 5), unsigned long)
/* PROC Module */
#define PROC_ATTACH _IOWR(DB, DB_IOC(DB_PROC, 0), unsigned long)
#define PROC_CTRL _IOR(DB, DB_IOC(DB_PROC, 1), unsigned long)
/* PROC_DETACH Deprecated */
#define PROC_DETACH _IOR(DB, DB_IOC(DB_PROC, 2), unsigned long)
#define PROC_ENUMNODE _IOWR(DB, DB_IOC(DB_PROC, 3), unsigned long)
#define PROC_ENUMRESOURCES _IOWR(DB, DB_IOC(DB_PROC, 4), unsigned long)
#define PROC_GET_STATE _IOWR(DB, DB_IOC(DB_PROC, 5), unsigned long)
#define PROC_GET_TRACE _IOWR(DB, DB_IOC(DB_PROC, 6), unsigned long)
#define PROC_LOAD _IOW(DB, DB_IOC(DB_PROC, 7), unsigned long)
#define PROC_REGISTERNOTIFY _IOWR(DB, DB_IOC(DB_PROC, 8), unsigned long)
#define PROC_START _IOW(DB, DB_IOC(DB_PROC, 9), unsigned long)
#define PROC_RSVMEM _IOWR(DB, DB_IOC(DB_PROC, 10), unsigned long)
#define PROC_UNRSVMEM _IOW(DB, DB_IOC(DB_PROC, 11), unsigned long)
#define PROC_MAPMEM _IOWR(DB, DB_IOC(DB_PROC, 12), unsigned long)
#define PROC_UNMAPMEM _IOR(DB, DB_IOC(DB_PROC, 13), unsigned long)
#define PROC_FLUSHMEMORY _IOW(DB, DB_IOC(DB_PROC, 14), unsigned long)
#define PROC_STOP _IOWR(DB, DB_IOC(DB_PROC, 15), unsigned long)
#define PROC_INVALIDATEMEMORY _IOW(DB, DB_IOC(DB_PROC, 16), unsigned long)
#define PROC_BEGINDMA _IOW(DB, DB_IOC(DB_PROC, 17), unsigned long)
#define PROC_ENDDMA _IOW(DB, DB_IOC(DB_PROC, 18), unsigned long)
/* NODE Module */
#define NODE_ALLOCATE _IOWR(DB, DB_IOC(DB_NODE, 0), unsigned long)
#define NODE_ALLOCMSGBUF _IOWR(DB, DB_IOC(DB_NODE, 1), unsigned long)
#define NODE_CHANGEPRIORITY _IOW(DB, DB_IOC(DB_NODE, 2), unsigned long)
#define NODE_CONNECT _IOW(DB, DB_IOC(DB_NODE, 3), unsigned long)
#define NODE_CREATE _IOW(DB, DB_IOC(DB_NODE, 4), unsigned long)
#define NODE_DELETE _IOW(DB, DB_IOC(DB_NODE, 5), unsigned long)
#define NODE_FREEMSGBUF _IOW(DB, DB_IOC(DB_NODE, 6), unsigned long)
#define NODE_GETATTR _IOWR(DB, DB_IOC(DB_NODE, 7), unsigned long)
#define NODE_GETMESSAGE _IOWR(DB, DB_IOC(DB_NODE, 8), unsigned long)
#define NODE_PAUSE _IOW(DB, DB_IOC(DB_NODE, 9), unsigned long)
#define NODE_PUTMESSAGE _IOW(DB, DB_IOC(DB_NODE, 10), unsigned long)
#define NODE_REGISTERNOTIFY _IOWR(DB, DB_IOC(DB_NODE, 11), unsigned long)
#define NODE_RUN _IOW(DB, DB_IOC(DB_NODE, 12), unsigned long)
#define NODE_TERMINATE _IOWR(DB, DB_IOC(DB_NODE, 13), unsigned long)
#define NODE_GETUUIDPROPS _IOWR(DB, DB_IOC(DB_NODE, 14), unsigned long)
/* STRM Module */
#define STRM_ALLOCATEBUFFER _IOWR(DB, DB_IOC(DB_STRM, 0), unsigned long)
#define STRM_CLOSE _IOW(DB, DB_IOC(DB_STRM, 1), unsigned long)
#define STRM_FREEBUFFER _IOWR(DB, DB_IOC(DB_STRM, 2), unsigned long)
#define STRM_GETEVENTHANDLE _IO(DB, DB_IOC(DB_STRM, 3)) /* Not Impl'd */
#define STRM_GETINFO _IOWR(DB, DB_IOC(DB_STRM, 4), unsigned long)
#define STRM_IDLE _IOW(DB, DB_IOC(DB_STRM, 5), unsigned long)
#define STRM_ISSUE _IOW(DB, DB_IOC(DB_STRM, 6), unsigned long)
#define STRM_OPEN _IOWR(DB, DB_IOC(DB_STRM, 7), unsigned long)
#define STRM_RECLAIM _IOWR(DB, DB_IOC(DB_STRM, 8), unsigned long)
#define STRM_REGISTERNOTIFY _IOWR(DB, DB_IOC(DB_STRM, 9), unsigned long)
#define STRM_SELECT _IOWR(DB, DB_IOC(DB_STRM, 10), unsigned long)
/* CMM Module */
#define CMM_ALLOCBUF _IO(DB, DB_IOC(DB_CMM, 0)) /* Not Impl'd */
#define CMM_FREEBUF _IO(DB, DB_IOC(DB_CMM, 1)) /* Not Impl'd */
#define CMM_GETHANDLE _IOR(DB, DB_IOC(DB_CMM, 2), unsigned long)
#define CMM_GETINFO _IOR(DB, DB_IOC(DB_CMM, 3), unsigned long)
#endif /* DSPAPIIOCTL_ */

167
drivers/staging/tidspbridge/include/dspbridge/dspapi.h
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@ -1,167 +0,0 @@
/*
* dspapi.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Includes the wrapper functions called directly by the
* DeviceIOControl interface.
*
* Notes:
* Bridge services exported to Bridge driver are initialized by the DSPAPI on
* behalf of the Bridge driver. Bridge driver must not call module Init/Exit
* functions.
*
* To ensure Bridge driver binary compatibility across different platforms,
* for the same processor, a Bridge driver must restrict its usage of system
* services to those exported by the DSPAPI library.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef DSPAPI_
#define DSPAPI_
#include <dspbridge/dspapi-ioctl.h>
/* This BRD API Library Version: */
#define BRD_API_MAJOR_VERSION (u32)8 /* .8x - Alpha, .9x - Beta, 1.x FCS */
#define BRD_API_MINOR_VERSION (u32)0
/*
* ======== api_call_dev_ioctl ========
* Purpose:
* Call the (wrapper) function for the corresponding API IOCTL.
* Parameters:
* cmd: IOCTL id, base 0.
* args: Argument structure.
* result:
* Returns:
* 0 if command called; -EINVAL if command not in IOCTL
* table.
* Requires:
* Ensures:
*/
extern int api_call_dev_ioctl(unsigned int cmd,
union trapped_args *args,
u32 *result, void *pr_ctxt);
/*
* ======== api_init ========
* Purpose:
* Initialize modules used by Bridge API.
* This procedure is called when the driver is loaded.
* Parameters:
* Returns:
* TRUE if success; FALSE otherwise.
* Requires:
* Ensures:
*/
extern bool api_init(void);
/*
* ======== api_init_complete2 ========
* Purpose:
* Perform any required bridge initialization which cannot
* be performed in api_init() or dev_start_device() due
* to the fact that some services are not yet
* completely initialized.
* Parameters:
* Returns:
* 0: Allow this device to load
* -EPERM: Failure.
* Requires:
* Bridge API initialized.
* Ensures:
*/
extern int api_init_complete2(void);
/*
* ======== api_exit ========
* Purpose:
* Exit all modules initialized in api_init(void).
* This procedure is called when the driver is unloaded.
* Parameters:
* Returns:
* Requires:
* api_init(void) was previously called.
* Ensures:
* Resources acquired in api_init(void) are freed.
*/
extern void api_exit(void);
/* MGR wrapper functions */
extern u32 mgrwrap_enum_node_info(union trapped_args *args, void *pr_ctxt);
extern u32 mgrwrap_enum_proc_info(union trapped_args *args, void *pr_ctxt);
extern u32 mgrwrap_register_object(union trapped_args *args, void *pr_ctxt);
extern u32 mgrwrap_unregister_object(union trapped_args *args, void *pr_ctxt);
extern u32 mgrwrap_wait_for_bridge_events(union trapped_args *args,
void *pr_ctxt);
extern u32 mgrwrap_get_process_resources_info(union trapped_args *args,
void *pr_ctxt);
/* CPRC (Processor) wrapper Functions */
extern u32 procwrap_attach(union trapped_args *args, void *pr_ctxt);
extern u32 procwrap_ctrl(union trapped_args *args, void *pr_ctxt);
extern u32 procwrap_detach(union trapped_args *args, void *pr_ctxt);
extern u32 procwrap_enum_node_info(union trapped_args *args, void *pr_ctxt);
extern u32 procwrap_enum_resources(union trapped_args *args, void *pr_ctxt);
extern u32 procwrap_get_state(union trapped_args *args, void *pr_ctxt);
extern u32 procwrap_get_trace(union trapped_args *args, void *pr_ctxt);
extern u32 procwrap_load(union trapped_args *args, void *pr_ctxt);
extern u32 procwrap_register_notify(union trapped_args *args, void *pr_ctxt);
extern u32 procwrap_start(union trapped_args *args, void *pr_ctxt);
extern u32 procwrap_reserve_memory(union trapped_args *args, void *pr_ctxt);
extern u32 procwrap_un_reserve_memory(union trapped_args *args, void *pr_ctxt);
extern u32 procwrap_map(union trapped_args *args, void *pr_ctxt);
extern u32 procwrap_un_map(union trapped_args *args, void *pr_ctxt);
extern u32 procwrap_flush_memory(union trapped_args *args, void *pr_ctxt);
extern u32 procwrap_stop(union trapped_args *args, void *pr_ctxt);
extern u32 procwrap_invalidate_memory(union trapped_args *args, void *pr_ctxt);
extern u32 procwrap_begin_dma(union trapped_args *args, void *pr_ctxt);
extern u32 procwrap_end_dma(union trapped_args *args, void *pr_ctxt);
/* NODE wrapper functions */
extern u32 nodewrap_allocate(union trapped_args *args, void *pr_ctxt);
extern u32 nodewrap_alloc_msg_buf(union trapped_args *args, void *pr_ctxt);
extern u32 nodewrap_change_priority(union trapped_args *args, void *pr_ctxt);
extern u32 nodewrap_connect(union trapped_args *args, void *pr_ctxt);
extern u32 nodewrap_create(union trapped_args *args, void *pr_ctxt);
extern u32 nodewrap_delete(union trapped_args *args, void *pr_ctxt);
extern u32 nodewrap_free_msg_buf(union trapped_args *args, void *pr_ctxt);
extern u32 nodewrap_get_attr(union trapped_args *args, void *pr_ctxt);
extern u32 nodewrap_get_message(union trapped_args *args, void *pr_ctxt);
extern u32 nodewrap_pause(union trapped_args *args, void *pr_ctxt);
extern u32 nodewrap_put_message(union trapped_args *args, void *pr_ctxt);
extern u32 nodewrap_register_notify(union trapped_args *args, void *pr_ctxt);
extern u32 nodewrap_run(union trapped_args *args, void *pr_ctxt);
extern u32 nodewrap_terminate(union trapped_args *args, void *pr_ctxt);
extern u32 nodewrap_get_uuid_props(union trapped_args *args, void *pr_ctxt);
/* STRM wrapper functions */
extern u32 strmwrap_allocate_buffer(union trapped_args *args, void *pr_ctxt);
extern u32 strmwrap_close(union trapped_args *args, void *pr_ctxt);
extern u32 strmwrap_free_buffer(union trapped_args *args, void *pr_ctxt);
extern u32 strmwrap_get_event_handle(union trapped_args *args, void *pr_ctxt);
extern u32 strmwrap_get_info(union trapped_args *args, void *pr_ctxt);
extern u32 strmwrap_idle(union trapped_args *args, void *pr_ctxt);
extern u32 strmwrap_issue(union trapped_args *args, void *pr_ctxt);
extern u32 strmwrap_open(union trapped_args *args, void *pr_ctxt);
extern u32 strmwrap_reclaim(union trapped_args *args, void *pr_ctxt);
extern u32 strmwrap_register_notify(union trapped_args *args, void *pr_ctxt);
extern u32 strmwrap_select(union trapped_args *args, void *pr_ctxt);
extern u32 cmmwrap_calloc_buf(union trapped_args *args, void *pr_ctxt);
extern u32 cmmwrap_free_buf(union trapped_args *args, void *pr_ctxt);
extern u32 cmmwrap_get_handle(union trapped_args *args, void *pr_ctxt);
extern u32 cmmwrap_get_info(union trapped_args *args, void *pr_ctxt);
#endif /* DSPAPI_ */

72
drivers/staging/tidspbridge/include/dspbridge/dspchnl.h
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@ -1,72 +0,0 @@
/*
* dspchnl.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Declares the upper edge channel class library functions required by
* all Bridge driver / DSP API driver interface tables. These functions are
* implemented by every class of Bridge channel library.
*
* Notes:
* The function comment headers reside in dspdefs.h.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef DSPCHNL_
#define DSPCHNL_
extern int bridge_chnl_create(struct chnl_mgr **channel_mgr,
struct dev_object *hdev_obj,
const struct chnl_mgrattrs
*mgr_attrts);
extern int bridge_chnl_destroy(struct chnl_mgr *hchnl_mgr);
extern int bridge_chnl_open(struct chnl_object **chnl,
struct chnl_mgr *hchnl_mgr,
s8 chnl_mode,
u32 ch_id,
const struct chnl_attr
*pattrs);
extern int bridge_chnl_close(struct chnl_object *chnl_obj);
extern int bridge_chnl_add_io_req(struct chnl_object *chnl_obj,
void *host_buf,
u32 byte_size, u32 buf_size,
u32 dw_dsp_addr, u32 dw_arg);
extern int bridge_chnl_get_ioc(struct chnl_object *chnl_obj,
u32 timeout, struct chnl_ioc *chan_ioc);
extern int bridge_chnl_cancel_io(struct chnl_object *chnl_obj);
extern int bridge_chnl_flush_io(struct chnl_object *chnl_obj,
u32 timeout);
extern int bridge_chnl_get_info(struct chnl_object *chnl_obj,
struct chnl_info *channel_info);
extern int bridge_chnl_get_mgr_info(struct chnl_mgr *hchnl_mgr,
u32 ch_id, struct chnl_mgrinfo
*mgr_info);
extern int bridge_chnl_idle(struct chnl_object *chnl_obj,
u32 timeout, bool flush_data);
extern int bridge_chnl_register_notify(struct chnl_object *chnl_obj,
u32 event_mask,
u32 notify_type,
struct dsp_notification
*hnotification);
#endif /* DSPCHNL_ */

1048
drivers/staging/tidspbridge/include/dspbridge/dspdefs.h
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File diff suppressed because it is too large Load Diff

43
drivers/staging/tidspbridge/include/dspbridge/dspdeh.h
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@ -1,43 +0,0 @@
/*
* dspdeh.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Defines upper edge DEH functions required by all Bridge driver/DSP API
* interface tables.
*
* Notes:
* Function comment headers reside with the function typedefs in dspdefs.h.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
* Copyright (C) 2010 Felipe Contreras
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef DSPDEH_
#define DSPDEH_
struct deh_mgr;
struct dev_object;
struct dsp_notification;
int bridge_deh_create(struct deh_mgr **ret_deh,
struct dev_object *hdev_obj);
int bridge_deh_destroy(struct deh_mgr *deh);
int bridge_deh_register_notify(struct deh_mgr *deh,
u32 event_mask,
u32 notify_type,
struct dsp_notification *hnotification);
void bridge_deh_notify(struct deh_mgr *deh, int event, int info);
#endif /* DSPDEH_ */

60
drivers/staging/tidspbridge/include/dspbridge/dspdrv.h
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@ -1,60 +0,0 @@
/*
* dspdrv.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* This is the Stream Interface for the DSp API.
* All Device operations are performed via DeviceIOControl.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#if !defined _DSPDRV_H_
#define _DSPDRV_H_
/*
* ======== dsp_deinit ========
* Purpose:
* This function is called by Device Manager to de-initialize a device.
* This function is not called by applications.
* Parameters:
* device_context:Handle to the device context. The XXX_Init function
* creates and returns this identifier.
* Returns:
* TRUE indicates the device successfully de-initialized. Otherwise it
* returns FALSE.
* Requires:
* device_context!= NULL. For a built in device this should never
* get called.
* Ensures:
*/
extern bool dsp_deinit(u32 device_context);
/*
* ======== dsp_init ========
* Purpose:
* This function is called by Device Manager to initialize a device.
* This function is not called by applications
* Parameters:
* dw_context: Specifies a pointer to a string containing the registry
* path to the active key for the stream interface driver.
* HKEY_LOCAL_MACHINE\Drivers\Active
* Returns:
* Returns a handle to the device context created. This is the our actual
* Device Object representing the DSP Device instance.
* Requires:
* Ensures:
* Succeeded: device context > 0
* Failed: device Context = 0
*/
extern u32 dsp_init(u32 *init_status);
#endif

41
drivers/staging/tidspbridge/include/dspbridge/dspio.h
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@ -1,41 +0,0 @@
/*
* dspio.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Declares the upper edge IO functions required by all Bridge driver /DSP API
* interface tables.
*
* Notes:
* Function comment headers reside in dspdefs.h.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef DSPIO_
#define DSPIO_
#include <dspbridge/devdefs.h>
#include <dspbridge/io.h>
extern int bridge_io_create(struct io_mgr **io_man,
struct dev_object *hdev_obj,
const struct io_attrs *mgr_attrts);
extern int bridge_io_destroy(struct io_mgr *hio_mgr);
extern int bridge_io_on_loaded(struct io_mgr *hio_mgr);
extern int bridge_io_get_proc_load(struct io_mgr *hio_mgr,
struct dsp_procloadstat *proc_lstat);
#endif /* DSPIO_ */

68
drivers/staging/tidspbridge/include/dspbridge/dspioctl.h
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@ -1,68 +0,0 @@
/*
* dspioctl.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Bridge driver BRD_IOCtl reserved command definitions.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef DSPIOCTL_
#define DSPIOCTL_
/* ------------------------------------ Hardware Abstraction Layer */
#include <hw_defs.h>
#include <hw_mmu.h>
/*
* Any IOCTLS at or above this value are reserved for standard Bridge driver
* interfaces.
*/
#define BRDIOCTL_RESERVEDBASE 0x8000
#define BRDIOCTL_CHNLREAD (BRDIOCTL_RESERVEDBASE + 0x10)
#define BRDIOCTL_CHNLWRITE (BRDIOCTL_RESERVEDBASE + 0x20)
/* DMMU */
#define BRDIOCTL_SETMMUCONFIG (BRDIOCTL_RESERVEDBASE + 0x60)
/* PWR */
#define BRDIOCTL_PWRCONTROL (BRDIOCTL_RESERVEDBASE + 0x70)
/* attention, modifiers:
* Some of these control enumerations are made visible to user for power
* control, so any changes to this list, should also be updated in the user
* header file 'dbdefs.h' ***/
/* These ioctls are reserved for PWR power commands for the DSP */
#define BRDIOCTL_DEEPSLEEP (BRDIOCTL_PWRCONTROL + 0x0)
#define BRDIOCTL_EMERGENCYSLEEP (BRDIOCTL_PWRCONTROL + 0x1)
#define BRDIOCTL_WAKEUP (BRDIOCTL_PWRCONTROL + 0x2)
#define BRDIOCTL_CLK_CTRL (BRDIOCTL_PWRCONTROL + 0x7)
/* DSP Initiated Hibernate */
#define BRDIOCTL_PWR_HIBERNATE (BRDIOCTL_PWRCONTROL + 0x8)
#define BRDIOCTL_PRESCALE_NOTIFY (BRDIOCTL_PWRCONTROL + 0x9)
#define BRDIOCTL_POSTSCALE_NOTIFY (BRDIOCTL_PWRCONTROL + 0xA)
#define BRDIOCTL_CONSTRAINT_REQUEST (BRDIOCTL_PWRCONTROL + 0xB)
/* Number of actual DSP-MMU TLB entries */
#define BRDIOCTL_NUMOFMMUTLB 32
struct bridge_ioctl_extproc {
u32 dsp_va; /* DSP virtual address */
u32 gpp_pa; /* GPP physical address */
/* GPP virtual address. __va does not work for ioremapped addresses */
u32 gpp_va;
u32 size; /* Size of the mapped memory in bytes */
enum hw_endianism_t endianism;
enum hw_mmu_mixed_size_t mixed_mode;
enum hw_element_size_t elem_size;
};
#endif /* DSPIOCTL_ */

56
drivers/staging/tidspbridge/include/dspbridge/dspmsg.h
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@ -1,56 +0,0 @@
/*
* dspmsg.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Declares the upper edge message class library functions required by
* all Bridge driver / DSP API interface tables. These functions are
* implemented by every class of Bridge driver channel library.
*
* Notes:
* Function comment headers reside in dspdefs.h.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef DSPMSG_
#define DSPMSG_
#include <dspbridge/msgdefs.h>
extern int bridge_msg_create(struct msg_mgr **msg_man,
struct dev_object *hdev_obj,
msg_onexit msg_callback);
extern int bridge_msg_create_queue(struct msg_mgr *hmsg_mgr,
struct msg_queue **msgq,
u32 msgq_id, u32 max_msgs, void *arg);
extern void bridge_msg_delete(struct msg_mgr *hmsg_mgr);
extern void bridge_msg_delete_queue(struct msg_queue *msg_queue_obj);
extern int bridge_msg_get(struct msg_queue *msg_queue_obj,
struct dsp_msg *pmsg, u32 utimeout);
extern int bridge_msg_put(struct msg_queue *msg_queue_obj,
const struct dsp_msg *pmsg, u32 utimeout);
extern int bridge_msg_register_notify(struct msg_queue *msg_queue_obj,
u32 event_mask,
u32 notify_type,
struct dsp_notification
*hnotification);
extern void bridge_msg_set_queue_id(struct msg_queue *msg_queue_obj,
u32 msgq_id);
#endif /* DSPMSG_ */

490
drivers/staging/tidspbridge/include/dspbridge/dynamic_loader.h
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@ -1,490 +0,0 @@
/*
* dynamic_loader.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Copyright (C) 2008 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef _DYNAMIC_LOADER_H_
#define _DYNAMIC_LOADER_H_
#include <linux/kernel.h>
#include <linux/types.h>
/*
* Dynamic Loader
*
* The function of the dynamic loader is to load a "module" containing
* instructions for a "target" processor into that processor. In the process
* it assigns memory for the module, resolves symbol references made by the
* module, and remembers symbols defined by the module.
*
* The dynamic loader is parameterized for a particular system by 4 classes
* that supply the module and system specific functions it requires
*/
/* The read functions for the module image to be loaded */
struct dynamic_loader_stream;
/* This class defines "host" symbol and support functions */
struct dynamic_loader_sym;
/* This class defines the allocator for "target" memory */
struct dynamic_loader_allocate;
/* This class defines the copy-into-target-memory functions */
struct dynamic_loader_initialize;
/*
* Option flags to modify the behavior of module loading
*/
#define DLOAD_INITBSS 0x1 /* initialize BSS sections to zero */
/*****************************************************************************
* Procedure dynamic_load_module
*
* Parameters:
* module The input stream that supplies the module image
* syms Host-side symbol table and malloc/free functions
* alloc Target-side memory allocation
* init Target-side memory initialization, or NULL for symbol read only
* options Option flags DLOAD_*
* mhandle A module handle for use with Dynamic_Unload
*
* Effect:
* The module image is read using *module. Target storage for the new image is
* obtained from *alloc. Symbols defined and referenced by the module are
* managed using *syms. The image is then relocated and references resolved
* as necessary, and the resulting executable bits are placed into target memory
* using *init.
*
* Returns:
* On a successful load, a module handle is placed in *mhandle, and zero is
* returned. On error, the number of errors detected is returned. Individual
* errors are reported during the load process using syms->error_report().
**************************************************************************** */
extern int dynamic_load_module(
/* the source for the module image */
struct dynamic_loader_stream *module,
/* host support for symbols and storage */
struct dynamic_loader_sym *syms,
/* the target memory allocator */
struct dynamic_loader_allocate *alloc,
/* the target memory initializer */
struct dynamic_loader_initialize *init,
unsigned options, /* option flags */
/* the returned module handle */
void **mhandle);
/*****************************************************************************
* Procedure dynamic_open_module
*
* Parameters:
* module The input stream that supplies the module image
* syms Host-side symbol table and malloc/free functions
* alloc Target-side memory allocation
* init Target-side memory initialization, or NULL for symbol read only
* options Option flags DLOAD_*
* mhandle A module handle for use with Dynamic_Unload
*
* Effect:
* The module image is read using *module. Target storage for the new image is
* obtained from *alloc. Symbols defined and referenced by the module are
* managed using *syms. The image is then relocated and references resolved
* as necessary, and the resulting executable bits are placed into target memory
* using *init.
*
* Returns:
* On a successful load, a module handle is placed in *mhandle, and zero is
* returned. On error, the number of errors detected is returned. Individual
* errors are reported during the load process using syms->error_report().
**************************************************************************** */
extern int dynamic_open_module(
/* the source for the module image */
struct dynamic_loader_stream *module,
/* host support for symbols and storage */
struct dynamic_loader_sym *syms,
/* the target memory allocator */
struct dynamic_loader_allocate *alloc,
/* the target memory initializer */
struct dynamic_loader_initialize *init,
unsigned options, /* option flags */
/* the returned module handle */
void **mhandle);
/*****************************************************************************
* Procedure dynamic_unload_module
*
* Parameters:
* mhandle A module handle from dynamic_load_module
* syms Host-side symbol table and malloc/free functions
* alloc Target-side memory allocation
*
* Effect:
* The module specified by mhandle is unloaded. Unloading causes all
* target memory to be deallocated, all symbols defined by the module to
* be purged, and any host-side storage used by the dynamic loader for
* this module to be released.
*
* Returns:
* Zero for success. On error, the number of errors detected is returned.
* Individual errors are reported using syms->error_report().
**************************************************************************** */
extern int dynamic_unload_module(void *mhandle, /* the module
* handle */
/* host support for symbols and
* storage */
struct dynamic_loader_sym *syms,
/* the target memory allocator */
struct dynamic_loader_allocate *alloc,
/* the target memory initializer */
struct dynamic_loader_initialize *init);
/*****************************************************************************
*****************************************************************************
* A class used by the dynamic loader for input of the module image
*****************************************************************************
**************************************************************************** */
struct dynamic_loader_stream {
/* public: */
/*************************************************************************
* read_buffer
*
* PARAMETERS :
* buffer Pointer to the buffer to fill
* bufsiz Amount of data desired in sizeof() units
*
* EFFECT :
* Reads the specified amount of data from the module input stream
* into the specified buffer. Returns the amount of data read in sizeof()
* units (which if less than the specification, represents an error).
*
* NOTES:
* In release 1 increments the file position by the number of bytes read
*
************************************************************************ */
int (*read_buffer) (struct dynamic_loader_stream *thisptr,
void *buffer, unsigned bufsiz);
/*************************************************************************
* set_file_posn (release 1 only)
*
* PARAMETERS :
* posn Desired file position relative to start of file in sizeof() units.
*
* EFFECT :
* Adjusts the internal state of the stream object so that the next
* read_buffer call will begin to read at the specified offset from
* the beginning of the input module. Returns 0 for success, non-zero
* for failure.
*
************************************************************************ */
int (*set_file_posn) (struct dynamic_loader_stream *thisptr,
/* to be eliminated in release 2 */
unsigned int posn);
};
/*****************************************************************************
*****************************************************************************
* A class used by the dynamic loader for symbol table support and
* miscellaneous host-side functions
*****************************************************************************
**************************************************************************** */
typedef u32 ldr_addr;
/*
* the structure of a symbol known to the dynamic loader
*/
struct dynload_symbol {
ldr_addr value;
};
struct dynamic_loader_sym {
/* public: */
/*************************************************************************
* find_matching_symbol
*
* PARAMETERS :
* name The name of the desired symbol
*
* EFFECT :
* Locates a symbol matching the name specified. A pointer to the
* symbol is returned if it exists; 0 is returned if no such symbol is
* found.
*
************************************************************************ */
struct dynload_symbol *(*find_matching_symbol)
(struct dynamic_loader_sym *thisptr, const char *name);
/*************************************************************************
* add_to_symbol_table
*
* PARAMETERS :
* nname Pointer to the name of the new symbol
* moduleid An opaque module id assigned by the dynamic loader
*
* EFFECT :
* The new symbol is added to the table. A pointer to the symbol is
* returned, or NULL is returned for failure.
*
* NOTES:
* It is permissible for this function to return NULL; the effect is that
* the named symbol will not be available to resolve references in
* subsequent loads. Returning NULL will not cause the current load
* to fail.
************************************************************************ */
struct dynload_symbol *(*add_to_symbol_table)
(struct dynamic_loader_sym *
thisptr, const char *nname, unsigned moduleid);
/*************************************************************************
* purge_symbol_table
*
* PARAMETERS :
* moduleid An opaque module id assigned by the dynamic loader
*
* EFFECT :
* Each symbol in the symbol table whose moduleid matches the argument
* is removed from the table.
************************************************************************ */
void (*purge_symbol_table) (struct dynamic_loader_sym *thisptr,
unsigned moduleid);
/*************************************************************************
* dload_allocate
*
* PARAMETERS :
* memsiz size of desired memory in sizeof() units
*
* EFFECT :
* Returns a pointer to some "host" memory for use by the dynamic
* loader, or NULL for failure.
* This function is serves as a replaceable form of "malloc" to
* allow the user to configure the memory usage of the dynamic loader.
************************************************************************ */
void *(*dload_allocate) (struct dynamic_loader_sym *thisptr,
unsigned memsiz);
/*************************************************************************
* dload_deallocate
*
* PARAMETERS :
* memptr pointer to previously allocated memory
*
* EFFECT :
* Releases the previously allocated "host" memory.
************************************************************************ */
void (*dload_deallocate) (struct dynamic_loader_sym *thisptr,
void *memptr);
/*************************************************************************
* error_report
*
* PARAMETERS :
* errstr pointer to an error string
* args additional arguments
*
* EFFECT :
* This function provides an error reporting interface for the dynamic
* loader. The error string and arguments are designed as for the
* library function vprintf.
************************************************************************ */
void (*error_report) (struct dynamic_loader_sym *thisptr,
const char *errstr, va_list args);
}; /* class dynamic_loader_sym */
/*****************************************************************************
*****************************************************************************
* A class used by the dynamic loader to allocate and deallocate target memory.
*****************************************************************************
**************************************************************************** */
struct ldr_section_info {
/* Name of the memory section assigned at build time */
const char *name;
ldr_addr run_addr; /* execution address of the section */
ldr_addr load_addr; /* load address of the section */
ldr_addr size; /* size of the section in addressable units */
#ifndef _BIG_ENDIAN
u16 page; /* memory page or view */
u16 type; /* one of the section types below */
#else
u16 type; /* one of the section types below */
u16 page; /* memory page or view */
#endif
/* a context field for use by dynamic_loader_allocate;
* ignored but maintained by the dynamic loader */
u32 context;
};
/* use this macro to extract type of section from ldr_section_info.type field */
#define DLOAD_SECTION_TYPE(typeinfo) (typeinfo & 0xF)
/* type of section to be allocated */
#define DLOAD_TEXT 0
#define DLOAD_DATA 1
#define DLOAD_BSS 2
/* internal use only, run-time cinit will be of type DLOAD_DATA */
#define DLOAD_CINIT 3
struct dynamic_loader_allocate {
/* public: */
/*************************************************************************
* Function allocate
*
* Parameters:
* info A pointer to an information block for the section
* align The alignment of the storage in target AUs
*
* Effect:
* Allocates target memory for the specified section and fills in the
* load_addr and run_addr fields of the section info structure. Returns TRUE
* for success, FALSE for failure.
*
* Notes:
* Frequently load_addr and run_addr are the same, but if they are not
* load_addr is used with dynamic_loader_initialize, and run_addr is
* used for almost all relocations. This function should always initialize
* both fields.
************************************************************************ */
int (*dload_allocate) (struct dynamic_loader_allocate *thisptr,
struct ldr_section_info *info, unsigned align);
/*************************************************************************
* Function deallocate
*
* Parameters:
* info A pointer to an information block for the section
*
* Effect:
* Releases the target memory previously allocated.
*
* Notes:
* The content of the info->name field is undefined on call to this function.
************************************************************************ */
void (*dload_deallocate) (struct dynamic_loader_allocate *thisptr,
struct ldr_section_info *info);
}; /* class dynamic_loader_allocate */
/*****************************************************************************
*****************************************************************************
* A class used by the dynamic loader to load data into a target. This class
* provides the interface-specific functions needed to load data.
*****************************************************************************
**************************************************************************** */
struct dynamic_loader_initialize {
/* public: */
/*************************************************************************
* Function connect
*
* Parameters:
* none
*
* Effect:
* Connect to the initialization interface. Returns TRUE for success,
* FALSE for failure.
*
* Notes:
* This function is called prior to use of any other functions in
* this interface.
************************************************************************ */
int (*connect) (struct dynamic_loader_initialize *thisptr);
/*************************************************************************
* Function readmem
*
* Parameters:
* bufr Pointer to a word-aligned buffer for the result
* locn Target address of first data element
* info Section info for the section in which the address resides
* bytsiz Size of the data to be read in sizeof() units
*
* Effect:
* Fills the specified buffer with data from the target. Returns TRUE for
* success, FALSE for failure.
************************************************************************ */
int (*readmem) (struct dynamic_loader_initialize *thisptr,
void *bufr,
ldr_addr locn,
struct ldr_section_info *info, unsigned bytsiz);
/*************************************************************************
* Function writemem
*
* Parameters:
* bufr Pointer to a word-aligned buffer of data
* locn Target address of first data element to be written
* info Section info for the section in which the address resides
* bytsiz Size of the data to be written in sizeof() units
*
* Effect:
* Writes the specified buffer to the target. Returns TRUE for success,
* FALSE for failure.
************************************************************************ */
int (*writemem) (struct dynamic_loader_initialize *thisptr,
void *bufr,
ldr_addr locn,
struct ldr_section_info *info, unsigned bytsiz);
/*************************************************************************
* Function fillmem
*
* Parameters:
* locn Target address of first data element to be written
* info Section info for the section in which the address resides
* bytsiz Size of the data to be written in sizeof() units
* val Value to be written in each byte
* Effect:
* Fills the specified area of target memory. Returns TRUE for success,
* FALSE for failure.
************************************************************************ */
int (*fillmem) (struct dynamic_loader_initialize *thisptr,
ldr_addr locn, struct ldr_section_info *info,
unsigned bytsiz, unsigned val);
/*************************************************************************
* Function execute
*
* Parameters:
* start Starting address
*
* Effect:
* The target code at the specified starting address is executed.
*
* Notes:
* This function is called at the end of the dynamic load process
* if the input module has specified a starting address.
************************************************************************ */
int (*execute) (struct dynamic_loader_initialize *thisptr,
ldr_addr start);
/*************************************************************************
* Function release
*
* Parameters:
* none
*
* Effect:
* Releases the connection to the load interface.
*
* Notes:
* This function is called at the end of the dynamic load process.
************************************************************************ */
void (*release) (struct dynamic_loader_initialize *thisptr);
}; /* class dynamic_loader_initialize */
#endif /* _DYNAMIC_LOADER_H_ */

108
drivers/staging/tidspbridge/include/dspbridge/getsection.h
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@ -1,108 +0,0 @@
/*
* getsection.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* This file provides an API add-on to the dynamic loader that allows the user
* to query section information and extract section data from dynamic load
* modules.
*
* Notes:
* Functions in this API assume that the supplied dynamic_loader_stream
* object supports the set_file_posn method.
*
* Copyright (C) 2008 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef _GETSECTION_H_
#define _GETSECTION_H_
#include "dynamic_loader.h"
/*
* Procedure dload_module_open
*
* Parameters:
* module The input stream that supplies the module image
* syms Host-side malloc/free and error reporting functions.
* Other methods are unused.
*
* Effect:
* Reads header information from a dynamic loader module using the specified
* stream object, and returns a handle for the module information. This
* handle may be used in subsequent query calls to obtain information
* contained in the module.
*
* Returns:
* NULL if an error is encountered, otherwise a module handle for use
* in subsequent operations.
*/
extern void *dload_module_open(struct dynamic_loader_stream
*module, struct dynamic_loader_sym
*syms);
/*
* Procedure dload_get_section_info
*
* Parameters:
* minfo Handle from dload_module_open for this module
* section_name Pointer to the string name of the section desired
* section_info Address of a section info structure pointer to be initialized
*
* Effect:
* Finds the specified section in the module information, and fills in
* the provided ldr_section_info structure.
*
* Returns:
* TRUE for success, FALSE for section not found
*/
extern int dload_get_section_info(void *minfo,
const char *section_name,
const struct ldr_section_info
**const section_info);
/*
* Procedure dload_get_section
*
* Parameters:
* minfo Handle from dload_module_open for this module
* section_info Pointer to a section info structure for the desired section
* section_data Buffer to contain the section initialized data
*
* Effect:
* Copies the initialized data for the specified section into the
* supplied buffer.
*
* Returns:
* TRUE for success, FALSE for section not found
*/
extern int dload_get_section(void *minfo,
const struct ldr_section_info *section_info,
void *section_data);
/*
* Procedure dload_module_close
*
* Parameters:
* minfo Handle from dload_module_open for this module
*
* Effect:
* Releases any storage associated with the module handle. On return,
* the module handle is invalid.
*
* Returns:
* Zero for success. On error, the number of errors detected is returned.
* Individual errors are reported using syms->error_report(), where syms was
* an argument to dload_module_open
*/
extern void dload_module_close(void *minfo);
#endif /* _GETSECTION_H_ */

32
drivers/staging/tidspbridge/include/dspbridge/gh.h
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@ -1,32 +0,0 @@
/*
* gh.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef GH_
#define GH_
#include <dspbridge/host_os.h>
extern struct gh_t_hash_tab *gh_create(u32 val_size,
u32 (*hash)(const void *), bool (*match)(const void *,
const void *), void (*delete) (void *));
extern void gh_delete(struct gh_t_hash_tab *hash_tab);
extern void *gh_find(struct gh_t_hash_tab *hash_tab, const void *key);
extern void *gh_insert(struct gh_t_hash_tab *hash_tab, const void *key,
const void *value);
#ifdef CONFIG_TIDSPBRIDGE_BACKTRACE
void gh_iterate(struct gh_t_hash_tab *hash_tab,
void (*callback)(void *, void *), void *user_data);
#endif
#endif /* GH_ */

57
drivers/staging/tidspbridge/include/dspbridge/host_os.h
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@ -1,57 +0,0 @@
/*
* host_os.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Copyright (C) 2008 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef _HOST_OS_H_
#define _HOST_OS_H_
#include <linux/atomic.h>
#include <linux/semaphore.h>
#include <linux/uaccess.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/syscalls.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/stddef.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/sched.h>
#include <linux/fs.h>
#include <linux/file.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/ctype.h>
#include <linux/mm.h>
#include <linux/device.h>
#include <linux/vmalloc.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/omap-mailbox.h>
#include <linux/pagemap.h>
#include <asm/cacheflush.h>
#include <linux/dma-mapping.h>
/* TODO -- Remove, once omap-iommu is used */
#define INT_DSP_MMU_IRQ (28 + NR_IRQS)
#define PRCM_VDD1 1
extern struct platform_device *omap_dspbridge_dev;
extern struct device *bridge;
#endif

80
drivers/staging/tidspbridge/include/dspbridge/io.h
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@ -1,80 +0,0 @@
/*
* io.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* The io module manages IO between CHNL and msg_ctrl.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef IO_
#define IO_
#include <dspbridge/cfgdefs.h>
#include <dspbridge/devdefs.h>
/* IO Objects: */
struct io_mgr;
/* IO manager attributes: */
struct io_attrs {
u8 birq; /* Channel's I/O IRQ number. */
bool irq_shared; /* TRUE if the IRQ is shareable. */
u32 word_size; /* DSP Word size. */
u32 shm_base; /* Physical base address of shared memory. */
u32 sm_length; /* Size (in bytes) of shared memory. */
};
/*
* ======== io_create ========
* Purpose:
* Create an IO manager object, responsible for managing IO between
* CHNL and msg_ctrl.
* Parameters:
* channel_mgr: Location to store a channel manager object on
* output.
* hdev_obj: Handle to a device object.
* mgr_attrts: IO manager attributes.
* mgr_attrts->birq: I/O IRQ number.
* mgr_attrts->irq_shared: TRUE if the IRQ is shareable.
* mgr_attrts->word_size: DSP Word size in equivalent PC bytes..
* Returns:
* 0: Success;
* -ENOMEM: Insufficient memory for requested resources.
* -EIO: Unable to plug channel ISR for configured IRQ.
* -EINVAL: Invalid DSP word size (must be > 0).
* Invalid base address for DSP communications.
* Requires:
* io_man != NULL.
* mgr_attrts != NULL.
* Ensures:
*/
extern int io_create(struct io_mgr **io_man,
struct dev_object *hdev_obj,
const struct io_attrs *mgr_attrts);
/*
* ======== io_destroy ========
* Purpose:
* Destroy the IO manager.
* Parameters:
* hio_mgr: IOmanager object.
* Returns:
* 0: Success.
* -EFAULT: hio_mgr was invalid.
* Requires:
* Ensures:
*/
extern int io_destroy(struct io_mgr *hio_mgr);
#endif /* CHNL_ */

160
drivers/staging/tidspbridge/include/dspbridge/io_sm.h
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@ -1,160 +0,0 @@
/*
* io_sm.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* IO dispatcher for a shared memory channel driver.
* Also, includes macros to simulate shm via port io calls.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef IOSM_
#define IOSM_
#include <dspbridge/_chnl_sm.h>
#include <dspbridge/host_os.h>
#include <dspbridge/io.h>
#include <dspbridge/mbx_sh.h> /* shared mailbox codes */
/* Magic code used to determine if DSP signaled exception. */
#define DEH_BASE MBX_DEH_BASE
#define DEH_LIMIT MBX_DEH_LIMIT
#define IO_INPUT 0
#define IO_OUTPUT 1
#define IO_SERVICE 2
#ifdef CONFIG_TIDSPBRIDGE_DVFS
/* The maximum number of OPPs that are supported */
extern s32 dsp_max_opps;
/* The Vdd1 opp table information */
extern u32 vdd1_dsp_freq[6][4];
#endif
/*
* ======== io_cancel_chnl ========
* Purpose:
* Cancel IO on a given channel.
* Parameters:
* hio_mgr: IO Manager.
* chnl: Index of channel to cancel IO on.
* Returns:
* Requires:
* Valid hio_mgr.
* Ensures:
*/
extern void io_cancel_chnl(struct io_mgr *hio_mgr, u32 chnl);
/*
* ======== io_dpc ========
* Purpose:
* Deferred procedure call for shared memory channel driver ISR. Carries
* out the dispatch of I/O.
* Parameters:
* ref_data: Pointer to reference data registered via a call to
* DPC_Create().
* Returns:
* Requires:
* Must not block.
* Must not acquire resources.
* All data touched must be locked in memory if running in kernel mode.
* Ensures:
* Non-preemptible (but interruptible).
*/
extern void io_dpc(unsigned long ref_data);
/*
* ======== io_mbox_msg ========
* Purpose:
* Main message handler for the shared memory Bridge channel manager.
* Determine if this message is ours, then schedules a DPC to
* dispatch I/O.
* Parameters:
* self: Pointer to its own notifier_block struct.
* len: Length of message.
* msg: Message code received.
* Returns:
* NOTIFY_OK if handled; NOTIFY_BAD otherwise.
*/
int io_mbox_msg(struct notifier_block *self, unsigned long len, void *msg);
/*
* ======== io_request_chnl ========
* Purpose:
* Request I/O from the DSP. Sets flags in shared memory, then interrupts
* the DSP.
* Parameters:
* hio_mgr: IO manager handle.
* pchnl: Ptr to the channel requesting I/O.
* io_mode: Mode of channel: {IO_INPUT | IO_OUTPUT}.
* Returns:
* Requires:
* pchnl != NULL
* Ensures:
*/
extern void io_request_chnl(struct io_mgr *io_manager,
struct chnl_object *pchnl,
u8 io_mode, u16 *mbx_val);
/*
* ======== iosm_schedule ========
* Purpose:
* Schedule DPC for IO.
* Parameters:
* pio_mgr: Ptr to a I/O manager.
* Returns:
* Requires:
* pchnl != NULL
* Ensures:
*/
extern void iosm_schedule(struct io_mgr *io_manager);
/*
* ======== io_sh_msetting ========
* Purpose:
* Sets the shared memory setting
* Parameters:
* hio_mgr: Handle to a I/O manager.
* desc: Shared memory type
* pargs: Ptr to shm setting
* Returns:
* Requires:
* hio_mgr != NULL
* pargs != NULL
* Ensures:
*/
extern int io_sh_msetting(struct io_mgr *hio_mgr, u8 desc, void *pargs);
/*
* Misc functions for the CHNL_IO shared memory library:
*/
/* Maximum channel bufsize that can be used. */
extern u32 io_buf_size(struct io_mgr *hio_mgr);
#ifdef CONFIG_TIDSPBRIDGE_BACKTRACE
/*
* ========print_dsp_trace_buffer ========
* Print DSP tracebuffer.
*/
extern int print_dsp_trace_buffer(struct bridge_dev_context
*hbridge_context);
int dump_dsp_stack(struct bridge_dev_context *bridge_context);
void dump_dl_modules(struct bridge_dev_context *bridge_context);
void print_dsp_debug_trace(struct io_mgr *hio_mgr);
#endif
#endif /* IOSM_ */

144
drivers/staging/tidspbridge/include/dspbridge/mbx_sh.h
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@ -1,144 +0,0 @@
/*
* mbx_sh.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Definitions for shared mailbox cmd/data values.(used on both
* the GPP and DSP sides).
*
* Copyright (C) 2008 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
/*
* Bridge usage of OMAP mailbox 1 is determined by the "class" of the
* mailbox interrupt's cmd value received. The class value are defined
* as a bit (10 thru 15) being set.
*
* Note: Only 16 bits of each is used. Other 16 bit data reg available.
*
* 16 bit Mbx bit defns:
*
* A). Exception/Error handling (Module DEH) : class = 0.
*
* 15 10 0
* ---------------------------------
* |0|0|0|0|0|0|x|x|x|x|x|x|x|x|x|x|
* ---------------------------------
* | (class) | (module specific) |
*
*
* B: DSP-DMA link driver channels (DDMA) : class = 1.
*
* 15 10 0
* ---------------------------------
* |0|0|0|0|0|1|b|b|b|b|b|c|c|c|c|c|
* ---------------------------------
* | (class) | (module specific) |
*
* where b -> buffer index (32 DDMA buffers/chnl max)
* c -> channel Id (32 DDMA chnls max)
*
*
* C: Proc-copy link driver channels (PCPY) : class = 2.
*
* 15 10 0
* ---------------------------------
* |0|0|0|0|1|0|x|x|x|x|x|x|x|x|x|x|
* ---------------------------------
* | (class) | (module specific) |
*
*
* D: Zero-copy link driver channels (DDZC) : class = 4.
*
* 15 10 0
* ---------------------------------
* |0|0|0|1|0|0|x|x|x|x|x|c|c|c|c|c|
* ---------------------------------
* | (class) | (module specific) |
*
* where x -> not used
* c -> channel Id (32 ZCPY chnls max)
*
*
* E: Power management : class = 8.
*
* 15 10 0
* ---------------------------------
* |0|0|1|0|0|0|x|x|x|x|x|c|c|c|c|c|
* 0010 00xx xxxc cccc
* 0010 00nn pppp qqqq
* nn:
* 00 = reserved
* 01 = pwr state change
* 10 = opp pre-change
* 11 = opp post-change
*
* if nn = pwr state change:
* pppp = don't care
* qqqq:
* 0010 = hibernate
* 0010 0001 0000 0010
* 0110 = retention
* 0010 0001 0000 0110
* others reserved
*
* if nn = opp pre-change:
* pppp = current opp
* qqqq = next opp
*
* if nn = opp post-change:
* pppp = prev opp
* qqqq = current opp
*
* ---------------------------------
* | (class) | (module specific) |
*
* where x -> not used
* c -> Power management command
*
*/
#ifndef _MBX_SH_H
#define _MBX_SH_H
#define MBX_PCPY_CLASS 0x0800 /* PROC-COPY " */
#define MBX_PM_CLASS 0x2000 /* Power Management */
#define MBX_DBG_CLASS 0x4000 /* For debugging purpose */
/*
* Exception Handler codes
* Magic code used to determine if DSP signaled exception.
*/
#define MBX_DEH_BASE 0x0
#define MBX_DEH_USERS_BASE 0x100 /* 256 */
#define MBX_DEH_LIMIT 0x3FF /* 1023 */
#define MBX_DEH_RESET 0x101 /* DSP RESET (DEH) */
/*
* Link driver command/status codes.
*/
/* Power Management Commands */
#define MBX_PM_DSPIDLE (MBX_PM_CLASS + 0x0)
#define MBX_PM_DSPWAKEUP (MBX_PM_CLASS + 0x1)
#define MBX_PM_EMERGENCYSLEEP (MBX_PM_CLASS + 0x2)
#define MBX_PM_SETPOINT_PRENOTIFY (MBX_PM_CLASS + 0x6)
#define MBX_PM_SETPOINT_POSTNOTIFY (MBX_PM_CLASS + 0x7)
#define MBX_PM_DSPRETENTION (MBX_PM_CLASS + 0x8)
#define MBX_PM_DSPHIBERNATE (MBX_PM_CLASS + 0x9)
#define MBX_PM_HIBERNATE_EN (MBX_PM_CLASS + 0xA)
#define MBX_PM_OPP_REQ (MBX_PM_CLASS + 0xB)
/* Bridge Debug Commands */
#define MBX_DBG_SYSPRINTF (MBX_DBG_CLASS + 0x0)
#endif /* _MBX_SH_H */

30
drivers/staging/tidspbridge/include/dspbridge/memdefs.h
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@ -1,30 +0,0 @@
/*
* memdefs.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Global MEM constants and types, shared between Bridge driver and DSP API.
*
* Copyright (C) 2008 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef MEMDEFS_
#define MEMDEFS_
/*
* MEM_VIRTUALSEGID is used by Node & Strm to access virtual address space in
* the correct client process context.
*/
#define MEM_SETVIRTUALSEGID 0x10000000
#define MEM_GETVIRTUALSEGID 0x20000000
#define MEM_MASKVIRTUALSEGID (MEM_SETVIRTUALSEGID | MEM_GETVIRTUALSEGID)
#endif /* MEMDEFS_ */

205
drivers/staging/tidspbridge/include/dspbridge/mgr.h
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@ -1,205 +0,0 @@
/*
* mgr.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* This is the DSP API RM module interface.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef MGR_
#define MGR_
#include <dspbridge/mgrpriv.h>
#define MAX_EVENTS 32
/*
* ======== mgr_wait_for_bridge_events ========
* Purpose:
* Block on any Bridge event(s)
* Parameters:
* anotifications : array of pointers to notification objects.
* count : number of elements in above array
* pu_index : index of signaled event object
* utimeout : timeout interval in milliseocnds
* Returns:
* 0 : Success.
* -ETIME : Wait timed out. *pu_index is undetermined.
* Details:
*/
int mgr_wait_for_bridge_events(struct dsp_notification
**anotifications,
u32 count, u32 *pu_index,
u32 utimeout);
/*
* ======== mgr_create ========
* Purpose:
* Creates the Manager Object. This is done during the driver loading.
* There is only one Manager Object in the DSP/BIOS Bridge.
* Parameters:
* mgr_obj: Location to store created MGR Object handle.
* dev_node_obj: Device object as known to the system.
* Returns:
* 0: Success
* -ENOMEM: Failed to Create the Object
* -EPERM: General Failure
* Requires:
* MGR Initialized (refs > 0 )
* mgr_obj != NULL.
* Ensures:
* 0: *mgr_obj is a valid MGR interface to the device.
* MGR Object stores the DCD Manager Handle.
* MGR Object stored in the Regsitry.
* !0: MGR Object not created
* Details:
* DCD Dll is loaded and MGR Object stores the handle of the DLL.
*/
extern int mgr_create(struct mgr_object **mgr_obj,
struct cfg_devnode *dev_node_obj);
/*
* ======== mgr_destroy ========
* Purpose:
* Destroys the MGR object. Called upon driver unloading.
* Parameters:
* hmgr_obj: Handle to Manager object .
* Returns:
* 0: Success.
* DCD Manager freed; MGR Object destroyed;
* MGR Object deleted from the Registry.
* -EPERM: Failed to destroy MGR Object
* Requires:
* MGR Initialized (refs > 0 )
* hmgr_obj is a valid MGR handle .
* Ensures:
* 0: MGR Object destroyed and hmgr_obj is Invalid MGR
* Handle.
*/
extern int mgr_destroy(struct mgr_object *hmgr_obj);
/*
* ======== mgr_enum_node_info ========
* Purpose:
* Enumerate and get configuration information about nodes configured
* in the node database.
* Parameters:
* node_id: The node index (base 0).
* pndb_props: Ptr to the dsp_ndbprops structure for output.
* undb_props_size: Size of the dsp_ndbprops structure.
* pu_num_nodes: Location where the number of nodes configured
* in the database will be returned.
* Returns:
* 0: Success.
* -EINVAL: Parameter node_id is > than the number of nodes.
* configutred in the system
* -EIDRM: During Enumeration there has been a change in
* the number of nodes configured or in the
* the properties of the enumerated nodes.
* -EPERM: Failed to querry the Node Data Base
* Requires:
* pNDBPROPS is not null
* undb_props_size >= sizeof(dsp_ndbprops)
* pu_num_nodes is not null
* MGR Initialized (refs > 0 )
* Ensures:
* SUCCESS on successful retreival of data and *pu_num_nodes > 0 OR
* DSP_FAILED && *pu_num_nodes == 0.
* Details:
*/
extern int mgr_enum_node_info(u32 node_id,
struct dsp_ndbprops *pndb_props,
u32 undb_props_size,
u32 *pu_num_nodes);
/*
* ======== mgr_enum_processor_info ========
* Purpose:
* Enumerate and get configuration information about available DSP
* processors
* Parameters:
* processor_id: The processor index (zero-based).
* processor_info: Ptr to the dsp_processorinfo structure .
* processor_info_size: Size of dsp_processorinfo structure.
* pu_num_procs: Location where the number of DSPs configured
* in the database will be returned
* Returns:
* 0: Success.
* -EINVAL: Parameter processor_id is > than the number of
* DSP Processors in the system.
* -EPERM: Failed to querry the Node Data Base
* Requires:
* processor_info is not null
* pu_num_procs is not null
* processor_info_size >= sizeof(dsp_processorinfo)
* MGR Initialized (refs > 0 )
* Ensures:
* SUCCESS on successful retreival of data and *pu_num_procs > 0 OR
* DSP_FAILED && *pu_num_procs == 0.
* Details:
*/
extern int mgr_enum_processor_info(u32 processor_id,
struct dsp_processorinfo
*processor_info,
u32 processor_info_size,
u8 *pu_num_procs);
/*
* ======== mgr_exit ========
* Purpose:
* Decrement reference count, and free resources when reference count is
* 0.
* Parameters:
* Returns:
* Requires:
* MGR is initialized.
* Ensures:
* When reference count == 0, MGR's private resources are freed.
*/
extern void mgr_exit(void);
/*
* ======== mgr_get_dcd_handle ========
* Purpose:
* Retrieves the MGR handle. Accessor Function
* Parameters:
* mgr_handle: Handle to the Manager Object
* dcd_handle: Ptr to receive the DCD Handle.
* Returns:
* 0: Success
* -EPERM: Failure to get the Handle
* Requires:
* MGR is initialized.
* dcd_handle != NULL
* Ensures:
* 0 and *dcd_handle != NULL ||
* -EPERM and *dcd_handle == NULL
*/
extern int mgr_get_dcd_handle(struct mgr_object
*mgr_handle, u32 *dcd_handle);
/*
* ======== mgr_init ========
* Purpose:
* Initialize MGR's private state, keeping a reference count on each
* call. Initializes the DCD.
* Parameters:
* Returns:
* TRUE if initialized; FALSE if error occurred.
* Requires:
* Ensures:
* TRUE: A requirement for the other public MGR functions.
*/
extern bool mgr_init(void);
#endif /* MGR_ */

45
drivers/staging/tidspbridge/include/dspbridge/mgrpriv.h
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@ -1,45 +0,0 @@
/*
* mgrpriv.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Global MGR constants and types, shared by PROC, MGR, and DSP API.
*
* Copyright (C) 2008 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef MGRPRIV_
#define MGRPRIV_
/*
* OMAP1510 specific
*/
#define MGR_MAXTLBENTRIES 32
/* RM MGR Object */
struct mgr_object;
struct mgr_tlbentry {
u32 dsp_virt; /* DSP virtual address */
u32 gpp_phys; /* GPP physical address */
};
/*
* The DSP_PROCESSOREXTINFO structure describes additional extended
* capabilities of a DSP processor not exposed to user.
*/
struct mgr_processorextinfo {
struct dsp_processorinfo ty_basic; /* user processor info */
/* private dsp mmu entries */
struct mgr_tlbentry ty_tlb[MGR_MAXTLBENTRIES];
};
#endif /* MGRPRIV_ */

59
drivers/staging/tidspbridge/include/dspbridge/msg.h
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@ -1,59 +0,0 @@
/*
* msg.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* DSP/BIOS Bridge msg_ctrl Module.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef MSG_
#define MSG_
#include <dspbridge/devdefs.h>
#include <dspbridge/msgdefs.h>
/*
* ======== msg_create ========
* Purpose:
* Create an object to manage message queues. Only one of these objects
* can exist per device object. The msg_ctrl manager must be created before
* the IO Manager.
* Parameters:
* msg_man: Location to store msg_ctrl manager handle on output.
* hdev_obj: The device object.
* msg_callback: Called whenever an RMS_EXIT message is received.
* Returns:
* Requires:
* msg_man != NULL.
* hdev_obj != NULL.
* msg_callback != NULL.
* Ensures:
*/
extern int msg_create(struct msg_mgr **msg_man,
struct dev_object *hdev_obj,
msg_onexit msg_callback);
/*
* ======== msg_delete ========
* Purpose:
* Delete a msg_ctrl manager allocated in msg_create().
* Parameters:
* hmsg_mgr: Handle returned from msg_create().
* Returns:
* Requires:
* Valid hmsg_mgr.
* Ensures:
*/
extern void msg_delete(struct msg_mgr *hmsg_mgr);
#endif /* MSG_ */

29
drivers/staging/tidspbridge/include/dspbridge/msgdefs.h
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@ -1,29 +0,0 @@
/*
* msgdefs.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Global msg_ctrl constants and types.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef MSGDEFS_
#define MSGDEFS_
/* msg_ctrl Objects: */
struct msg_mgr;
struct msg_queue;
/* Function prototype for callback to be called on RMS_EXIT message received */
typedef void (*msg_onexit) (void *h, s32 node_status);
#endif /* MSGDEFS_ */

55
drivers/staging/tidspbridge/include/dspbridge/nldr.h
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@ -1,55 +0,0 @@
/*
* nldr.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* DSP/BIOS Bridge dynamic loader interface.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#include <dspbridge/dbdefs.h>
#include <dspbridge/dbdcddef.h>
#include <dspbridge/dev.h>
#include <dspbridge/rmm.h>
#include <dspbridge/nldrdefs.h>
#ifndef NLDR_
#define NLDR_
extern int nldr_allocate(struct nldr_object *nldr_obj,
void *priv_ref, const struct dcd_nodeprops
*node_props,
struct nldr_nodeobject **nldr_nodeobj,
bool *pf_phase_split);
extern int nldr_create(struct nldr_object **nldr,
struct dev_object *hdev_obj,
const struct nldr_attrs *pattrs);
extern void nldr_delete(struct nldr_object *nldr_obj);
extern int nldr_get_fxn_addr(struct nldr_nodeobject *nldr_node_obj,
char *str_fxn, u32 * addr);
extern int nldr_get_rmm_manager(struct nldr_object *nldr,
struct rmm_target_obj **rmm_mgr);
extern int nldr_load(struct nldr_nodeobject *nldr_node_obj,
enum nldr_phase phase);
extern int nldr_unload(struct nldr_nodeobject *nldr_node_obj,
enum nldr_phase phase);
#ifdef CONFIG_TIDSPBRIDGE_BACKTRACE
int nldr_find_addr(struct nldr_nodeobject *nldr_node, u32 sym_addr,
u32 offset_range, void *offset_output, char *sym_name);
#endif
#endif /* NLDR_ */

259
drivers/staging/tidspbridge/include/dspbridge/nldrdefs.h
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@ -1,259 +0,0 @@
/*
* nldrdefs.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Global Dynamic + static/overlay Node loader (NLDR) constants and types.
*
* Copyright (C) 2008 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef NLDRDEFS_
#define NLDRDEFS_
#include <dspbridge/dbdcddef.h>
#include <dspbridge/devdefs.h>
#define NLDR_MAXPATHLENGTH 255
/* NLDR Objects: */
struct nldr_object;
struct nldr_nodeobject;
/*
* ======== nldr_loadtype ========
* Load types for a node. Must match values in node.h55.
*/
enum nldr_loadtype {
NLDR_STATICLOAD, /* Linked in base image, not overlay */
NLDR_DYNAMICLOAD, /* Dynamically loaded node */
NLDR_OVLYLOAD /* Linked in base image, overlay node */
};
/*
* ======== nldr_ovlyfxn ========
* Causes code or data to be copied from load address to run address. This
* is the "cod_writefxn" that gets passed to the DBLL_Library and is used as
* the ZL write function.
*
* Parameters:
* priv_ref: Handle to identify the node.
* dsp_run_addr: Run address of code or data.
* dsp_load_addr: Load address of code or data.
* ul_num_bytes: Number of (GPP) bytes to copy.
* mem_space: RMS_CODE or RMS_DATA.
* Returns:
* ul_num_bytes: Success.
* 0: Failure.
* Requires:
* Ensures:
*/
typedef u32(*nldr_ovlyfxn) (void *priv_ref, u32 dsp_run_addr,
u32 dsp_load_addr, u32 ul_num_bytes, u32 mem_space);
/*
* ======== nldr_writefxn ========
* Write memory function. Used for dynamic load writes.
* Parameters:
* priv_ref: Handle to identify the node.
* dsp_add: Address of code or data.
* pbuf: Code or data to be written
* ul_num_bytes: Number of (GPP) bytes to write.
* mem_space: DBLL_DATA or DBLL_CODE.
* Returns:
* ul_num_bytes: Success.
* 0: Failure.
* Requires:
* Ensures:
*/
typedef u32(*nldr_writefxn) (void *priv_ref,
u32 dsp_add, void *pbuf,
u32 ul_num_bytes, u32 mem_space);
/*
* ======== nldr_attrs ========
* Attributes passed to nldr_create function.
*/
struct nldr_attrs {
nldr_ovlyfxn ovly;
nldr_writefxn write;
u16 dsp_word_size;
u16 dsp_mau_size;
};
/*
* ======== nldr_phase ========
* Indicates node create, delete, or execute phase function.
*/
enum nldr_phase {
NLDR_CREATE,
NLDR_DELETE,
NLDR_EXECUTE,
NLDR_NOPHASE
};
/*
* Typedefs of loader functions imported from a DLL, or defined in a
* function table.
*/
/*
* ======== nldr_allocate ========
* Allocate resources to manage the loading of a node on the DSP.
*
* Parameters:
* nldr_obj: Handle of loader that will load the node.
* priv_ref: Handle to identify the node.
* node_props: Pointer to a dcd_nodeprops for the node.
* nldr_nodeobj: Location to store node handle on output. This handle
* will be passed to nldr_load/nldr_unload.
* pf_phase_split: pointer to int variable referenced in node.c
* Returns:
* 0: Success.
* -ENOMEM: Insufficient memory on GPP.
* Requires:
* Valid nldr_obj.
* node_props != NULL.
* nldr_nodeobj != NULL.
* Ensures:
* 0: IsValidNode(*nldr_nodeobj).
* error: *nldr_nodeobj == NULL.
*/
typedef int(*nldr_allocatefxn) (struct nldr_object *nldr_obj,
void *priv_ref,
const struct dcd_nodeprops
* node_props,
struct nldr_nodeobject
**nldr_nodeobj,
bool *pf_phase_split);
/*
* ======== nldr_create ========
* Create a loader object. This object handles the loading and unloading of
* create, delete, and execute phase functions of nodes on the DSP target.
*
* Parameters:
* nldr: Location to store loader handle on output.
* hdev_obj: Device for this processor.
* pattrs: Loader attributes.
* Returns:
* 0: Success;
* -ENOMEM: Insufficient memory for requested resources.
* Requires:
* nldr != NULL.
* hdev_obj != NULL.
* pattrs != NULL.
* Ensures:
* 0: Valid *nldr.
* error: *nldr == NULL.
*/
typedef int(*nldr_createfxn) (struct nldr_object **nldr,
struct dev_object *hdev_obj,
const struct nldr_attrs *pattrs);
/*
* ======== nldr_delete ========
* Delete the NLDR loader.
*
* Parameters:
* nldr_obj: Node manager object.
* Returns:
* Requires:
* Valid nldr_obj.
* Ensures:
* nldr_obj invalid
*/
typedef void (*nldr_deletefxn) (struct nldr_object *nldr_obj);
/*
* ======== NLDR_Free ========
* Free resources allocated in nldr_allocate.
*
* Parameters:
* nldr_node_obj: Handle returned from nldr_allocate().
* Returns:
* Requires:
* Valid nldr_node_obj.
* Ensures:
*/
typedef void (*nldr_freefxn) (struct nldr_nodeobject *nldr_node_obj);
/*
* ======== nldr_get_fxn_addr ========
* Get address of create, delete, or execute phase function of a node on
* the DSP.
*
* Parameters:
* nldr_node_obj: Handle returned from nldr_allocate().
* str_fxn: Name of function.
* addr: Location to store function address.
* Returns:
* 0: Success.
* -ESPIPE: Address of function not found.
* Requires:
* Valid nldr_node_obj.
* addr != NULL;
* str_fxn != NULL;
* Ensures:
*/
typedef int(*nldr_getfxnaddrfxn) (struct nldr_nodeobject
* nldr_node_obj,
char *str_fxn, u32 * addr);
/*
* ======== nldr_load ========
* Load create, delete, or execute phase function of a node on the DSP.
*
* Parameters:
* nldr_node_obj: Handle returned from nldr_allocate().
* phase: Type of function to load (create, delete, or execute).
* Returns:
* 0: Success.
* -ENOMEM: Insufficient memory on GPP.
* -ENXIO: Can't overlay phase because overlay memory
* is already in use.
* -EILSEQ: Failure in dynamic loader library.
* Requires:
* Valid nldr_node_obj.
* Ensures:
*/
typedef int(*nldr_loadfxn) (struct nldr_nodeobject *nldr_node_obj,
enum nldr_phase phase);
/*
* ======== nldr_unload ========
* Unload create, delete, or execute phase function of a node on the DSP.
*
* Parameters:
* nldr_node_obj: Handle returned from nldr_allocate().
* phase: Node function to unload (create, delete, or execute).
* Returns:
* 0: Success.
* -ENOMEM: Insufficient memory on GPP.
* Requires:
* Valid nldr_node_obj.
* Ensures:
*/
typedef int(*nldr_unloadfxn) (struct nldr_nodeobject *nldr_node_obj,
enum nldr_phase phase);
/*
* ======== node_ldr_fxns ========
*/
struct node_ldr_fxns {
nldr_allocatefxn allocate;
nldr_createfxn create;
nldr_deletefxn delete;
nldr_getfxnaddrfxn get_fxn_addr;
nldr_loadfxn load;
nldr_unloadfxn unload;
};
#endif /* NLDRDEFS_ */

524
drivers/staging/tidspbridge/include/dspbridge/node.h
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@ -1,524 +0,0 @@
/*
* node.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* DSP/BIOS Bridge Node Manager.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef NODE_
#define NODE_
#include <dspbridge/procpriv.h>
#include <dspbridge/nodedefs.h>
#include <dspbridge/disp.h>
#include <dspbridge/nldrdefs.h>
#include <dspbridge/drv.h>
/*
* ======== node_allocate ========
* Purpose:
* Allocate GPP resources to manage a node on the DSP.
* Parameters:
* hprocessor: Handle of processor that is allocating the node.
* node_uuid: Pointer to a dsp_uuid for the node.
* pargs: Optional arguments to be passed to the node.
* attr_in: Optional pointer to node attributes (priority,
* timeout...)
* noderes: Location to store node resource info.
* Returns:
* 0: Success.
* -ENOMEM: Insufficient memory on GPP.
* -ENOKEY: Node UUID has not been registered.
* -ESPIPE: iAlg functions not found for a DAIS node.
* -EDOM: attr_in != NULL and attr_in->prio out of
* range.
* -EPERM: A failure occurred, unable to allocate node.
* -EBADR: Proccessor is not in the running state.
* Requires:
* hprocessor != NULL.
* node_uuid != NULL.
* noderes != NULL.
* Ensures:
* 0: IsValidNode(*ph_node).
* error: *noderes == NULL.
*/
extern int node_allocate(struct proc_object *hprocessor,
const struct dsp_uuid *node_uuid,
const struct dsp_cbdata
*pargs, const struct dsp_nodeattrin
*attr_in,
struct node_res_object **noderes,
struct process_context *pr_ctxt);
/*
* ======== node_alloc_msg_buf ========
* Purpose:
* Allocate and Prepare a buffer whose descriptor will be passed to a
* Node within a (dsp_msg)message
* Parameters:
* hnode: The node handle.
* usize: The size of the buffer to be allocated.
* pattr: Pointer to a dsp_bufferattr structure.
* pbuffer: Location to store the address of the allocated
* buffer on output.
* Returns:
* 0: Success.
* -EFAULT: Invalid node handle.
* -ENOMEM: Insufficent memory.
* -EPERM: General Failure.
* -EINVAL: Invalid Size.
* Requires:
* pbuffer != NULL.
* Ensures:
*/
extern int node_alloc_msg_buf(struct node_object *hnode,
u32 usize, struct dsp_bufferattr
*pattr, u8 **pbuffer);
/*
* ======== node_change_priority ========
* Purpose:
* Change the priority of an allocated node.
* Parameters:
* hnode: Node handle returned from node_allocate.
* prio: New priority level to set node's priority to.
* Returns:
* 0: Success.
* -EFAULT: Invalid hnode.
* -EDOM: prio is out of range.
* -EPERM: The specified node is not a task node.
* Unable to change node's runtime priority level.
* -EBADR: Node is not in the NODE_ALLOCATED, NODE_PAUSED,
* or NODE_RUNNING state.
* -ETIME: A timeout occurred before the DSP responded.
* Requires:
* Ensures:
* 0 && (Node's current priority == prio)
*/
extern int node_change_priority(struct node_object *hnode, s32 prio);
/*
* ======== node_connect ========
* Purpose:
* Connect two nodes on the DSP, or a node on the DSP to the GPP. In the
* case that the connection is being made between a node on the DSP and
* the GPP, one of the node handles (either node1 or node2) must be
* the constant NODE_HGPPNODE.
* Parameters:
* node1: Handle of first node to connect to second node. If
* this is a connection from the GPP to node2, node1
* must be the constant NODE_HGPPNODE. Otherwise, node1
* must be a node handle returned from a successful call
* to Node_Allocate().
* node2: Handle of second node. Must be either NODE_HGPPNODE
* if this is a connection from DSP node to GPP, or a
* node handle returned from a successful call to
* node_allocate().
* stream1: Output stream index on first node, to be connected
* to second node's input stream. Value must range from
* 0 <= stream1 < number of output streams.
* stream2: Input stream index on second node. Value must range
* from 0 <= stream2 < number of input streams.
* pattrs: Stream attributes (NULL ==> use defaults).
* conn_param: A pointer to a dsp_cbdata structure that defines
* connection parameter for device nodes to pass to DSP
* side.
* If the value of this parameter is NULL, then this API
* behaves like DSPNode_Connect. This parameter will have
* length of the string and the null terminated string in
* dsp_cbdata struct. This can be extended in future tp
* pass binary data.
* Returns:
* 0: Success.
* -EFAULT: Invalid node1 or node2.
* -ENOMEM: Insufficient host memory.
* -EINVAL: A stream index parameter is invalid.
* -EISCONN: A connection already exists for one of the
* indices stream1 or stream2.
* -EBADR: Either node1 or node2 is not in the
* NODE_ALLOCATED state.
* -ECONNREFUSED: No more connections available.
* -EPERM: Attempt to make an illegal connection (eg,
* Device node to device node, or device node to
* GPP), the two nodes are on different DSPs.
* Requires:
* Ensures:
*/
extern int node_connect(struct node_object *node1,
u32 stream1,
struct node_object *node2,
u32 stream2,
struct dsp_strmattr *pattrs,
struct dsp_cbdata
*conn_param);
/*
* ======== node_create ========
* Purpose:
* Create a node on the DSP by remotely calling the node's create
* function. If necessary, load code that contains the node's create
* function.
* Parameters:
* hnode: Node handle returned from node_allocate().
* Returns:
* 0: Success.
* -EFAULT: Invalid hnode.
* -ESPIPE: Create function not found in the COFF file.
* -EBADR: Node is not in the NODE_ALLOCATED state.
* -ENOMEM: Memory allocation failure on the DSP.
* -ETIME: A timeout occurred before the DSP responded.
* -EPERM: A failure occurred, unable to create node.
* Requires:
* Ensures:
*/
extern int node_create(struct node_object *hnode);
/*
* ======== node_create_mgr ========
* Purpose:
* Create a NODE Manager object. This object handles the creation,
* deletion, and execution of nodes on the DSP target. The NODE Manager
* also maintains a pipe map of used and available node connections.
* Each DEV object should have exactly one NODE Manager object.
*
* Parameters:
* node_man: Location to store node manager handle on output.
* hdev_obj: Device for this processor.
* Returns:
* 0: Success;
* -ENOMEM: Insufficient memory for requested resources.
* -EPERM: General failure.
* Requires:
* node_man != NULL.
* hdev_obj != NULL.
* Ensures:
* 0: Valide *node_man.
* error: *node_man == NULL.
*/
extern int node_create_mgr(struct node_mgr **node_man,
struct dev_object *hdev_obj);
/*
* ======== node_delete ========
* Purpose:
* Delete resources allocated in node_allocate(). If the node was
* created, delete the node on the DSP by remotely calling the node's
* delete function. Loads the node's delete function if necessary.
* GPP side resources are freed after node's delete function returns.
* Parameters:
* noderes: Node resource info handle returned from
* node_allocate().
* pr_ctxt: Pointer to process context data.
* Returns:
* 0: Success.
* -EFAULT: Invalid hnode.
* -ETIME: A timeout occurred before the DSP responded.
* -EPERM: A failure occurred in deleting the node.
* -ESPIPE: Delete function not found in the COFF file.
* Requires:
* Ensures:
* 0: hnode is invalid.
*/
extern int node_delete(struct node_res_object *noderes,
struct process_context *pr_ctxt);
/*
* ======== node_delete_mgr ========
* Purpose:
* Delete the NODE Manager.
* Parameters:
* hnode_mgr: Node manager object.
* Returns:
* 0: Success.
* Requires:
* Valid hnode_mgr.
* Ensures:
*/
extern int node_delete_mgr(struct node_mgr *hnode_mgr);
/*
* ======== node_enum_nodes ========
* Purpose:
* Enumerate the nodes currently allocated for the DSP.
* Parameters:
* hnode_mgr: Node manager returned from node_create_mgr().
* node_tab: Array to copy node handles into.
* node_tab_size: Number of handles that can be written to node_tab.
* pu_num_nodes: Location where number of node handles written to
* node_tab will be written.
* pu_allocated: Location to write total number of allocated nodes.
* Returns:
* 0: Success.
* -EINVAL: node_tab is too small to hold all node handles.
* Requires:
* Valid hnode_mgr.
* node_tab != NULL || node_tab_size == 0.
* pu_num_nodes != NULL.
* pu_allocated != NULL.
* Ensures:
* - (-EINVAL && *pu_num_nodes == 0)
* - || (0 && *pu_num_nodes <= node_tab_size) &&
* (*pu_allocated == *pu_num_nodes)
*/
extern int node_enum_nodes(struct node_mgr *hnode_mgr,
void **node_tab,
u32 node_tab_size,
u32 *pu_num_nodes,
u32 *pu_allocated);
/*
* ======== node_free_msg_buf ========
* Purpose:
* Free a message buffer previously allocated with node_alloc_msg_buf.
* Parameters:
* hnode: The node handle.
* pbuffer: (Address) Buffer allocated by node_alloc_msg_buf.
* pattr: Same buffer attributes passed to node_alloc_msg_buf.
* Returns:
* 0: Success.
* -EFAULT: Invalid node handle.
* -EPERM: Failure to free the buffer.
* Requires:
* pbuffer != NULL.
* Ensures:
*/
extern int node_free_msg_buf(struct node_object *hnode,
u8 *pbuffer,
struct dsp_bufferattr
*pattr);
/*
* ======== node_get_attr ========
* Purpose:
* Copy the current attributes of the specified node into a dsp_nodeattr
* structure.
* Parameters:
* hnode: Node object allocated from node_allocate().
* pattr: Pointer to dsp_nodeattr structure to copy node's
* attributes.
* attr_size: Size of pattr.
* Returns:
* 0: Success.
* -EFAULT: Invalid hnode.
* Requires:
* pattr != NULL.
* Ensures:
* 0: *pattrs contains the node's current attributes.
*/
extern int node_get_attr(struct node_object *hnode,
struct dsp_nodeattr *pattr, u32 attr_size);
/*
* ======== node_get_message ========
* Purpose:
* Retrieve a message from a node on the DSP. The node must be either a
* message node, task node, or XDAIS socket node.
* If a message is not available, this function will block until a
* message is available, or the node's timeout value is reached.
* Parameters:
* hnode: Node handle returned from node_allocate().
* message: Pointer to dsp_msg structure to copy the
* message into.
* utimeout: Timeout in milliseconds to wait for message.
* Returns:
* 0: Success.
* -EFAULT: Invalid hnode.
* -EPERM: Cannot retrieve messages from this type of node.
* Error occurred while trying to retrieve a message.
* -ETIME: Timeout occurred and no message is available.
* Requires:
* message != NULL.
* Ensures:
*/
extern int node_get_message(struct node_object *hnode,
struct dsp_msg *message, u32 utimeout);
/*
* ======== node_get_nldr_obj ========
* Purpose:
* Retrieve the Nldr manager
* Parameters:
* hnode_mgr: Node Manager
* nldr_ovlyobj: Pointer to a Nldr manager handle
* Returns:
* 0: Success.
* -EFAULT: Invalid hnode.
* Ensures:
*/
extern int node_get_nldr_obj(struct node_mgr *hnode_mgr,
struct nldr_object **nldr_ovlyobj);
/*
* ======== node_on_exit ========
* Purpose:
* Gets called when RMS_EXIT is received for a node. PROC needs to pass
* this function as a parameter to msg_create(). This function then gets
* called by the Bridge driver when an exit message for a node is received.
* Parameters:
* hnode: Handle of the node that the exit message is for.
* node_status: Return status of the node's execute phase.
* Returns:
* Ensures:
*/
void node_on_exit(struct node_object *hnode, s32 node_status);
/*
* ======== node_pause ========
* Purpose:
* Suspend execution of a node currently running on the DSP.
* Parameters:
* hnode: Node object representing a node currently
* running on the DSP.
* Returns:
* 0: Success.
* -EFAULT: Invalid hnode.
* -EPERM: Node is not a task or socket node.
* Failed to pause node.
* -ETIME: A timeout occurred before the DSP responded.
* DSP_EWRONGSTSATE: Node is not in NODE_RUNNING state.
* Requires:
* Ensures:
*/
extern int node_pause(struct node_object *hnode);
/*
* ======== node_put_message ========
* Purpose:
* Send a message to a message node, task node, or XDAIS socket node.
* This function will block until the message stream can accommodate
* the message, or a timeout occurs. The message will be copied, so Msg
* can be re-used immediately after return.
* Parameters:
* hnode: Node handle returned by node_allocate().
* pmsg: Location of message to be sent to the node.
* utimeout: Timeout in msecs to wait.
* Returns:
* 0: Success.
* -EFAULT: Invalid hnode.
* -EPERM: Messages can't be sent to this type of node.
* Unable to send message.
* -ETIME: Timeout occurred before message could be set.
* -EBADR: Node is in invalid state for sending messages.
* Requires:
* pmsg != NULL.
* Ensures:
*/
extern int node_put_message(struct node_object *hnode,
const struct dsp_msg *pmsg, u32 utimeout);
/*
* ======== node_register_notify ========
* Purpose:
* Register to be notified on specific events for this node.
* Parameters:
* hnode: Node handle returned by node_allocate().
* event_mask: Mask of types of events to be notified about.
* notify_type: Type of notification to be sent.
* hnotification: Handle to be used for notification.
* Returns:
* 0: Success.
* -EFAULT: Invalid hnode.
* -ENOMEM: Insufficient memory on GPP.
* -EINVAL: event_mask is invalid.
* -ENOSYS: Notification type specified by notify_type is not
* supported.
* Requires:
* hnotification != NULL.
* Ensures:
*/
extern int node_register_notify(struct node_object *hnode,
u32 event_mask, u32 notify_type,
struct dsp_notification
*hnotification);
/*
* ======== node_run ========
* Purpose:
* Start execution of a node's execute phase, or resume execution of
* a node that has been suspended (via node_pause()) on the DSP. Load
* the node's execute function if necessary.
* Parameters:
* hnode: Node object representing a node currently
* running on the DSP.
* Returns:
* 0: Success.
* -EFAULT: Invalid hnode.
* -EPERM: hnode doesn't represent a message, task or dais socket node.
* Unable to start or resume execution.
* -ETIME: A timeout occurred before the DSP responded.
* DSP_EWRONGSTSATE: Node is not in NODE_PAUSED or NODE_CREATED state.
* -ESPIPE: Execute function not found in the COFF file.
* Requires:
* Ensures:
*/
extern int node_run(struct node_object *hnode);
/*
* ======== node_terminate ========
* Purpose:
* Signal a node running on the DSP that it should exit its execute
* phase function.
* Parameters:
* hnode: Node object representing a node currently
* running on the DSP.
* pstatus: Location to store execute-phase function return
* value.
* Returns:
* 0: Success.
* -EFAULT: Invalid hnode.
* -ETIME: A timeout occurred before the DSP responded.
* -EPERM: Type of node specified cannot be terminated.
* Unable to terminate the node.
* -EBADR: Operation not valid for the current node state.
* Requires:
* pstatus != NULL.
* Ensures:
*/
extern int node_terminate(struct node_object *hnode,
int *pstatus);
/*
* ======== node_get_uuid_props ========
* Purpose:
* Fetch Node properties given the UUID
* Parameters:
*
*/
extern int node_get_uuid_props(void *hprocessor,
const struct dsp_uuid *node_uuid,
struct dsp_ndbprops
*node_props);
#ifdef CONFIG_TIDSPBRIDGE_BACKTRACE
/**
* node_find_addr() - Find the closest symbol to the given address.
*
* @node_mgr: Node manager handle
* @sym_addr: Given address to find the closest symbol
* @offset_range: offset range to look fo the closest symbol
* @sym_addr_output: Symbol Output address
* @sym_name: String with the symbol name of the closest symbol
*
* This function finds the closest symbol to the address where a MMU
* Fault occurred on the DSP side.
*/
int node_find_addr(struct node_mgr *node_mgr, u32 sym_addr,
u32 offset_range, void *sym_addr_output,
char *sym_name);
enum node_state node_get_state(void *hnode);
#endif
#endif /* NODE_ */

28
drivers/staging/tidspbridge/include/dspbridge/nodedefs.h
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@ -1,28 +0,0 @@
/*
* nodedefs.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Global NODE constants and types, shared by PROCESSOR, NODE, and DISP.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef NODEDEFS_
#define NODEDEFS_
#define NODE_SUSPENDEDPRI -1
/* NODE Objects: */
struct node_mgr;
struct node_object;
#endif /* NODEDEFS_ */

181
drivers/staging/tidspbridge/include/dspbridge/nodepriv.h
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@ -1,181 +0,0 @@
/*
* nodepriv.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Private node header shared by NODE and DISP.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef NODEPRIV_
#define NODEPRIV_
#include <dspbridge/strmdefs.h>
#include <dspbridge/nodedefs.h>
#include <dspbridge/nldrdefs.h>
/* DSP address of node environment structure */
typedef u32 nodeenv;
/*
* Node create structures
*/
/* Message node */
struct node_msgargs {
u32 max_msgs; /* Max # of simultaneous messages for node */
u32 seg_id; /* Segment for allocating message buffers */
u32 notify_type; /* Notify type (SEM_post, SWI_post, etc.) */
u32 arg_length; /* Length in 32-bit words of arg data block */
u8 *pdata; /* Argument data for node */
};
struct node_strmdef {
u32 buf_size; /* Size of buffers for SIO stream */
u32 num_bufs; /* max # of buffers in SIO stream at once */
u32 seg_id; /* Memory segment id to allocate buffers */
u32 timeout; /* Timeout for blocking SIO calls */
u32 buf_alignment; /* Buffer alignment */
char *sz_device; /* Device name for stream */
};
/* Task node */
struct node_taskargs {
struct node_msgargs node_msg_args;
s32 prio;
u32 stack_size;
u32 sys_stack_size;
u32 stack_seg;
u32 dsp_heap_res_addr; /* DSP virtual heap address */
u32 dsp_heap_addr; /* DSP virtual heap address */
u32 heap_size; /* Heap size */
u32 gpp_heap_addr; /* GPP virtual heap address */
u32 profile_id; /* Profile ID */
u32 num_inputs;
u32 num_outputs;
u32 dais_arg; /* Address of iAlg object */
struct node_strmdef *strm_in_def;
struct node_strmdef *strm_out_def;
};
/*
* ======== node_createargs ========
*/
struct node_createargs {
union {
struct node_msgargs node_msg_args;
struct node_taskargs task_arg_obj;
} asa;
};
/*
* ======== node_get_channel_id ========
* Purpose:
* Get the channel index reserved for a stream connection between the
* host and a node. This index is reserved when node_connect() is called
* to connect the node with the host. This index should be passed to
* the CHNL_Open function when the stream is actually opened.
* Parameters:
* hnode: Node object allocated from node_allocate().
* dir: Input (DSP_TONODE) or output (DSP_FROMNODE).
* index: Stream index.
* chan_id: Location to store channel index.
* Returns:
* 0: Success.
* -EFAULT: Invalid hnode.
* -EPERM: Not a task or DAIS socket node.
* -EINVAL: The node's stream corresponding to index and dir
* is not a stream to or from the host.
* Requires:
* Valid dir.
* chan_id != NULL.
* Ensures:
*/
extern int node_get_channel_id(struct node_object *hnode,
u32 dir, u32 index, u32 *chan_id);
/*
* ======== node_get_strm_mgr ========
* Purpose:
* Get the STRM manager for a node.
* Parameters:
* hnode: Node allocated with node_allocate().
* strm_man: Location to store STRM manager on output.
* Returns:
* 0: Success.
* -EFAULT: Invalid hnode.
* Requires:
* strm_man != NULL.
* Ensures:
*/
extern int node_get_strm_mgr(struct node_object *hnode,
struct strm_mgr **strm_man);
/*
* ======== node_get_timeout ========
* Purpose:
* Get the timeout value of a node.
* Parameters:
* hnode: Node allocated with node_allocate(), or DSP_HGPPNODE.
* Returns:
* Node's timeout value.
* Requires:
* Valid hnode.
* Ensures:
*/
extern u32 node_get_timeout(struct node_object *hnode);
/*
* ======== node_get_type ========
* Purpose:
* Get the type (device, message, task, or XDAIS socket) of a node.
* Parameters:
* hnode: Node allocated with node_allocate(), or DSP_HGPPNODE.
* Returns:
* Node type: NODE_DEVICE, NODE_TASK, NODE_XDAIS, or NODE_GPP.
* Requires:
* Valid hnode.
* Ensures:
*/
extern enum node_type node_get_type(struct node_object *hnode);
/*
* ======== get_node_info ========
* Purpose:
* Get node information without holding semaphore.
* Parameters:
* hnode: Node allocated with node_allocate(), or DSP_HGPPNODE.
* Returns:
* Node info: priority, device owner, no. of streams, execution state
* NDB properties.
* Requires:
* Valid hnode.
* Ensures:
*/
extern void get_node_info(struct node_object *hnode,
struct dsp_nodeinfo *node_info);
/*
* ======== node_get_load_type ========
* Purpose:
* Get the load type (dynamic, overlay, static) of a node.
* Parameters:
* hnode: Node allocated with node_allocate(), or DSP_HGPPNODE.
* Returns:
* Node type: NLDR_DYNAMICLOAD, NLDR_OVLYLOAD, NLDR_STATICLOAD
* Requires:
* Valid hnode.
* Ensures:
*/
extern enum nldr_loadtype node_get_load_type(struct node_object *hnode);
#endif /* NODEPRIV_ */

217
drivers/staging/tidspbridge/include/dspbridge/ntfy.h
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@ -1,217 +0,0 @@
/*
* ntfy.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Manage lists of notification events.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef NTFY_
#define NTFY_
#include <dspbridge/host_os.h>
#include <dspbridge/dbdefs.h>
#include <dspbridge/sync.h>
/**
* ntfy_object - head structure to nofify dspbridge events
* @head: List of notify objects
* @ntfy_lock: lock for list access.
*
*/
struct ntfy_object {
struct raw_notifier_head head;/* List of notifier objects */
spinlock_t ntfy_lock; /* For critical sections */
};
/**
* ntfy_event - structure store specify event to be notified
* @noti_block: List of notify objects
* @event: event that it respond
* @type: event type (only DSP_SIGNALEVENT supported)
* @sync_obj: sync_event used to set the event
*
*/
struct ntfy_event {
struct notifier_block noti_block;
u32 event; /* Events to be notified about */
u32 type; /* Type of notification to be sent */
struct sync_object sync_obj;
};
/**
* dsp_notifier_event() - callback function to nofity events
* @this: pointer to itself struct notifier_block
* @event: event to be notified.
* @data: Currently not used.
*
*/
int dsp_notifier_event(struct notifier_block *this, unsigned long event,
void *data);
/**
* ntfy_init() - Set the initial state of the ntfy_object structure.
* @no: pointer to ntfy_object structure.
*
* This function sets the initial state of the ntfy_object in order it
* can be used by the other ntfy functions.
*/
static inline void ntfy_init(struct ntfy_object *no)
{
spin_lock_init(&no->ntfy_lock);
RAW_INIT_NOTIFIER_HEAD(&no->head);
}
/**
* ntfy_delete() - delete list of nofy events registered.
* @ntfy_obj: Pointer to the ntfy object structure.
*
* This function is used to remove all the notify events registered.
* unregister function is not needed in this function, to unregister
* a ntfy_event please look at ntfy_register function.
*
*/
static inline void ntfy_delete(struct ntfy_object *ntfy_obj)
{
struct ntfy_event *ne;
struct notifier_block *nb;
spin_lock_bh(&ntfy_obj->ntfy_lock);
nb = ntfy_obj->head.head;
while (nb) {
ne = container_of(nb, struct ntfy_event, noti_block);
nb = nb->next;
kfree(ne);
}
spin_unlock_bh(&ntfy_obj->ntfy_lock);
}
/**
* ntfy_notify() - nofity all event register for an specific event.
* @ntfy_obj: Pointer to the ntfy_object structure.
* @event: event to be notified.
*
* This function traverses all the ntfy events registers and
* set the event with mach with @event.
*/
static inline void ntfy_notify(struct ntfy_object *ntfy_obj, u32 event)
{
spin_lock_bh(&ntfy_obj->ntfy_lock);
raw_notifier_call_chain(&ntfy_obj->head, event, NULL);
spin_unlock_bh(&ntfy_obj->ntfy_lock);
}
/**
* ntfy_init() - Create and initialize a ntfy_event structure.
* @event: event that the ntfy event will respond
* @type event type (only DSP_SIGNALEVENT supported)
*
* This function create a ntfy_event element and sets the event it will
* respond the ntfy_event in order it can be used by the other ntfy functions.
* In case of success it will return a pointer to the ntfy_event struct
* created. Otherwise it will return NULL;
*/
static inline struct ntfy_event *ntfy_event_create(u32 event, u32 type)
{
struct ntfy_event *ne;
ne = kmalloc(sizeof(struct ntfy_event), GFP_KERNEL);
if (ne) {
sync_init_event(&ne->sync_obj);
ne->noti_block.notifier_call = dsp_notifier_event;
ne->event = event;
ne->type = type;
}
return ne;
}
/**
* ntfy_register() - register new ntfy_event into a given ntfy_object
* @ntfy_obj: Pointer to the ntfy_object structure.
* @noti: Pointer to the handle to be returned to the user space.
* @event event that the ntfy event will respond
* @type event type (only DSP_SIGNALEVENT supported)
*
* This function register a new ntfy_event into the ntfy_object list,
* which will respond to the @event passed.
* This function will return 0 in case of error.
* -EFAULT in case of bad pointers and
* DSP_EMemory in case of no memory to create ntfy_event.
*/
static inline int ntfy_register(struct ntfy_object *ntfy_obj,
struct dsp_notification *noti,
u32 event, u32 type)
{
struct ntfy_event *ne;
int status = 0;
if (!noti || !ntfy_obj) {
status = -EFAULT;
goto func_end;
}
if (!event) {
status = -EINVAL;
goto func_end;
}
ne = ntfy_event_create(event, type);
if (!ne) {
status = -ENOMEM;
goto func_end;
}
noti->handle = &ne->sync_obj;
spin_lock_bh(&ntfy_obj->ntfy_lock);
raw_notifier_chain_register(&ntfy_obj->head, &ne->noti_block);
spin_unlock_bh(&ntfy_obj->ntfy_lock);
func_end:
return status;
}
/**
* ntfy_unregister() - unregister a ntfy_event from a given ntfy_object
* @ntfy_obj: Pointer to the ntfy_object structure.
* @noti: Pointer to the event that will be removed.
*
* This function unregister a ntfy_event from the ntfy_object list,
* @noti contains the event which is wanted to be removed.
* This function will return 0 in case of error.
* -EFAULT in case of bad pointers and
* DSP_EMemory in case of no memory to create ntfy_event.
*/
static inline int ntfy_unregister(struct ntfy_object *ntfy_obj,
struct dsp_notification *noti)
{
int status = 0;
struct ntfy_event *ne;
if (!noti || !ntfy_obj) {
status = -EFAULT;
goto func_end;
}
ne = container_of((struct sync_object *)noti, struct ntfy_event,
sync_obj);
spin_lock_bh(&ntfy_obj->ntfy_lock);
raw_notifier_chain_unregister(&ntfy_obj->head,
&ne->noti_block);
kfree(ne);
spin_unlock_bh(&ntfy_obj->ntfy_lock);
func_end:
return status;
}
#endif /* NTFY_ */

591
drivers/staging/tidspbridge/include/dspbridge/proc.h
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@ -1,591 +0,0 @@
/*
* proc.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* This is the DSP API RM module interface.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef PROC_
#define PROC_
#include <dspbridge/cfgdefs.h>
#include <dspbridge/devdefs.h>
#include <dspbridge/drv.h>
/*
* ======== proc_attach ========
* Purpose:
* Prepare for communication with a particular DSP processor, and return
* a handle to the processor object. The PROC Object gets created
* Parameters:
* processor_id : The processor index (zero-based).
* hmgr_obj : Handle to the Manager Object
* attr_in : Ptr to the dsp_processorattrin structure.
* A NULL value means use default values.
* ph_processor : Ptr to location to store processor handle.
* Returns:
* 0 : Success.
* -EPERM : General failure.
* -EFAULT : Invalid processor handle.
* 0: Success; Processor already attached.
* Requires:
* ph_processor != NULL.
* PROC Initialized.
* Ensures:
* -EPERM, and *ph_processor == NULL, OR
* Success and *ph_processor is a Valid Processor handle OR
* 0 and *ph_processor is a Valid Processor.
* Details:
* When attr_in is NULL, the default timeout value is 10 seconds.
*/
extern int proc_attach(u32 processor_id,
const struct dsp_processorattrin
*attr_in, void **ph_processor,
struct process_context *pr_ctxt);
/*
* ======== proc_auto_start =========
* Purpose:
* A Particular device gets loaded with the default image
* if the AutoStart flag is set.
* Parameters:
* hdev_obj : Handle to the Device
* Returns:
* 0 : On Successful Loading
* -ENOENT : No DSP exec file found.
* -EPERM : General Failure
* Requires:
* hdev_obj != NULL.
* dev_node_obj != NULL.
* PROC Initialized.
* Ensures:
*/
extern int proc_auto_start(struct cfg_devnode *dev_node_obj,
struct dev_object *hdev_obj);
/*
* ======== proc_ctrl ========
* Purpose:
* Pass control information to the GPP device driver managing the DSP
* processor. This will be an OEM-only function, and not part of the
* 'Bridge application developer's API.
* Parameters:
* hprocessor : The processor handle.
* dw_cmd : Private driver IOCTL cmd ID.
* pargs : Ptr to an driver defined argument structure.
* Returns:
* 0 : SUCCESS
* -EFAULT : Invalid processor handle.
* -ETIME: A Timeout Occurred before the Control information
* could be sent.
* -EPERM : General Failure.
* Requires:
* PROC Initialized.
* Ensures
* Details:
* This function Calls bridge_dev_ctrl.
*/
extern int proc_ctrl(void *hprocessor,
u32 dw_cmd, struct dsp_cbdata *arg);
/*
* ======== proc_detach ========
* Purpose:
* Close a DSP processor and de-allocate all (GPP) resources reserved
* for it. The Processor Object is deleted.
* Parameters:
* pr_ctxt : The processor handle.
* Returns:
* 0 : Success.
* -EFAULT : InValid Handle.
* -EPERM : General failure.
* Requires:
* PROC Initialized.
* Ensures:
* PROC Object is destroyed.
*/
extern int proc_detach(struct process_context *pr_ctxt);
/*
* ======== proc_enum_nodes ========
* Purpose:
* Enumerate the nodes currently allocated on a processor.
* Parameters:
* hprocessor : The processor handle.
* node_tab : The first Location of an array allocated for node
* handles.
* node_tab_size: The number of (DSP_HNODE) handles that can be held
* to the memory the client has allocated for node_tab
* pu_num_nodes : Location where DSPProcessor_EnumNodes will return
* the number of valid handles written to node_tab
* pu_allocated : Location where DSPProcessor_EnumNodes will return
* the number of nodes that are allocated on the DSP.
* Returns:
* 0 : Success.
* -EFAULT : Invalid processor handle.
* -EINVAL : The amount of memory allocated for node_tab is
* insufficent. That is the number of nodes actually
* allocated on the DSP is greater than the value
* specified for node_tab_size.
* -EPERM : Unable to get Resource Information.
* Details:
* Requires
* pu_num_nodes is not NULL.
* pu_allocated is not NULL.
* node_tab is not NULL.
* PROC Initialized.
* Ensures:
* Details:
*/
extern int proc_enum_nodes(void *hprocessor,
void **node_tab,
u32 node_tab_size,
u32 *pu_num_nodes,
u32 *pu_allocated);
/*
* ======== proc_get_resource_info ========
* Purpose:
* Enumerate the resources currently available on a processor.
* Parameters:
* hprocessor : The processor handle.
* resource_type: Type of resource .
* resource_info: Ptr to the dsp_resourceinfo structure.
* resource_info_size: Size of the structure.
* Returns:
* 0 : Success.
* -EFAULT : Invalid processor handle.
* -EBADR: The processor is not in the PROC_RUNNING state.
* -ETIME: A timeout occurred before the DSP responded to the
* querry.
* -EPERM : Unable to get Resource Information
* Requires:
* resource_info is not NULL.
* Parameter resource_type is Valid.[TBD]
* resource_info_size is >= sizeof dsp_resourceinfo struct.
* PROC Initialized.
* Ensures:
* Details:
* This function currently returns
* -ENOSYS, and does not write any data to the resource_info struct.
*/
extern int proc_get_resource_info(void *hprocessor,
u32 resource_type,
struct dsp_resourceinfo
*resource_info,
u32 resource_info_size);
/*
* ======== proc_get_dev_object =========
* Purpose:
* Returns the DEV Hanlde for a given Processor handle
* Parameters:
* hprocessor : Processor Handle
* device_obj : Location to store the DEV Handle.
* Returns:
* 0 : Success; *device_obj has Dev handle
* -EPERM : Failure; *device_obj is zero.
* Requires:
* device_obj is not NULL
* PROC Initialized.
* Ensures:
* 0 : *device_obj is not NULL
* -EPERM : *device_obj is NULL.
*/
extern int proc_get_dev_object(void *hprocessor,
struct dev_object **device_obj);
/*
* ======== proc_get_state ========
* Purpose:
* Report the state of the specified DSP processor.
* Parameters:
* hprocessor : The processor handle.
* proc_state_obj : Ptr to location to store the dsp_processorstate
* structure.
* state_info_size: Size of dsp_processorstate.
* Returns:
* 0 : Success.
* -EFAULT : Invalid processor handle.
* -EPERM : General failure while querying processor state.
* Requires:
* proc_state_obj is not NULL
* state_info_size is >= than the size of dsp_processorstate structure.
* PROC Initialized.
* Ensures:
* Details:
*/
extern int proc_get_state(void *hprocessor, struct dsp_processorstate
*proc_state_obj, u32 state_info_size);
/*
* ======== PROC_GetProcessorID ========
* Purpose:
* Report the state of the specified DSP processor.
* Parameters:
* hprocessor : The processor handle.
* proc_id : Processor ID
*
* Returns:
* 0 : Success.
* -EFAULT : Invalid processor handle.
* -EPERM : General failure while querying processor state.
* Requires:
* proc_state_obj is not NULL
* state_info_size is >= than the size of dsp_processorstate structure.
* PROC Initialized.
* Ensures:
* Details:
*/
extern int proc_get_processor_id(void *proc, u32 * proc_id);
/*
* ======== proc_get_trace ========
* Purpose:
* Retrieve the trace buffer from the specified DSP processor.
* Parameters:
* hprocessor : The processor handle.
* pbuf : Ptr to buffer to hold trace output.
* max_size : Maximum size of the output buffer.
* Returns:
* 0 : Success.
* -EFAULT : Invalid processor handle.
* -EPERM : General failure while retrieving processor trace
* Buffer.
* Requires:
* pbuf is not NULL
* max_size is > 0.
* PROC Initialized.
* Ensures:
* Details:
*/
extern int proc_get_trace(void *hprocessor, u8 * pbuf, u32 max_size);
/*
* ======== proc_load ========
* Purpose:
* Reset a processor and load a new base program image.
* This will be an OEM-only function.
* Parameters:
* hprocessor: The processor handle.
* argc_index: The number of Arguments(strings)in the aArgV[]
* user_args: An Array of Arguments(Unicode Strings)
* user_envp: An Array of Environment settings(Unicode Strings)
* Returns:
* 0: Success.
* -ENOENT: The DSP Executable was not found.
* -EFAULT: Invalid processor handle.
* -EPERM : Unable to Load the Processor
* Requires:
* user_args is not NULL
* argc_index is > 0
* PROC Initialized.
* Ensures:
* Success and ProcState == PROC_LOADED
* or DSP_FAILED status.
* Details:
* Does not implement access rights to control which GPP application
* can load the processor.
*/
extern int proc_load(void *hprocessor,
const s32 argc_index, const char **user_args,
const char **user_envp);
/*
* ======== proc_register_notify ========
* Purpose:
* Register to be notified of specific processor events
* Parameters:
* hprocessor : The processor handle.
* event_mask : Mask of types of events to be notified about.
* notify_type : Type of notification to be sent.
* hnotification: Handle to be used for notification.
* Returns:
* 0 : Success.
* -EFAULT : Invalid processor handle or hnotification.
* -EINVAL : Parameter event_mask is Invalid
* DSP_ENOTIMP : The notification type specified in uNotifyMask
* is not supported.
* -EPERM : Unable to register for notification.
* Requires:
* hnotification is not NULL
* PROC Initialized.
* Ensures:
* Details:
*/
extern int proc_register_notify(void *hprocessor,
u32 event_mask, u32 notify_type,
struct dsp_notification
*hnotification);
/*
* ======== proc_notify_clients ========
* Purpose:
* Notify the Processor Clients
* Parameters:
* proc : The processor handle.
* events : Event to be notified about.
* Returns:
* 0 : Success.
* -EFAULT : Invalid processor handle.
* -EPERM : Failure to Set or Reset the Event
* Requires:
* events is Supported or Valid type of Event
* proc is a valid handle
* PROC Initialized.
* Ensures:
*/
extern int proc_notify_clients(void *proc, u32 events);
/*
* ======== proc_notify_all_clients ========
* Purpose:
* Notify the Processor Clients
* Parameters:
* proc : The processor handle.
* events : Event to be notified about.
* Returns:
* 0 : Success.
* -EFAULT : Invalid processor handle.
* -EPERM : Failure to Set or Reset the Event
* Requires:
* events is Supported or Valid type of Event
* proc is a valid handle
* PROC Initialized.
* Ensures:
* Details:
* NODE And STRM would use this function to notify their clients
* about the state changes in NODE or STRM.
*/
extern int proc_notify_all_clients(void *proc, u32 events);
/*
* ======== proc_start ========
* Purpose:
* Start a processor running.
* Processor must be in PROC_LOADED state.
* This will be an OEM-only function, and not part of the 'Bridge
* application developer's API.
* Parameters:
* hprocessor : The processor handle.
* Returns:
* 0 : Success.
* -EFAULT : Invalid processor handle.
* -EBADR: Processor is not in PROC_LOADED state.
* -EPERM : Unable to start the processor.
* Requires:
* PROC Initialized.
* Ensures:
* Success and ProcState == PROC_RUNNING or DSP_FAILED status.
* Details:
*/
extern int proc_start(void *hprocessor);
/*
* ======== proc_stop ========
* Purpose:
* Start a processor running.
* Processor must be in PROC_LOADED state.
* This will be an OEM-only function, and not part of the 'Bridge
* application developer's API.
* Parameters:
* hprocessor : The processor handle.
* Returns:
* 0 : Success.
* -EFAULT : Invalid processor handle.
* -EBADR: Processor is not in PROC_LOADED state.
* -EPERM : Unable to start the processor.
* Requires:
* PROC Initialized.
* Ensures:
* Success and ProcState == PROC_RUNNING or DSP_FAILED status.
* Details:
*/
extern int proc_stop(void *hprocessor);
/*
* ======== proc_end_dma ========
* Purpose:
* Begin a DMA transfer
* Parameters:
* hprocessor : The processor handle.
* pmpu_addr : Buffer start address
* ul_size : Buffer size
* dir : The direction of the transfer
* Requires:
* Memory was previously mapped.
*/
extern int proc_end_dma(void *hprocessor, void *pmpu_addr, u32 ul_size,
enum dma_data_direction dir);
/*
* ======== proc_begin_dma ========
* Purpose:
* Begin a DMA transfer
* Parameters:
* hprocessor : The processor handle.
* pmpu_addr : Buffer start address
* ul_size : Buffer size
* dir : The direction of the transfer
* Requires:
* Memory was previously mapped.
*/
extern int proc_begin_dma(void *hprocessor, void *pmpu_addr, u32 ul_size,
enum dma_data_direction dir);
/*
* ======== proc_flush_memory ========
* Purpose:
* Flushes a buffer from the MPU data cache.
* Parameters:
* hprocessor : The processor handle.
* pmpu_addr : Buffer start address
* ul_size : Buffer size
* ul_flags : Reserved.
* Returns:
* 0 : Success.
* -EFAULT : Invalid processor handle.
* -EPERM : General failure.
* Requires:
* PROC Initialized.
* Ensures:
* Details:
* All the arguments are currently ignored.
*/
extern int proc_flush_memory(void *hprocessor,
void *pmpu_addr, u32 ul_size, u32 ul_flags);
/*
* ======== proc_invalidate_memory ========
* Purpose:
* Invalidates a buffer from the MPU data cache.
* Parameters:
* hprocessor : The processor handle.
* pmpu_addr : Buffer start address
* ul_size : Buffer size
* Returns:
* 0 : Success.
* -EFAULT : Invalid processor handle.
* -EPERM : General failure.
* Requires:
* PROC Initialized.
* Ensures:
* Details:
* All the arguments are currently ignored.
*/
extern int proc_invalidate_memory(void *hprocessor,
void *pmpu_addr, u32 ul_size);
/*
* ======== proc_map ========
* Purpose:
* Maps a MPU buffer to DSP address space.
* Parameters:
* hprocessor : The processor handle.
* pmpu_addr : Starting address of the memory region to map.
* ul_size : Size of the memory region to map.
* req_addr : Requested DSP start address. Offset-adjusted actual
* mapped address is in the last argument.
* pp_map_addr : Ptr to DSP side mapped u8 address.
* ul_map_attr : Optional endianness attributes, virt to phys flag.
* Returns:
* 0 : Success.
* -EFAULT : Invalid processor handle.
* -EPERM : General failure.
* -ENOMEM : MPU side memory allocation error.
* -ENOENT : Cannot find a reserved region starting with this
* : address.
* Requires:
* pmpu_addr is not NULL
* ul_size is not zero
* pp_map_addr is not NULL
* PROC Initialized.
* Ensures:
* Details:
*/
extern int proc_map(void *hprocessor,
void *pmpu_addr,
u32 ul_size,
void *req_addr,
void **pp_map_addr, u32 ul_map_attr,
struct process_context *pr_ctxt);
/*
* ======== proc_reserve_memory ========
* Purpose:
* Reserve a virtually contiguous region of DSP address space.
* Parameters:
* hprocessor : The processor handle.
* ul_size : Size of the address space to reserve.
* pp_rsv_addr : Ptr to DSP side reserved u8 address.
* Returns:
* 0 : Success.
* -EFAULT : Invalid processor handle.
* -EPERM : General failure.
* -ENOMEM : Cannot reserve chunk of this size.
* Requires:
* pp_rsv_addr is not NULL
* PROC Initialized.
* Ensures:
* Details:
*/
extern int proc_reserve_memory(void *hprocessor,
u32 ul_size, void **pp_rsv_addr,
struct process_context *pr_ctxt);
/*
* ======== proc_un_map ========
* Purpose:
* Removes a MPU buffer mapping from the DSP address space.
* Parameters:
* hprocessor : The processor handle.
* map_addr : Starting address of the mapped memory region.
* Returns:
* 0 : Success.
* -EFAULT : Invalid processor handle.
* -EPERM : General failure.
* -ENOENT : Cannot find a mapped region starting with this
* : address.
* Requires:
* map_addr is not NULL
* PROC Initialized.
* Ensures:
* Details:
*/
extern int proc_un_map(void *hprocessor, void *map_addr,
struct process_context *pr_ctxt);
/*
* ======== proc_un_reserve_memory ========
* Purpose:
* Frees a previously reserved region of DSP address space.
* Parameters:
* hprocessor : The processor handle.
* prsv_addr : Ptr to DSP side reservedBYTE address.
* Returns:
* 0 : Success.
* -EFAULT : Invalid processor handle.
* -EPERM : General failure.
* -ENOENT : Cannot find a reserved region starting with this
* : address.
* Requires:
* prsv_addr is not NULL
* PROC Initialized.
* Ensures:
* Details:
*/
extern int proc_un_reserve_memory(void *hprocessor,
void *prsv_addr,
struct process_context *pr_ctxt);
#endif /* PROC_ */

25
drivers/staging/tidspbridge/include/dspbridge/procpriv.h
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@ -1,25 +0,0 @@
/*
* procpriv.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Global PROC constants and types, shared by PROC, MGR and DSP API.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef PROCPRIV_
#define PROCPRIV_
/* RM PROC Object */
struct proc_object;
#endif /* PROCPRIV_ */

113
drivers/staging/tidspbridge/include/dspbridge/pwr.h
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@ -1,113 +0,0 @@
/*
* pwr.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef PWR_
#define PWR_
#include <dspbridge/dbdefs.h>
#include <dspbridge/mbx_sh.h>
/* valid sleep command codes that can be sent by GPP via mailbox: */
#define PWR_DEEPSLEEP MBX_PM_DSPIDLE
#define PWR_EMERGENCYDEEPSLEEP MBX_PM_EMERGENCYSLEEP
#define PWR_WAKEUP MBX_PM_DSPWAKEUP
/*
* ======== pwr_sleep_dsp ========
* Signal the DSP to go to sleep.
*
* Parameters:
* sleep_code: New sleep state for DSP. (Initially, valid codes
* are PWR_DEEPSLEEP or PWR_EMERGENCYDEEPSLEEP; both of
* these codes will simply put the DSP in deep sleep.)
*
* timeout: Maximum time (msec) that PWR should wait for
* confirmation that the DSP sleep state has been
* reached. If PWR should simply send the command to
* the DSP to go to sleep and then return (i.e.,
* asynchrounous sleep), the timeout should be
* specified as zero.
*
* Returns:
* 0: Success.
* 0: Success, but the DSP was already asleep.
* -EINVAL: The specified sleep_code is not supported.
* -ETIME: A timeout occurred while waiting for DSP sleep
* confirmation.
* -EPERM: General failure, unable to send sleep command to
* the DSP.
*/
extern int pwr_sleep_dsp(const u32 sleep_code, const u32 timeout);
/*
* ======== pwr_wake_dsp ========
* Signal the DSP to wake from sleep.
*
* Parameters:
* timeout: Maximum time (msec) that PWR should wait for
* confirmation that the DSP is awake. If PWR should
* simply send a command to the DSP to wake and then
* return (i.e., asynchrounous wake), timeout should
* be specified as zero.
*
* Returns:
* 0: Success.
* 0: Success, but the DSP was already awake.
* -ETIME: A timeout occurred while waiting for wake
* confirmation.
* -EPERM: General failure, unable to send wake command to
* the DSP.
*/
extern int pwr_wake_dsp(const u32 timeout);
/*
* ======== pwr_pm_pre_scale ========
* Prescale notification to DSP.
*
* Parameters:
* voltage_domain: The voltage domain for which notification is sent
* level: The level of voltage domain
*
* Returns:
* 0: Success.
* 0: Success, but the DSP was already awake.
* -ETIME: A timeout occurred while waiting for wake
* confirmation.
* -EPERM: General failure, unable to send wake command to
* the DSP.
*/
extern int pwr_pm_pre_scale(u16 voltage_domain, u32 level);
/*
* ======== pwr_pm_post_scale ========
* PostScale notification to DSP.
*
* Parameters:
* voltage_domain: The voltage domain for which notification is sent
* level: The level of voltage domain
*
* Returns:
* 0: Success.
* 0: Success, but the DSP was already awake.
* -ETIME: A timeout occurred while waiting for wake
* confirmation.
* -EPERM: General failure, unable to send wake command to
* the DSP.
*/
extern int pwr_pm_post_scale(u16 voltage_domain, u32 level);
#endif /* PWR_ */

41
drivers/staging/tidspbridge/include/dspbridge/resourcecleanup.h
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@ -1,41 +0,0 @@
/*
* resourcecleanup.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#include <dspbridge/nodepriv.h>
#include <dspbridge/drv.h>
extern int drv_remove_all_dmm_res_elements(void *process_ctxt);
extern int drv_remove_all_node_res_elements(void *process_ctxt);
extern int drv_remove_all_resources(void *process_ctxt);
extern int drv_insert_node_res_element(void *hnode, void *node_resource,
void *process_ctxt);
extern void drv_proc_node_update_heap_status(void *node_resource, s32 status);
extern void drv_proc_node_update_status(void *node_resource, s32 status);
extern int drv_proc_update_strm_res(u32 num_bufs, void *strm_resources);
extern int drv_proc_insert_strm_res_element(void *stream_obj,
void *strm_res,
void *process_ctxt);
extern int drv_remove_all_strm_res_elements(void *process_ctxt);
extern enum node_state node_get_state(void *hnode);

156
drivers/staging/tidspbridge/include/dspbridge/rmm.h
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/*
* rmm.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* This memory manager provides general heap management and arbitrary
* alignment for any number of memory segments, and management of overlay
* memory.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef RMM_
#define RMM_
/*
* ======== rmm_addr ========
* DSP address + segid
*/
struct rmm_addr {
u32 addr;
s32 segid;
};
/*
* ======== rmm_segment ========
* Memory segment on the DSP available for remote allocations.
*/
struct rmm_segment {
u32 base; /* Base of the segment */
u32 length; /* Size of the segment (target MAUs) */
s32 space; /* Code or data */
u32 number; /* Number of Allocated Blocks */
};
/*
* ======== RMM_Target ========
*/
struct rmm_target_obj;
/*
* ======== rmm_alloc ========
*
* rmm_alloc is used to remotely allocate or reserve memory on the DSP.
*
* Parameters:
* target - Target returned from rmm_create().
* segid - Memory segment to allocate from.
* size - Size (target MAUS) to allocate.
* align - alignment.
* dsp_address - If reserve is FALSE, the location to store allocated
* address on output, otherwise, the DSP address to
* reserve.
* reserve - If TRUE, reserve the memory specified by dsp_address.
* Returns:
* 0: Success.
* -ENOMEM: Memory allocation on GPP failed.
* -ENXIO: Cannot "allocate" overlay memory because it's
* already in use.
* Requires:
* RMM initialized.
* Valid target.
* dsp_address != NULL.
* size > 0
* reserve || target->num_segs > 0.
* Ensures:
*/
extern int rmm_alloc(struct rmm_target_obj *target, u32 segid, u32 size,
u32 align, u32 *dsp_address, bool reserve);
/*
* ======== rmm_create ========
* Create a target object with memory segments for remote allocation. If
* seg_tab == NULL or num_segs == 0, memory can only be reserved through
* rmm_alloc().
*
* Parameters:
* target_obj: - Location to store target on output.
* seg_tab: - Table of memory segments.
* num_segs: - Number of memory segments.
* Returns:
* 0: Success.
* -ENOMEM: Memory allocation failed.
* Requires:
* RMM initialized.
* target_obj != NULL.
* num_segs == 0 || seg_tab != NULL.
* Ensures:
* Success: Valid *target_obj.
* Failure: *target_obj == NULL.
*/
extern int rmm_create(struct rmm_target_obj **target_obj,
struct rmm_segment seg_tab[], u32 num_segs);
/*
* ======== rmm_delete ========
* Delete target allocated in rmm_create().
*
* Parameters:
* target - Target returned from rmm_create().
* Returns:
* Requires:
* RMM initialized.
* Valid target.
* Ensures:
*/
extern void rmm_delete(struct rmm_target_obj *target);
/*
* ======== rmm_free ========
* Free or unreserve memory allocated through rmm_alloc().
*
* Parameters:
* target: - Target returned from rmm_create().
* segid: - Segment of memory to free.
* dsp_address: - Address to free or unreserve.
* size: - Size of memory to free or unreserve.
* reserved: - TRUE if memory was reserved only, otherwise FALSE.
* Returns:
* Requires:
* RMM initialized.
* Valid target.
* reserved || segid < target->num_segs.
* reserve || [dsp_address, dsp_address + size] is a valid memory range.
* Ensures:
*/
extern bool rmm_free(struct rmm_target_obj *target, u32 segid, u32 dsp_addr,
u32 size, bool reserved);
/*
* ======== rmm_stat ========
* Obtain memory segment status
*
* Parameters:
* segid: Segment ID of the dynamic loading segment.
* mem_stat_buf: Pointer to allocated buffer into which memory stats are
* placed.
* Returns:
* TRUE: Success.
* FALSE: Failure.
* Requires:
* segid < target->num_segs
* Ensures:
*/
extern bool rmm_stat(struct rmm_target_obj *target, enum dsp_memtype segid,
struct dsp_memstat *mem_stat_buf);
#endif /* RMM_ */

86
drivers/staging/tidspbridge/include/dspbridge/rms_sh.h
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@ -1,86 +0,0 @@
/*
* rms_sh.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* DSP/BIOS Bridge Resource Manager Server shared definitions (used on both
* GPP and DSP sides).
*
* Copyright (C) 2008 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef RMS_SH_
#define RMS_SH_
#include <dspbridge/rmstypes.h>
/* Memory Types: */
#define RMS_CODE 0 /* Program space */
#define RMS_DATA 1 /* Data space */
/* RM Server Command and Response Buffer Sizes: */
#define RMS_COMMANDBUFSIZE 256 /* Size of command buffer */
/* Pre-Defined Command/Response Codes: */
#define RMS_EXIT 0x80000000 /* GPP->Node: shutdown */
#define RMS_EXITACK 0x40000000 /* Node->GPP: ack shutdown */
#define RMS_BUFDESC 0x20000000 /* Arg1 SM buf, Arg2 SM size */
#define RMS_KILLTASK 0x10000000 /* GPP->Node: Kill Task */
/* RM Server RPC Command Structure: */
struct rms_command {
rms_word fxn; /* Server function address */
rms_word arg1; /* First argument */
rms_word arg2; /* Second argument */
rms_word data; /* Function-specific data array */
};
/*
* The rms_strm_def structure defines the parameters for both input and output
* streams, and is passed to a node's create function.
*/
struct rms_strm_def {
rms_word bufsize; /* Buffer size (in DSP words) */
rms_word nbufs; /* Max number of bufs in stream */
rms_word segid; /* Segment to allocate buffers */
rms_word align; /* Alignment for allocated buffers */
rms_word timeout; /* Timeout (msec) for blocking calls */
char name[1]; /* Device Name (terminated by '\0') */
};
/* Message node create args structure: */
struct rms_msg_args {
rms_word max_msgs; /* Max # simultaneous msgs to node */
rms_word segid; /* Mem segment for NODE_allocMsgBuf */
rms_word notify_type; /* Type of message notification */
rms_word arg_length; /* Length (in DSP chars) of arg data */
rms_word arg_data; /* Arg data for node */
};
/* Partial task create args structure */
struct rms_more_task_args {
rms_word priority; /* Task's runtime priority level */
rms_word stack_size; /* Task's stack size */
rms_word sysstack_size; /* Task's system stack size (55x) */
rms_word stack_seg; /* Memory segment for task's stack */
rms_word heap_addr; /* base address of the node memory heap in
* external memory (DSP virtual address) */
rms_word heap_size; /* size in MAUs of the node memory heap in
* external memory */
rms_word misc; /* Misc field. Not used for 'normal'
* task nodes; for xDAIS socket nodes
* specifies the IALG_Fxn pointer.
*/
/* # input STRM definition structures */
rms_word num_input_streams;
};
#endif /* RMS_SH_ */

24
drivers/staging/tidspbridge/include/dspbridge/rmstypes.h
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@ -1,24 +0,0 @@
/*
* rmstypes.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* DSP/BIOS Bridge Resource Manager Server shared data type definitions.
*
* Copyright (C) 2008 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef RMSTYPES_
#define RMSTYPES_
#include <linux/types.h>
typedef u32 rms_word;
#endif /* RMSTYPES_ */

306
drivers/staging/tidspbridge/include/dspbridge/strm.h
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@ -1,306 +0,0 @@
/*
* strm.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* DSPBridge Stream Manager.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef STRM_
#define STRM_
#include <dspbridge/dev.h>
#include <dspbridge/strmdefs.h>
#include <dspbridge/proc.h>
/*
* ======== strm_allocate_buffer ========
* Purpose:
* Allocate data buffer(s) for use with a stream.
* Parameter:
* strmres: Stream resource info handle returned from strm_open().
* usize: Size (GPP bytes) of the buffer(s).
* num_bufs: Number of buffers to allocate.
* ap_buffer: Array to hold buffer addresses.
* Returns:
* 0: Success.
* -EFAULT: Invalid stream_obj.
* -ENOMEM: Insufficient memory.
* -EPERM: Failure occurred, unable to allocate buffers.
* -EINVAL: usize must be > 0 bytes.
* Requires:
* ap_buffer != NULL.
* Ensures:
*/
extern int strm_allocate_buffer(struct strm_res_object *strmres,
u32 usize,
u8 **ap_buffer,
u32 num_bufs,
struct process_context *pr_ctxt);
/*
* ======== strm_close ========
* Purpose:
* Close a stream opened with strm_open().
* Parameter:
* strmres: Stream resource info handle returned from strm_open().
* Returns:
* 0: Success.
* -EFAULT: Invalid stream_obj.
* -EPIPE: Some data buffers issued to the stream have not
* been reclaimed.
* -EPERM: Failure to close stream.
* Requires:
* Ensures:
*/
extern int strm_close(struct strm_res_object *strmres,
struct process_context *pr_ctxt);
/*
* ======== strm_create ========
* Purpose:
* Create a STRM manager object. This object holds information about the
* device needed to open streams.
* Parameters:
* strm_man: Location to store handle to STRM manager object on
* output.
* dev_obj: Device for this processor.
* Returns:
* 0: Success;
* -ENOMEM: Insufficient memory for requested resources.
* -EPERM: General failure.
* Requires:
* strm_man != NULL.
* dev_obj != NULL.
* Ensures:
* 0: Valid *strm_man.
* error: *strm_man == NULL.
*/
extern int strm_create(struct strm_mgr **strm_man,
struct dev_object *dev_obj);
/*
* ======== strm_delete ========
* Purpose:
* Delete the STRM Object.
* Parameters:
* strm_mgr_obj: Handle to STRM manager object from strm_create.
* Returns:
* Requires:
* Valid strm_mgr_obj.
* Ensures:
* strm_mgr_obj is not valid.
*/
extern void strm_delete(struct strm_mgr *strm_mgr_obj);
/*
* ======== strm_free_buffer ========
* Purpose:
* Free buffer(s) allocated with strm_allocate_buffer.
* Parameter:
* strmres: Stream resource info handle returned from strm_open().
* ap_buffer: Array containing buffer addresses.
* num_bufs: Number of buffers to be freed.
* Returns:
* 0: Success.
* -EFAULT: Invalid stream handle.
* -EPERM: Failure occurred, unable to free buffers.
* Requires:
* ap_buffer != NULL.
* Ensures:
*/
extern int strm_free_buffer(struct strm_res_object *strmres,
u8 **ap_buffer, u32 num_bufs,
struct process_context *pr_ctxt);
/*
* ======== strm_get_info ========
* Purpose:
* Get information about a stream. User's dsp_streaminfo is contained
* in stream_info struct. stream_info also contains Bridge private info.
* Parameters:
* stream_obj: Stream handle returned from strm_open().
* stream_info: Location to store stream info on output.
* uSteamInfoSize: Size of user's dsp_streaminfo structure.
* Returns:
* 0: Success.
* -EFAULT: Invalid stream_obj.
* -EINVAL: stream_info_size < sizeof(dsp_streaminfo).
* -EPERM: Unable to get stream info.
* Requires:
* stream_info != NULL.
* Ensures:
*/
extern int strm_get_info(struct strm_object *stream_obj,
struct stream_info *stream_info,
u32 stream_info_size);
/*
* ======== strm_idle ========
* Purpose:
* Idle a stream and optionally flush output data buffers.
* If this is an output stream and flush_data is TRUE, all data currently
* enqueued will be discarded.
* If this is an output stream and flush_data is FALSE, this function
* will block until all currently buffered data is output, or the timeout
* specified has been reached.
* After a successful call to strm_idle(), all buffers can immediately
* be reclaimed.
* Parameters:
* stream_obj: Stream handle returned from strm_open().
* flush_data: If TRUE, discard output buffers.
* Returns:
* 0: Success.
* -EFAULT: Invalid stream_obj.
* -ETIME: A timeout occurred before the stream could be idled.
* -EPERM: Unable to idle stream.
* Requires:
* Ensures:
*/
extern int strm_idle(struct strm_object *stream_obj, bool flush_data);
/*
* ======== strm_issue ========
* Purpose:
* Send a buffer of data to a stream.
* Parameters:
* stream_obj: Stream handle returned from strm_open().
* pbuf: Pointer to buffer of data to be sent to the stream.
* ul_bytes: Number of bytes of data in the buffer.
* ul_buf_size: Actual buffer size in bytes.
* dw_arg: A user argument that travels with the buffer.
* Returns:
* 0: Success.
* -EFAULT: Invalid stream_obj.
* -ENOSR: The stream is full.
* -EPERM: Failure occurred, unable to issue buffer.
* Requires:
* pbuf != NULL.
* Ensures:
*/
extern int strm_issue(struct strm_object *stream_obj, u8 * pbuf,
u32 ul_bytes, u32 ul_buf_size, u32 dw_arg);
/*
* ======== strm_open ========
* Purpose:
* Open a stream for sending/receiving data buffers to/from a task of
* DAIS socket node on the DSP.
* Parameters:
* hnode: Node handle returned from node_allocate().
* dir: DSP_TONODE or DSP_FROMNODE.
* index: Stream index.
* pattr: Pointer to structure containing attributes to be
* applied to stream. Cannot be NULL.
* strmres: Location to store stream resource info handle on output.
* Returns:
* 0: Success.
* -EFAULT: Invalid hnode.
* -EPERM: Invalid direction.
* hnode is not a task or DAIS socket node.
* Unable to open stream.
* -EINVAL: Invalid index.
* Requires:
* strmres != NULL.
* pattr != NULL.
* Ensures:
* 0: *strmres is valid.
* error: *strmres == NULL.
*/
extern int strm_open(struct node_object *hnode, u32 dir,
u32 index, struct strm_attr *pattr,
struct strm_res_object **strmres,
struct process_context *pr_ctxt);
/*
* ======== strm_reclaim ========
* Purpose:
* Request a buffer back from a stream.
* Parameters:
* stream_obj: Stream handle returned from strm_open().
* buf_ptr: Location to store pointer to reclaimed buffer.
* nbytes: Location where number of bytes of data in the
* buffer will be written.
* buff_size: Location where actual buffer size will be written.
* pdw_arg: Location where user argument that travels with
* the buffer will be written.
* Returns:
* 0: Success.
* -EFAULT: Invalid stream_obj.
* -ETIME: A timeout occurred before a buffer could be
* retrieved.
* -EPERM: Failure occurred, unable to reclaim buffer.
* Requires:
* buf_ptr != NULL.
* nbytes != NULL.
* pdw_arg != NULL.
* Ensures:
*/
extern int strm_reclaim(struct strm_object *stream_obj,
u8 **buf_ptr, u32 * nbytes,
u32 *buff_size, u32 *pdw_arg);
/*
* ======== strm_register_notify ========
* Purpose:
* Register to be notified on specific events for this stream.
* Parameters:
* stream_obj: Stream handle returned by strm_open().
* event_mask: Mask of types of events to be notified about.
* notify_type: Type of notification to be sent.
* hnotification: Handle to be used for notification.
* Returns:
* 0: Success.
* -EFAULT: Invalid stream_obj.
* -ENOMEM: Insufficient memory on GPP.
* -EINVAL: event_mask is invalid.
* -ENOSYS: Notification type specified by notify_type is not
* supported.
* Requires:
* hnotification != NULL.
* Ensures:
*/
extern int strm_register_notify(struct strm_object *stream_obj,
u32 event_mask, u32 notify_type,
struct dsp_notification
*hnotification);
/*
* ======== strm_select ========
* Purpose:
* Select a ready stream.
* Parameters:
* strm_tab: Array of stream handles returned from strm_open().
* strms: Number of stream handles in array.
* pmask: Location to store mask of ready streams on output.
* utimeout: Timeout value (milliseconds).
* Returns:
* 0: Success.
* -EDOM: strms out of range.
* -EFAULT: Invalid stream handle in array.
* -ETIME: A timeout occurred before a stream became ready.
* -EPERM: Failure occurred, unable to select a stream.
* Requires:
* strm_tab != NULL.
* strms > 0.
* pmask != NULL.
* Ensures:
* 0: *pmask != 0 || utimeout == 0.
* Error: *pmask == 0.
*/
extern int strm_select(struct strm_object **strm_tab,
u32 strms, u32 *pmask, u32 utimeout);
#endif /* STRM_ */

44
drivers/staging/tidspbridge/include/dspbridge/strmdefs.h
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@ -1,44 +0,0 @@
/*
* strmdefs.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Global STRM constants and types.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef STRMDEFS_
#define STRMDEFS_
struct strm_mgr;
struct strm_object;
struct strm_attr {
void *user_event;
char *str_event_name;
void *virt_base; /* Process virtual base address of
* mapped SM */
u32 virt_size; /* Size of virtual space in bytes */
struct dsp_streamattrin *stream_attr_in;
};
struct stream_info {
enum dsp_strmmode strm_mode; /* transport mode of
* stream(DMA, ZEROCOPY..) */
u32 segment_id; /* Segment strm allocs from. 0 is local mem */
void *virt_base; /* " " Stream'process virt base */
struct dsp_streaminfo *user_strm; /* User's stream information
* returned */
};
#endif /* STRMDEFS_ */

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