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ALSA: hda - Move azx_interrupt to hda_controller
This code will be reused by an hda_platform driver as it has no PCI dependencies. This allows update_rirb to be static as all users are now in hda_controller.c. Signed-off-by: Dylan Reid <dgreid@chromium.org> Signed-off-by: Takashi Iwai <tiwai@suse.de>
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@ -22,6 +22,7 @@
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#include <linux/clocksource.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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@ -1162,7 +1163,7 @@ static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
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#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
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/* retrieve RIRB entry - called from interrupt handler */
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void azx_update_rirb(struct azx *chip)
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static void azx_update_rirb(struct azx *chip)
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{
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unsigned int rp, wp;
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unsigned int addr;
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@ -1205,7 +1206,6 @@ void azx_update_rirb(struct azx *chip)
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}
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}
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}
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EXPORT_SYMBOL_GPL(azx_update_rirb);
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/* receive a response */
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static unsigned int azx_rirb_get_response(struct hda_bus *bus,
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@ -1747,5 +1747,70 @@ void azx_stop_chip(struct azx *chip)
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chip->initialized = 0;
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}
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/*
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* interrupt handler
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*/
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irqreturn_t azx_interrupt(int irq, void *dev_id)
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{
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struct azx *chip = dev_id;
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struct azx_dev *azx_dev;
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u32 status;
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u8 sd_status;
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int i;
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#ifdef CONFIG_PM_RUNTIME
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if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
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if (chip->card->dev->power.runtime_status != RPM_ACTIVE)
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return IRQ_NONE;
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#endif
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spin_lock(&chip->reg_lock);
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if (chip->disabled) {
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spin_unlock(&chip->reg_lock);
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return IRQ_NONE;
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}
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status = azx_readl(chip, INTSTS);
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if (status == 0 || status == 0xffffffff) {
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spin_unlock(&chip->reg_lock);
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return IRQ_NONE;
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}
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for (i = 0; i < chip->num_streams; i++) {
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azx_dev = &chip->azx_dev[i];
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if (status & azx_dev->sd_int_sta_mask) {
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sd_status = azx_sd_readb(chip, azx_dev, SD_STS);
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azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
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if (!azx_dev->substream || !azx_dev->running ||
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!(sd_status & SD_INT_COMPLETE))
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continue;
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/* check whether this IRQ is really acceptable */
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if (!chip->ops->position_check ||
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chip->ops->position_check(chip, azx_dev)) {
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spin_unlock(&chip->reg_lock);
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snd_pcm_period_elapsed(azx_dev->substream);
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spin_lock(&chip->reg_lock);
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}
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}
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}
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/* clear rirb int */
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status = azx_readb(chip, RIRBSTS);
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if (status & RIRB_INT_MASK) {
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if (status & RIRB_INT_RESPONSE) {
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if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
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udelay(80);
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azx_update_rirb(chip);
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}
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azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
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}
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spin_unlock(&chip->reg_lock);
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return IRQ_HANDLED;
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}
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EXPORT_SYMBOL_GPL(azx_interrupt);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Common HDA driver funcitons");
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@ -50,7 +50,6 @@ void azx_free_stream_pages(struct azx *chip);
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/*
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* CORB / RIRB interface
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*/
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void azx_update_rirb(struct azx *chip);
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int azx_send_cmd(struct hda_bus *bus, unsigned int val);
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unsigned int azx_get_response(struct hda_bus *bus,
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unsigned int addr);
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@ -59,5 +58,6 @@ unsigned int azx_get_response(struct hda_bus *bus,
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void azx_init_chip(struct azx *chip, int full_reset);
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void azx_stop_chip(struct azx *chip);
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void azx_enter_link_reset(struct azx *chip);
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irqreturn_t azx_interrupt(int irq, void *dev_id);
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#endif /* __SOUND_HDA_CONTROLLER_H */
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@ -413,7 +413,6 @@ static void azx_init_pci(struct azx *chip)
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}
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}
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static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
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/* called from IRQ */
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@ -433,70 +432,6 @@ static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
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return 0;
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}
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/*
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* interrupt handler
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*/
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static irqreturn_t azx_interrupt(int irq, void *dev_id)
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{
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struct azx *chip = dev_id;
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struct azx_dev *azx_dev;
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u32 status;
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u8 sd_status;
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int i;
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#ifdef CONFIG_PM_RUNTIME
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if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
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if (chip->card->dev->power.runtime_status != RPM_ACTIVE)
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return IRQ_NONE;
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#endif
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spin_lock(&chip->reg_lock);
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if (chip->disabled) {
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spin_unlock(&chip->reg_lock);
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return IRQ_NONE;
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}
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status = azx_readl(chip, INTSTS);
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if (status == 0 || status == 0xffffffff) {
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spin_unlock(&chip->reg_lock);
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return IRQ_NONE;
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}
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for (i = 0; i < chip->num_streams; i++) {
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azx_dev = &chip->azx_dev[i];
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if (status & azx_dev->sd_int_sta_mask) {
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sd_status = azx_sd_readb(chip, azx_dev, SD_STS);
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azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
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if (!azx_dev->substream || !azx_dev->running ||
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!(sd_status & SD_INT_COMPLETE))
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continue;
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/* check whether this IRQ is really acceptable */
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if (!chip->ops->position_check ||
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chip->ops->position_check(chip, azx_dev)) {
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spin_unlock(&chip->reg_lock);
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snd_pcm_period_elapsed(azx_dev->substream);
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spin_lock(&chip->reg_lock);
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}
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}
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}
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/* clear rirb int */
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status = azx_readb(chip, RIRBSTS);
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if (status & RIRB_INT_MASK) {
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if (status & RIRB_INT_RESPONSE) {
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if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
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udelay(80);
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azx_update_rirb(chip);
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}
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azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
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}
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spin_unlock(&chip->reg_lock);
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return IRQ_HANDLED;
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}
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/*
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* Probe the given codec address
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*/
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