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rtw88: coex: 8723d: set antanna control owner

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Without setting antenna control owner, the WiFi could be disconnected if
the BT has traffic. Because the antenna is switched to BT side for its
traffic, and the WiFi will have no chance to transfer data. Set control
owner to prevent WiFi disconnect issue.

Fixes: f5df1a8b43 ("rtw88: 8723d: Add 8723DE to Kconfig and Makefile")
Tested-by: You-Sheng Yang <vicamo.yang@canonical.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20200529025009.2468-2-yhchuang@realtek.com
This commit is contained in:
Ping-Ke Shih 2020-05-29 10:50:07 +08:00 committed by Kalle Valo
parent 53df5271f2
commit efad661168
4 changed files with 17 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/net/wireless/realtek/rtw88/coex.c
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@ -751,10 +751,18 @@ EXPORT_SYMBOL(rtw_coex_write_indirect_reg);
static void rtw_coex_coex_ctrl_owner(struct rtw_dev *rtwdev, bool wifi_control)
{
if (wifi_control)
struct rtw_chip_info *chip = rtwdev->chip;
const struct rtw_hw_reg *btg_reg = chip->btg_reg;
if (wifi_control) {
rtw_write32_set(rtwdev, REG_SYS_SDIO_CTRL, BIT_LTE_MUX_CTRL_PATH);
else
if (btg_reg)
rtw_write8_set(rtwdev, btg_reg->addr, btg_reg->mask);
} else {
rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_LTE_MUX_CTRL_PATH);
if (btg_reg)
rtw_write8_clr(rtwdev, btg_reg->addr, btg_reg->mask);
}
}
static void rtw_coex_set_gnt_bt(struct rtw_dev *rtwdev, u8 state)

1
drivers/net/wireless/realtek/rtw88/main.h
View File

@ -1174,6 +1174,7 @@ struct rtw_chip_info {
const struct coex_rf_para *wl_rf_para_tx;
const struct coex_rf_para *wl_rf_para_rx;
const struct coex_5g_afh_map *afh_5g;
const struct rtw_hw_reg *btg_reg;
const struct rtw_reg_domain *coex_info_hw_regs;
};

5
drivers/net/wireless/realtek/rtw88/rtw8723d.c
View File

@ -2068,6 +2068,10 @@ static const u8 wl_rssi_step_8723d[] = {60, 50, 44, 30};
static const u8 bt_rssi_step_8723d[] = {30, 30, 30, 30};
static const struct coex_5g_afh_map afh_5g_8723d[] = { {0, 0, 0} };
static const struct rtw_hw_reg btg_reg_8723d = {
.addr = REG_BTG_SEL, .mask = BIT_MASK_BTG_WL,
};
/* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
static const struct coex_rf_para rf_para_tx_8723d[] = {
{0, 0, false, 7}, /* for normal */
@ -2734,6 +2738,7 @@ struct rtw_chip_info rtw8723d_hw_spec = {
.bt_afh_span_bw40 = 0x30,
.afh_5g_num = ARRAY_SIZE(afh_5g_8723d),
.afh_5g = afh_5g_8723d,
.btg_reg = &btg_reg_8723d,
.coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8723d),
.coex_info_hw_regs = coex_info_hw_regs_8723d,

1
drivers/net/wireless/realtek/rtw88/rtw8723d.h
View File

@ -145,6 +145,7 @@ static inline s32 iqk_mult(s32 x, s32 y, s32 *ext)
#define REG_GPIO_INTM 0x0048
#define REG_BTG_SEL 0x0067
#define BIT_MASK_BTG_WL BIT(7)
#define REG_LTECOEX_PATH_CONTROL 0x0070
#define REG_LTECOEX_CTRL 0x07c0
#define REG_LTECOEX_WRITE_DATA 0x07c4