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watchdog: Add Aspeed watchdog driver
Provides generic watchdog features as well as reboot support for the Aspeed SoCs. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
This commit is contained in:
Joel Stanley
Wim Van Sebroeck
parent
0c9444cc9e
commit
efa859f7d7
@ -669,6 +669,19 @@ config RENESAS_WDT
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This driver adds watchdog support for the integrated watchdogs in the
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Renesas R-Car and other SH-Mobile SoCs (usually named RWDT or SWDT).
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config ASPEED_WATCHDOG
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tristate "Aspeed 2400 watchdog support"
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depends on ARCH_ASPEED || COMPILE_TEST
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select WATCHDOG_CORE
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help
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Say Y here to include support for the watchdog timer
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in Apseed BMC SoCs.
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This driver is required to reboot the SoC.
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To compile this driver as a module, choose M here: the
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module will be called aspeed_wdt.
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# AVR32 Architecture
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config AT32AP700X_WDT
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@ -74,6 +74,7 @@ obj-$(CONFIG_LPC18XX_WATCHDOG) += lpc18xx_wdt.o
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obj-$(CONFIG_BCM7038_WDT) += bcm7038_wdt.o
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obj-$(CONFIG_ATLAS7_WATCHDOG) += atlas7_wdt.o
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obj-$(CONFIG_RENESAS_WDT) += renesas_wdt.o
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obj-$(CONFIG_ASPEED_WATCHDOG) += aspeed_wdt.o
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# AVR32 Architecture
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obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
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212
drivers/watchdog/aspeed_wdt.c
Normal file
212
drivers/watchdog/aspeed_wdt.c
Normal file
@ -0,0 +1,212 @@
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/*
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* Copyright 2016 IBM Corporation
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*
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* Joel Stanley <joel@jms.id.au>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/watchdog.h>
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struct aspeed_wdt {
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struct watchdog_device wdd;
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void __iomem *base;
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u32 ctrl;
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};
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static const struct of_device_id aspeed_wdt_of_table[] = {
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{ .compatible = "aspeed,ast2400-wdt" },
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{ .compatible = "aspeed,ast2500-wdt" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
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#define WDT_STATUS 0x00
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#define WDT_RELOAD_VALUE 0x04
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#define WDT_RESTART 0x08
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#define WDT_CTRL 0x0C
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#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
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#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
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#define WDT_CTRL_1MHZ_CLK BIT(4)
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#define WDT_CTRL_WDT_EXT BIT(3)
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#define WDT_CTRL_WDT_INTR BIT(2)
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#define WDT_CTRL_RESET_SYSTEM BIT(1)
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#define WDT_CTRL_ENABLE BIT(0)
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#define WDT_RESTART_MAGIC 0x4755
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/* 32 bits at 1MHz, in milliseconds */
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#define WDT_MAX_TIMEOUT_MS 4294967
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#define WDT_DEFAULT_TIMEOUT 30
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#define WDT_RATE_1MHZ 1000000
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static struct aspeed_wdt *to_aspeed_wdt(struct watchdog_device *wdd)
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{
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return container_of(wdd, struct aspeed_wdt, wdd);
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}
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static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count)
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{
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wdt->ctrl |= WDT_CTRL_ENABLE;
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writel(0, wdt->base + WDT_CTRL);
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writel(count, wdt->base + WDT_RELOAD_VALUE);
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writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
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writel(wdt->ctrl, wdt->base + WDT_CTRL);
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}
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static int aspeed_wdt_start(struct watchdog_device *wdd)
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{
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struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
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aspeed_wdt_enable(wdt, wdd->timeout * WDT_RATE_1MHZ);
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return 0;
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}
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static int aspeed_wdt_stop(struct watchdog_device *wdd)
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{
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struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
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wdt->ctrl &= ~WDT_CTRL_ENABLE;
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writel(wdt->ctrl, wdt->base + WDT_CTRL);
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return 0;
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}
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static int aspeed_wdt_ping(struct watchdog_device *wdd)
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{
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struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
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writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
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return 0;
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}
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static int aspeed_wdt_set_timeout(struct watchdog_device *wdd,
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unsigned int timeout)
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{
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struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
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u32 actual;
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wdd->timeout = timeout;
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actual = min(timeout, wdd->max_hw_heartbeat_ms * 1000);
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writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE);
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writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
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return 0;
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}
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static int aspeed_wdt_restart(struct watchdog_device *wdd,
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unsigned long action, void *data)
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{
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struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
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aspeed_wdt_enable(wdt, 128 * WDT_RATE_1MHZ / 1000);
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mdelay(1000);
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return 0;
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}
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static const struct watchdog_ops aspeed_wdt_ops = {
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.start = aspeed_wdt_start,
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.stop = aspeed_wdt_stop,
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.ping = aspeed_wdt_ping,
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.set_timeout = aspeed_wdt_set_timeout,
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.restart = aspeed_wdt_restart,
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.owner = THIS_MODULE,
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};
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static const struct watchdog_info aspeed_wdt_info = {
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.options = WDIOF_KEEPALIVEPING
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| WDIOF_MAGICCLOSE
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| WDIOF_SETTIMEOUT,
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.identity = KBUILD_MODNAME,
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};
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static int aspeed_wdt_remove(struct platform_device *pdev)
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{
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struct aspeed_wdt *wdt = platform_get_drvdata(pdev);
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watchdog_unregister_device(&wdt->wdd);
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return 0;
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}
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static int aspeed_wdt_probe(struct platform_device *pdev)
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{
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struct aspeed_wdt *wdt;
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struct resource *res;
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int ret;
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wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
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if (!wdt)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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wdt->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(wdt->base))
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return PTR_ERR(wdt->base);
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/*
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* The ast2400 wdt can run at PCLK, or 1MHz. The ast2500 only
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* runs at 1MHz. We chose to always run at 1MHz, as there's no
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* good reason to have a faster watchdog counter.
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*/
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wdt->wdd.info = &aspeed_wdt_info;
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wdt->wdd.ops = &aspeed_wdt_ops;
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wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS;
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wdt->wdd.parent = &pdev->dev;
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wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT;
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watchdog_init_timeout(&wdt->wdd, 0, &pdev->dev);
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/*
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* Control reset on a per-device basis to ensure the
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* host is not affected by a BMC reboot, so only reset
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* the SOC and not the full chip
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*/
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wdt->ctrl = WDT_CTRL_RESET_MODE_SOC |
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WDT_CTRL_1MHZ_CLK |
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WDT_CTRL_RESET_SYSTEM;
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if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) {
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aspeed_wdt_start(&wdt->wdd);
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set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
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}
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ret = watchdog_register_device(&wdt->wdd);
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if (ret) {
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dev_err(&pdev->dev, "failed to register\n");
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return ret;
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}
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platform_set_drvdata(pdev, wdt);
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return 0;
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}
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static struct platform_driver aspeed_watchdog_driver = {
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.probe = aspeed_wdt_probe,
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.remove = aspeed_wdt_remove,
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.driver = {
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.name = KBUILD_MODNAME,
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.of_match_table = of_match_ptr(aspeed_wdt_of_table),
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},
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};
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module_platform_driver(aspeed_watchdog_driver);
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MODULE_DESCRIPTION("Aspeed Watchdog Driver");
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MODULE_LICENSE("GPL");
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