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irqchip/renesas-rzg2l: Implement restriction when writing ISCR register

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The RZ/G2L manual (chapter "IRQ Status Control Register (ISCR)") describes
the operation to clear interrupts through the ISCR register as follows:

[Write operation]

  When "Falling-edge detection", "Rising-edge detection" or
  "Falling/Rising-edge detection" is set in IITSR:

    - In case ISTAT is 1
	0: IRQn interrupt detection status is cleared.
	1: Invalid to write.
    - In case ISTAT is 0
	Invalid to write.

  When "Low-level detection" is set in IITSR.:
        Invalid to write.

Take the interrupt type into account when clearing interrupts through the
ISCR register to avoid writing the ISCR when the interrupt type is level.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231120111820.87398-6-claudiu.beznea.uj@bp.renesas.com
This commit is contained in:
Claudiu Beznea 2023-11-20 13:18:16 +02:00 committed by Thomas Gleixner
parent b94f455372
commit ef88eefb1a
1 changed files with 10 additions and 4 deletions
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14
drivers/irqchip/irq-renesas-rzg2l.c
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@ -78,11 +78,17 @@ static void rzg2l_irq_eoi(struct irq_data *d)
unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START;
struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
u32 bit = BIT(hw_irq);
u32 reg;
u32 iitsr, iscr;
reg = readl_relaxed(priv->base + ISCR);
if (reg & bit)
writel_relaxed(reg & ~bit, priv->base + ISCR);
iscr = readl_relaxed(priv->base + ISCR);
iitsr = readl_relaxed(priv->base + IITSR);
/*
* ISCR can only be cleared if the type is falling-edge, rising-edge or
* falling/rising-edge.
*/
if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq)))
writel_relaxed(iscr & ~bit, priv->base + ISCR);
}
static void rzg2l_tint_eoi(struct irq_data *d)