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ARM: realview: set up cache correctly on the PB11MPCore

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The L2 cache comes up in a "safe mode" on the PB11MPCore, as
it has several issues. This sets it up properly with the right
size and associativity, also requiring the outer sync to be
disabled for the machine to boot properly.

Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Linus Walleij 2015-12-30 21:05:09 +01:00 committed by Arnd Bergmann
parent f0dba77620
commit ef2a270592
1 changed files with 13 additions and 0 deletions
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13
arch/arm/boot/dts/arm-realview-pb11mp.dts
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@ -99,6 +99,19 @@
<0 31 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-level = <2>;
/*
* Override default cache size, sets and
* associativity as these may be erroneously set
* up by boot loader(s), probably for safety
* since th outer sync operation can cause the
* cache to hang unless disabled.
*/
cache-size = <1048576>; // 1MB
cache-sets = <4096>;
cache-line-size = <32>;
arm,shared-override;
arm,parity-enable;
arm,outer-sync-disable;
};
scu@1f000000 {