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drm/i915/gt: Limit VFE threads based on GT
MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the
range [0, n-1] where n is #EU * (#threads/EU) with the number of threads
based on plaform and the number of EU based on the number of slices and
subslices. This is a fixed number per platform/gt, so appropriately
limit the number of threads we spawn to match the device.
v2: Oversaturate the system with tasks to force execution on every HW
thread; if the thread idles it is returned to the pool and may be reused
again before an unused thread.
v3: Fix more state commands, which was causing Baytrail to barf.
v4: STATE_CACHE_INVALIDATE requires a stall on Ivybridge
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024
Fixes: 47f8253d2b ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Cc: Jon Bloomfield <jon.bloomfield@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Randy Wright <rwright@hpe.com>
Cc: stable@vger.kernel.org # v5.7+
Reviewed-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210111225220.3483-1-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
parent
cd7a214f6b
commit
eebfb32e26
@ -7,8 +7,6 @@
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#include "i915_drv.h"
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#include "intel_gpu_commands.h"
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#define MAX_URB_ENTRIES 64
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#define STATE_SIZE (4 * 1024)
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#define GT3_INLINE_DATA_DELAYS 0x1E00
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#define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))
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@ -34,38 +32,59 @@ struct batch_chunk {
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};
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struct batch_vals {
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u32 max_primitives;
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u32 max_urb_entries;
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u32 cmd_size;
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u32 state_size;
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u32 max_threads;
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u32 state_start;
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u32 batch_size;
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u32 surface_start;
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u32 surface_height;
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u32 surface_width;
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u32 scratch_size;
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u32 max_size;
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u32 size;
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};
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static inline int num_primitives(const struct batch_vals *bv)
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{
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/*
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* We need to saturate the GPU with work in order to dispatch
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* a shader on every HW thread, and clear the thread-local registers.
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* In short, we have to dispatch work faster than the shaders can
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* run in order to fill the EU and occupy each HW thread.
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*/
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return bv->max_threads;
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}
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static void
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batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv)
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{
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if (IS_HASWELL(i915)) {
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bv->max_primitives = 280;
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bv->max_urb_entries = MAX_URB_ENTRIES;
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switch (INTEL_INFO(i915)->gt) {
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default:
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case 1:
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bv->max_threads = 70;
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break;
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case 2:
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bv->max_threads = 140;
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break;
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case 3:
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bv->max_threads = 280;
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break;
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}
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bv->surface_height = 16 * 16;
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bv->surface_width = 32 * 2 * 16;
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} else {
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bv->max_primitives = 128;
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bv->max_urb_entries = MAX_URB_ENTRIES / 2;
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switch (INTEL_INFO(i915)->gt) {
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default:
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case 1: /* including vlv */
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bv->max_threads = 36;
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break;
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case 2:
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bv->max_threads = 128;
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break;
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}
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bv->surface_height = 16 * 8;
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bv->surface_width = 32 * 16;
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}
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bv->cmd_size = bv->max_primitives * 4096;
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bv->state_size = STATE_SIZE;
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bv->state_start = bv->cmd_size;
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bv->batch_size = bv->cmd_size + bv->state_size;
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bv->scratch_size = bv->surface_height * bv->surface_width;
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bv->max_size = bv->batch_size + bv->scratch_size;
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bv->state_start = round_up(SZ_1K + num_primitives(bv) * 64, SZ_4K);
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bv->surface_start = bv->state_start + SZ_4K;
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bv->size = bv->surface_start + bv->surface_height * bv->surface_width;
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}
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static void batch_init(struct batch_chunk *bc,
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@ -155,7 +174,8 @@ static u32
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gen7_fill_binding_table(struct batch_chunk *state,
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const struct batch_vals *bv)
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{
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u32 surface_start = gen7_fill_surface_state(state, bv->batch_size, bv);
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u32 surface_start =
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gen7_fill_surface_state(state, bv->surface_start, bv);
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u32 *cs = batch_alloc_items(state, 32, 8);
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u32 offset = batch_offset(state, cs);
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@ -214,9 +234,9 @@ static void
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gen7_emit_state_base_address(struct batch_chunk *batch,
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u32 surface_state_base)
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{
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u32 *cs = batch_alloc_items(batch, 0, 12);
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u32 *cs = batch_alloc_items(batch, 0, 10);
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*cs++ = STATE_BASE_ADDRESS | (12 - 2);
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*cs++ = STATE_BASE_ADDRESS | (10 - 2);
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/* general */
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*cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY;
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/* surface */
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@ -233,8 +253,6 @@ gen7_emit_state_base_address(struct batch_chunk *batch,
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*cs++ = BASE_ADDRESS_MODIFY;
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*cs++ = 0;
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*cs++ = BASE_ADDRESS_MODIFY;
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*cs++ = 0;
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*cs++ = 0;
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batch_advance(batch, cs);
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}
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@ -244,8 +262,7 @@ gen7_emit_vfe_state(struct batch_chunk *batch,
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u32 urb_size, u32 curbe_size,
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u32 mode)
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{
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u32 urb_entries = bv->max_urb_entries;
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u32 threads = bv->max_primitives - 1;
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u32 threads = bv->max_threads - 1;
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u32 *cs = batch_alloc_items(batch, 32, 8);
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*cs++ = MEDIA_VFE_STATE | (8 - 2);
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@ -254,7 +271,7 @@ gen7_emit_vfe_state(struct batch_chunk *batch,
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*cs++ = 0;
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/* number of threads & urb entries for GPGPU vs Media Mode */
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*cs++ = threads << 16 | urb_entries << 8 | mode << 2;
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*cs++ = threads << 16 | 1 << 8 | mode << 2;
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*cs++ = 0;
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@ -293,17 +310,12 @@ gen7_emit_media_object(struct batch_chunk *batch,
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{
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unsigned int x_offset = (media_object_index % 16) * 64;
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unsigned int y_offset = (media_object_index / 16) * 16;
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unsigned int inline_data_size;
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unsigned int media_batch_size;
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unsigned int i;
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unsigned int pkt = 6 + 3;
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u32 *cs;
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inline_data_size = 112 * 8;
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media_batch_size = inline_data_size + 6;
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cs = batch_alloc_items(batch, 8, pkt);
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cs = batch_alloc_items(batch, 8, media_batch_size);
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*cs++ = MEDIA_OBJECT | (media_batch_size - 2);
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*cs++ = MEDIA_OBJECT | (pkt - 2);
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/* interface descriptor offset */
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*cs++ = 0;
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@ -317,25 +329,44 @@ gen7_emit_media_object(struct batch_chunk *batch,
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*cs++ = 0;
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/* inline */
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*cs++ = (y_offset << 16) | (x_offset);
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*cs++ = y_offset << 16 | x_offset;
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*cs++ = 0;
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*cs++ = GT3_INLINE_DATA_DELAYS;
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for (i = 3; i < inline_data_size; i++)
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*cs++ = 0;
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batch_advance(batch, cs);
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}
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static void gen7_emit_pipeline_flush(struct batch_chunk *batch)
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{
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u32 *cs = batch_alloc_items(batch, 0, 5);
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u32 *cs = batch_alloc_items(batch, 0, 4);
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*cs++ = GFX_OP_PIPE_CONTROL(5);
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*cs++ = PIPE_CONTROL_STATE_CACHE_INVALIDATE |
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PIPE_CONTROL_GLOBAL_GTT_IVB;
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*cs++ = GFX_OP_PIPE_CONTROL(4);
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*cs++ = PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
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PIPE_CONTROL_DEPTH_CACHE_FLUSH |
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PIPE_CONTROL_DC_FLUSH_ENABLE |
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PIPE_CONTROL_CS_STALL;
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*cs++ = 0;
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*cs++ = 0;
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batch_advance(batch, cs);
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}
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static void gen7_emit_pipeline_invalidate(struct batch_chunk *batch)
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{
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u32 *cs = batch_alloc_items(batch, 0, 8);
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/* ivb: Stall before STATE_CACHE_INVALIDATE */
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*cs++ = GFX_OP_PIPE_CONTROL(4);
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*cs++ = PIPE_CONTROL_STALL_AT_SCOREBOARD |
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PIPE_CONTROL_CS_STALL;
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*cs++ = 0;
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*cs++ = 0;
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*cs++ = GFX_OP_PIPE_CONTROL(4);
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*cs++ = PIPE_CONTROL_STATE_CACHE_INVALIDATE;
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*cs++ = 0;
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*cs++ = 0;
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batch_advance(batch, cs);
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}
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@ -344,34 +375,34 @@ static void emit_batch(struct i915_vma * const vma,
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const struct batch_vals *bv)
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{
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struct drm_i915_private *i915 = vma->vm->i915;
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unsigned int desc_count = 64;
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const u32 urb_size = 112;
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const unsigned int desc_count = 1;
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const unsigned int urb_size = 1;
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struct batch_chunk cmds, state;
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u32 interface_descriptor;
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u32 descriptors;
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unsigned int i;
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batch_init(&cmds, vma, start, 0, bv->cmd_size);
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batch_init(&state, vma, start, bv->state_start, bv->state_size);
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batch_init(&cmds, vma, start, 0, bv->state_start);
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batch_init(&state, vma, start, bv->state_start, SZ_4K);
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interface_descriptor =
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gen7_fill_interface_descriptor(&state, bv,
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IS_HASWELL(i915) ?
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&cb_kernel_hsw :
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&cb_kernel_ivb,
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desc_count);
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gen7_emit_pipeline_flush(&cmds);
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descriptors = gen7_fill_interface_descriptor(&state, bv,
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IS_HASWELL(i915) ?
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&cb_kernel_hsw :
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&cb_kernel_ivb,
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desc_count);
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gen7_emit_pipeline_invalidate(&cmds);
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batch_add(&cmds, PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
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batch_add(&cmds, MI_NOOP);
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gen7_emit_state_base_address(&cmds, interface_descriptor);
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gen7_emit_pipeline_invalidate(&cmds);
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gen7_emit_pipeline_flush(&cmds);
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gen7_emit_state_base_address(&cmds, descriptors);
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gen7_emit_pipeline_invalidate(&cmds);
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gen7_emit_vfe_state(&cmds, bv, urb_size - 1, 0, 0);
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gen7_emit_interface_descriptor_load(&cmds, descriptors, desc_count);
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gen7_emit_interface_descriptor_load(&cmds,
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interface_descriptor,
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desc_count);
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for (i = 0; i < bv->max_primitives; i++)
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for (i = 0; i < num_primitives(bv); i++)
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gen7_emit_media_object(&cmds, i);
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batch_add(&cmds, MI_BATCH_BUFFER_END);
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@ -385,15 +416,15 @@ int gen7_setup_clear_gpr_bb(struct intel_engine_cs * const engine,
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batch_get_defaults(engine->i915, &bv);
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if (!vma)
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return bv.max_size;
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return bv.size;
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GEM_BUG_ON(vma->obj->base.size < bv.max_size);
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GEM_BUG_ON(vma->obj->base.size < bv.size);
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batch = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
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if (IS_ERR(batch))
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return PTR_ERR(batch);
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emit_batch(vma, memset(batch, 0, bv.max_size), &bv);
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emit_batch(vma, memset(batch, 0, bv.size), &bv);
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i915_gem_object_flush_map(vma->obj);
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__i915_gem_object_release_map(vma->obj);
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