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drm/nv50/pm: introduce hwsq-based memory reclocking
More work needs to be done on supporting the different memory types. v2 (Ben Skeggs): - fixed up conflicts from not having pausing patch first - restructured code somewhat to fit with how all the other code works - fixed bug where incorrect mpll_ctrl could get set sometimes - removed stuff that's cargo-culted from the binary driver - merged nv92+ display disable into hwsq - fixed incorrect opcode 0x5f magic at end of ucode Signed-off-by: Martin Peres <martin.peres@ensi-bourges.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Martin Peres
Ben Skeggs
parent
abbd3f8e3b
commit
eeb7a50bdd
98
drivers/gpu/drm/nouveau/nouveau_hwsq.h
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98
drivers/gpu/drm/nouveau/nouveau_hwsq.h
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@ -0,0 +1,98 @@
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/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#ifndef __NOUVEAU_HWSQ_H__
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#define __NOUVEAU_HWSQ_H__
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struct hwsq_ucode {
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u8 data[0x200];
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union {
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u8 *u08;
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u16 *u16;
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u32 *u32;
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} ptr;
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u16 len;
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u32 reg;
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u32 val;
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};
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static inline void
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hwsq_init(struct hwsq_ucode *hwsq)
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{
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hwsq->ptr.u08 = hwsq->data;
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hwsq->reg = 0xffffffff;
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hwsq->val = 0xffffffff;
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}
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static inline void
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hwsq_fini(struct hwsq_ucode *hwsq)
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{
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do {
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*hwsq->ptr.u08++ = 0x7f;
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hwsq->len = hwsq->ptr.u08 - hwsq->data;
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} while (hwsq->len & 3);
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hwsq->ptr.u08 = hwsq->data;
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}
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static inline void
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hwsq_unkn(struct hwsq_ucode *hwsq, u8 v0)
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{
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*hwsq->ptr.u08++ = v0;
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}
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static inline void
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hwsq_op5f(struct hwsq_ucode *hwsq, u8 v0, u8 v1)
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{
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*hwsq->ptr.u08++ = 0x5f;
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*hwsq->ptr.u08++ = v0;
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*hwsq->ptr.u08++ = v1;
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}
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static inline void
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hwsq_wr32(struct hwsq_ucode *hwsq, u32 reg, u32 val)
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{
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if (val != hwsq->val) {
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if ((val & 0xffff0000) == (hwsq->val & 0xffff0000)) {
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*hwsq->ptr.u08++ = 0x42;
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*hwsq->ptr.u16++ = (val & 0x0000ffff);
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} else {
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*hwsq->ptr.u08++ = 0xe2;
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*hwsq->ptr.u32++ = val;
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}
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hwsq->val = val;
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}
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if ((reg & 0xffff0000) == (hwsq->reg & 0xffff0000)) {
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*hwsq->ptr.u08++ = 0x40;
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*hwsq->ptr.u16++ = (reg & 0x0000ffff);
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} else {
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*hwsq->ptr.u08++ = 0xe0;
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*hwsq->ptr.u32++ = reg;
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}
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hwsq->reg = reg;
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}
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#endif
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@ -27,6 +27,7 @@
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#include "nouveau_bios.h"
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#include "nouveau_hw.h"
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#include "nouveau_pm.h"
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#include "nouveau_hwsq.h"
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enum clk_src {
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clk_src_crystal,
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@ -351,6 +352,9 @@ nv50_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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}
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struct nv50_pm_state {
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struct hwsq_ucode mclk_hwsq;
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u32 mscript;
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u32 emast;
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u32 nctrl;
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u32 ncoef;
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@ -359,10 +363,6 @@ struct nv50_pm_state {
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u32 amast;
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u32 pdivs;
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u32 mscript;
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u32 mctrl;
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u32 mcoef;
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};
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static u32
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@ -415,6 +415,80 @@ clk_same(u32 a, u32 b)
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return ((a / 1000) == (b / 1000));
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}
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static int
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calc_mclk(struct drm_device *dev, u32 freq, struct hwsq_ucode *hwsq)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct pll_lims pll;
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u32 mast = nv_rd32(dev, 0x00c040);
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u32 ctrl = nv_rd32(dev, 0x004008);
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u32 coef = nv_rd32(dev, 0x00400c);
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u32 orig = ctrl;
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u32 crtc_mask = 0;
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int N, M, P;
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int ret, i;
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/* use pcie refclock if possible, otherwise use mpll */
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ctrl &= ~0x81ff0200;
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if (clk_same(freq, read_clk(dev, clk_src_href))) {
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ctrl |= 0x00000200 | (pll.log2p_bias << 19);
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} else {
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ret = calc_pll(dev, 0x4008, &pll, freq, &N, &M, &P);
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if (ret == 0)
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return -EINVAL;
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ctrl |= 0x80000000 | (P << 22) | (P << 16);
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ctrl |= pll.log2p_bias << 19;
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coef = (N << 8) | M;
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}
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mast &= ~0xc0000000; /* get MCLK_2 from HREF */
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mast |= 0x0000c000; /* use MCLK_2 as MPLL_BYPASS clock */
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/* determine active crtcs */
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for (i = 0; i < 2; i++) {
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if (nv_rd32(dev, NV50_PDISPLAY_CRTC_C(i, CLOCK)))
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crtc_mask |= (1 << i);
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}
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/* build the ucode which will reclock the memory for us */
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hwsq_init(hwsq);
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if (crtc_mask) {
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hwsq_op5f(hwsq, crtc_mask, 0x00); /* wait for scanout */
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hwsq_op5f(hwsq, crtc_mask, 0x01); /* wait for vblank */
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}
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if (dev_priv->chipset >= 0x92)
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hwsq_wr32(hwsq, 0x611200, 0x00003300); /* disable scanout */
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hwsq_unkn(hwsq, 0xb0); /* disable bus access */
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hwsq_op5f(hwsq, 0x00, 0x01); /* no idea :s */
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/* prepare memory controller */
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hwsq_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge banks and idle */
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hwsq_wr32(hwsq, 0x1002d0, 0x00000001); /* force refresh */
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hwsq_wr32(hwsq, 0x100210, 0x00000000); /* stop the automatic refresh */
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hwsq_wr32(hwsq, 0x1002dc, 0x00000001); /* start self refresh mode */
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/* reclock memory */
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hwsq_wr32(hwsq, 0xc040, mast);
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hwsq_wr32(hwsq, 0x4008, orig | 0x00000200); /* bypass MPLL */
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hwsq_wr32(hwsq, 0x400c, coef);
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hwsq_wr32(hwsq, 0x4008, ctrl);
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/* restart memory controller */
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hwsq_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge banks and idle */
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hwsq_wr32(hwsq, 0x1002dc, 0x00000000); /* stop self refresh mode */
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hwsq_wr32(hwsq, 0x100210, 0x80000000); /* restart automatic refresh */
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hwsq_unkn(hwsq, 0x07); /* wait for the PLL to stabilize (12us) */
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hwsq_unkn(hwsq, 0x0b); /* may be unnecessary: causes flickering */
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hwsq_unkn(hwsq, 0xd0); /* enable bus access again */
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hwsq_op5f(hwsq, 0x00, 0x00); /* no idea, reverse of 0x00, 0x01? */
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if (dev_priv->chipset >= 0x92)
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hwsq_wr32(hwsq, 0x611200, 0x00003330); /* enable scanout */
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hwsq_fini(hwsq);
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return 0;
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}
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void *
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nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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{
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@ -462,23 +536,16 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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info->scoef = (N << 8) | M;
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}
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/* memory: use pcie refclock if possible, otherwise use mpll */
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info->mscript = perflvl->memscript;
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if (clk_same(perflvl->memory, read_clk(dev, clk_src_href))) {
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info->mctrl = 0x00000200 | (pll.log2p_bias << 19);
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info->mcoef = nv_rd32(dev, 0x400c);
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} else
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/* memory: build hwsq ucode which we'll use to reclock memory */
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info->mclk_hwsq.len = 0;
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if (perflvl->memory) {
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clk = calc_pll(dev, 0x4008, &pll, perflvl->memory,
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&N, &M, &P1);
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if (clk == 0)
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clk = calc_mclk(dev, perflvl->memory, &info->mclk_hwsq);
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if (clk < 0) {
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ret = clk;
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goto error;
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}
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info->mctrl = 0x80000000 | (P1 << 22) | (P1 << 16);
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info->mctrl |= pll.log2p_bias << 19;
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info->mcoef = (N << 8) | M;
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} else {
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info->mctrl = 0x00000000;
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info->mscript = perflvl->memscript;
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}
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/* vdec: avoid modifying xpll until we know exactly how the other
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@ -537,6 +604,44 @@ error:
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return ERR_PTR(ret);
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}
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static int
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prog_mclk(struct drm_device *dev, struct hwsq_ucode *hwsq)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 hwsq_data, hwsq_kick;
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int i;
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if (dev_priv->chipset < 0x90) {
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hwsq_data = 0x001400;
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hwsq_kick = 0x00000003;
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} else {
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hwsq_data = 0x080000;
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hwsq_kick = 0x00000001;
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}
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/* upload hwsq ucode */
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nv_mask(dev, 0x001098, 0x00000008, 0x00000000);
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nv_wr32(dev, 0x001304, 0x00000000);
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for (i = 0; i < hwsq->len / 4; i++)
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nv_wr32(dev, hwsq_data + (i * 4), hwsq->ptr.u32[i]);
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nv_mask(dev, 0x001098, 0x00000018, 0x00000018);
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/* launch, and wait for completion */
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nv_wr32(dev, 0x00130c, hwsq_kick);
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if (!nv_wait(dev, 0x001308, 0x00000100, 0x00000000)) {
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NV_ERROR(dev, "hwsq ucode exec timed out\n");
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NV_ERROR(dev, "0x001308: 0x%08x\n", nv_rd32(dev, 0x001308));
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for (i = 0; i < hwsq->len / 4; i++) {
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NV_ERROR(dev, "0x%06x: 0x%08x\n", 0x1400 + (i * 4),
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nv_rd32(dev, 0x001400 + (i * 4)));
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}
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return -EIO;
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}
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return 0;
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}
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int
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nv50_pm_clocks_set(struct drm_device *dev, void *data)
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{
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@ -550,6 +655,28 @@ nv50_pm_clocks_set(struct drm_device *dev, void *data)
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if (!nv_wait(dev, 0x002504, 0x00000010, 0x00000010))
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goto error;
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/* memory: it is *very* important we change this first, the ucode
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* we build in pre() now has hardcoded 0xc040 values, which can't
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* change before we execute it or the engine clocks may end up
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* messed up.
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*/
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if (info->mclk_hwsq.len) {
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/* execute some scripts that do ??? from the vbios.. */
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if (!bit_table(dev, 'M', &M) && M.version == 1) {
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if (M.length >= 6)
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nouveau_bios_init_exec(dev, ROM16(M.data[5]));
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if (M.length >= 8)
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nouveau_bios_init_exec(dev, ROM16(M.data[7]));
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if (M.length >= 10)
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nouveau_bios_init_exec(dev, ROM16(M.data[9]));
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nouveau_bios_init_exec(dev, info->mscript);
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}
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ret = prog_mclk(dev, &info->mclk_hwsq);
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if (ret)
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goto resume;
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}
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/* reclock vdec/dom6 */
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nv_mask(dev, 0x00c040, 0x00000c00, 0x00000000);
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switch (dev_priv->chipset) {
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@ -578,50 +705,6 @@ nv50_pm_clocks_set(struct drm_device *dev, void *data)
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nv_wr32(dev, 0x00402c, info->ncoef);
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nv_mask(dev, 0x00c040, 0x00100033, info->emast);
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/* memory */
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if (!info->mctrl)
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goto resume;
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/* execute some scripts that do ??? from the vbios.. */
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if (!bit_table(dev, 'M', &M) && M.version == 1) {
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if (M.length >= 6)
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nouveau_bios_init_exec(dev, ROM16(M.data[5]));
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if (M.length >= 8)
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nouveau_bios_init_exec(dev, ROM16(M.data[7]));
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if (M.length >= 10)
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nouveau_bios_init_exec(dev, ROM16(M.data[9]));
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nouveau_bios_init_exec(dev, info->mscript);
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}
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/* disable display */
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if (dev_priv->chipset >= 0x92) {
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nv_wr32(dev, 0x611200, 0x00003300);
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udelay(100);
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}
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/* prepare ram for reclocking */
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nv_wr32(dev, 0x1002d4, 0x00000001); /* precharge */
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nv_wr32(dev, 0x1002d0, 0x00000001); /* refresh */
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nv_wr32(dev, 0x1002d0, 0x00000001); /* refresh */
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nv_mask(dev, 0x100210, 0x80000000, 0x00000000); /* no auto-refresh */
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nv_wr32(dev, 0x1002dc, 0x00000001); /* enable self-refresh */
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/* modify mpll */
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nv_mask(dev, 0x00c040, 0x0000c000, 0x0000c000);
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nv_mask(dev, 0x004008, 0x01ff0200, 0x00000200 | info->mctrl);
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nv_wr32(dev, 0x00400c, info->mcoef);
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udelay(100);
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nv_mask(dev, 0x004008, 0x81ff0200, info->mctrl);
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/* re-enable normal operation of memory controller */
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nv_wr32(dev, 0x1002dc, 0x00000000);
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nv_mask(dev, 0x100210, 0x80000000, 0x80000000);
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udelay(100);
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/* re-enable display */
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if (dev_priv->chipset >= 0x92)
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nv_wr32(dev, 0x611200, 0x00003330);
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goto resume;
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error:
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ret = -EBUSY;
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