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RISC-V Devicetrees for v6.9
Microchip: Missing bus clocks for the CAN controllers spotted during the creation of a driver for the controllers and a specific compatible for the SiFive PDMA block on PolarFire SoC. Starfive: PWM nodes for the jh7100 and jh7110. Camera subsystem support for the latter. Most notably however is the addition of ethernet support for the jh7110 which finally allows people to use the network on the OG VisionFive and on the Beagle-V Starlight board. This was made possible by the non-standard cache management operations support added for the RZ/Five which could be extended to the ccache present on the jh7100. bindings: Additional clarification for what the reg property represents for cpus and two opencores PWM binding changes - the original addition and an added compatible. The latter is here as the driver patch was not ready but the PWM maintainer told me to go ahead and merge it. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZed3VgAKCRB4tDGHoIJi 0rfBAP9n6/i9bitGfqZHXKc1CpqwIWb8sw28OC4u6UWaNEzSmQEA0R0bagMcfVDi szpu4+58Bk4hbd/6lOwacdskEUp0bwU= =gBjh -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmXoD90ACgkQYKtH/8kJ Uicd9hAAny3U0DB36GMakjIJJkBMSrrbIydydt9mSdkOjsgAt6qUUpBahbMjGE3+ U688dtHOMlsZ0ZubVngN+xYtI6xOXP9SU0+P3u/reCQ8SSZnbtndtwmRFd8ZHJFT Nx5MSl71SzzSL7E3vT638VlZvcq0a5fcUKPZql40iLUnY0iJ6IdcU8cZLWoqkOZF R2zhCUGzLuRrAZF9nPgAKGHwPskq1gqWMMCnLf6NIgaxfjf8POuGAgJBVJ1CYg0P kSzXUrEphjD+IpCbffkGJ1epq1+SbYfYo6P9MisiWbv8/xvoZ+VJnbTb+NLg3Wuo i8B5uFOBi65rLCCErDDYNr2huESHHC8IN9ndvRG/eXTaLek4WhJ1cxXDPHBzN9OF DMKKgSeRZnMj/EQ0jQQPK0I9KymVdy+qwAhAr0DKEzGSiiu1hVlxfvspq+EzW9DR O9v2+hRCALpripRGf7wVG+16HtzvbbH1hHGABb4YTl3rf0bSqXTt84wIQ9MBSe+e nFsCnOdA5zNBN3gtiKlbYQE/jiTYCeyqfCJOwXlw83KKSGJfNG+mTOR/vhpVOAbq Djb6dEemeYxZ95P5PFSqm7GOttZWI3vthyWpPeF1qfGuZ6g55+zZyZHsVKevkWzd 54Z/rpLdUBeDRkwNLa9W0r/5oZOLNccKhkS9Qy6umjSsBXa14qA= =0UyT -----END PGP SIGNATURE----- Merge tag 'riscv-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/late RISC-V Devicetrees for v6.9 Microchip: Missing bus clocks for the CAN controllers spotted during the creation of a driver for the controllers and a specific compatible for the SiFive PDMA block on PolarFire SoC. Starfive: PWM nodes for the jh7100 and jh7110. Camera subsystem support for the latter. Most notably however is the addition of ethernet support for the jh7110 which finally allows people to use the network on the OG VisionFive and on the Beagle-V Starlight board. This was made possible by the non-standard cache management operations support added for the RZ/Five which could be extended to the ccache present on the jh7100. bindings: Additional clarification for what the reg property represents for cpus and two opencores PWM binding changes - the original addition and an added compatible. The latter is here as the driver patch was not ready but the PWM maintainer told me to go ahead and merge it. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: jh7110: Add camera subsystem nodes dt-bindings: pwm: opencores: Add compatible for StarFive JH8100 dt-bindings: riscv: cpus: reg matches hart ID riscv: dts: microchip: add specific compatible for mpfs pdma riscv: dts: microchip: add missing CAN bus clocks riscv: dts: starfive: beaglev-starlight: Setup phy reset gpio riscv: dts: starfive: visionfive-v1: Setup ethernet phy riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmac riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodes riscv: dts: starfive: jh7110: Add PWM node and pins configuration riscv: dts: starfive: jh7100: Add PWM node and pins configuration dt-bindings: pwm: Add bindings for OpenCores PWM Controller Link: https://lore.kernel.org/r/20240305-iodine-moneywise-53797ae9bf6e@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
ee7dad0b81
56
Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
Normal file
56
Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
Normal file
@ -0,0 +1,56 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: OpenCores PWM controller
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maintainers:
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- William Qiu <william.qiu@starfivetech.com>
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description:
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The OpenCores PTC ip core contains a PWM controller. When operating in PWM
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mode, the PTC core generates binary signal with user-programmable low and
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high periods. All PTC counters and registers are 32-bit.
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allOf:
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- $ref: pwm.yaml#
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properties:
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compatible:
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items:
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- enum:
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- starfive,jh7100-pwm
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- starfive,jh7110-pwm
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- starfive,jh8100-pwm
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- const: opencores,pwm-v1
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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"#pwm-cells":
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const: 3
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required:
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- compatible
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- reg
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- clocks
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additionalProperties: false
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examples:
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- |
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pwm@12490000 {
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compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
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reg = <0x12490000 0x10000>;
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clocks = <&clkgen 181>;
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resets = <&rstgen 109>;
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#pwm-cells = <3>;
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};
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@ -75,6 +75,10 @@ properties:
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- riscv,sv57
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- riscv,none
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reg:
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description:
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The hart ID of this CPU node.
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riscv,cbom-block-size:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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@ -243,7 +243,7 @@
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};
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pdma: dma-controller@3000000 {
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compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
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compatible = "microchip,mpfs-pdma", "sifive,pdma0";
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reg = <0x0 0x3000000 0x0 0x8000>;
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interrupt-parent = <&plic>;
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interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
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@ -422,7 +422,7 @@
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can0: can@2010c000 {
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compatible = "microchip,mpfs-can";
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reg = <0x0 0x2010c000 0x0 0x1000>;
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clocks = <&clkcfg CLK_CAN0>;
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clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>;
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interrupt-parent = <&plic>;
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interrupts = <56>;
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status = "disabled";
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@ -431,7 +431,7 @@
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can1: can@2010d000 {
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compatible = "microchip,mpfs-can";
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reg = <0x0 0x2010d000 0x0 0x1000>;
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clocks = <&clkcfg CLK_CAN1>;
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clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>;
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interrupt-parent = <&plic>;
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interrupts = <57>;
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status = "disabled";
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@ -11,3 +11,14 @@
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model = "BeagleV Starlight Beta";
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compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100";
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};
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&gmac {
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phy-handle = <&phy>;
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};
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&mdio {
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phy: ethernet-phy@7 {
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reg = <7>;
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reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
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};
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};
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@ -72,7 +72,91 @@
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};
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};
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&gmac {
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pinctrl-names = "default";
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pinctrl-0 = <&gmac_pins>;
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phy-mode = "rgmii-id";
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status = "okay";
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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};
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};
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&gpio {
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gmac_pins: gmac-0 {
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gtxclk-pins {
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pins = <PAD_FUNC_SHARE(115)>;
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bias-pull-up;
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drive-strength = <35>;
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input-enable;
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input-schmitt-enable;
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slew-rate = <0>;
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};
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miitxclk-pins {
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pins = <PAD_FUNC_SHARE(116)>;
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bias-pull-up;
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drive-strength = <14>;
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input-enable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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tx-pins {
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pins = <PAD_FUNC_SHARE(117)>,
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<PAD_FUNC_SHARE(119)>,
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<PAD_FUNC_SHARE(120)>,
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<PAD_FUNC_SHARE(121)>,
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<PAD_FUNC_SHARE(122)>,
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<PAD_FUNC_SHARE(123)>,
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<PAD_FUNC_SHARE(124)>,
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<PAD_FUNC_SHARE(125)>,
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<PAD_FUNC_SHARE(126)>;
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bias-pull-up;
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drive-strength = <35>;
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input-disable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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rxclk-pins {
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pins = <PAD_FUNC_SHARE(127)>;
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bias-pull-up;
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drive-strength = <14>;
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input-enable;
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input-schmitt-disable;
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slew-rate = <6>;
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};
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rxer-pins {
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pins = <PAD_FUNC_SHARE(129)>;
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bias-pull-up;
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drive-strength = <14>;
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input-enable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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rx-pins {
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pins = <PAD_FUNC_SHARE(128)>,
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<PAD_FUNC_SHARE(130)>,
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<PAD_FUNC_SHARE(131)>,
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<PAD_FUNC_SHARE(132)>,
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<PAD_FUNC_SHARE(133)>,
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<PAD_FUNC_SHARE(134)>,
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<PAD_FUNC_SHARE(135)>,
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<PAD_FUNC_SHARE(136)>,
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<PAD_FUNC_SHARE(137)>,
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<PAD_FUNC_SHARE(138)>,
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<PAD_FUNC_SHARE(139)>,
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<PAD_FUNC_SHARE(140)>,
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<PAD_FUNC_SHARE(141)>;
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bias-pull-up;
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drive-strength = <14>;
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input-enable;
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input-schmitt-enable;
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slew-rate = <0>;
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};
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};
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i2c0_pins: i2c0-0 {
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i2c-pins {
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pinmux = <GPIOMUX(62, GPO_LOW,
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@ -115,6 +199,24 @@
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};
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};
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pwm_pins: pwm-0 {
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pwm-pins {
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pinmux = <GPIOMUX(7,
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GPO_PWM_PAD_OUT_BIT0,
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GPO_PWM_PAD_OE_N_BIT0,
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GPI_NONE)>,
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<GPIOMUX(5,
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GPO_PWM_PAD_OUT_BIT1,
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GPO_PWM_PAD_OE_N_BIT1,
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GPI_NONE)>;
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bias-disable;
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drive-strength = <35>;
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input-disable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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};
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sdio0_pins: sdio0-0 {
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clk-pins {
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pinmux = <GPIOMUX(54, GPO_SDIO0_PAD_CCLK_OUT,
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@ -257,6 +359,12 @@
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clock-frequency = <27000000>;
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};
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&pwm {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm_pins>;
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status = "okay";
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};
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&sdio0 {
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broken-cd;
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bus-width = <4>;
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@ -6,7 +6,6 @@
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/dts-v1/;
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#include "jh7100-common.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "StarFive VisionFive V1";
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@ -18,3 +17,24 @@
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priority = <224>;
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};
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};
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&gmac {
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phy-handle = <&phy>;
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};
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/*
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* The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
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* manual adjustment of the RX internal delay to work properly. The default
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* RX delay provided by the driver (1.95ns) is too high, but applying a 50%
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* reduction seems to mitigate the issue.
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*
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* It is worth noting the adjustment is not necessary on BeagleV Starlight SBC,
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* which uses a Microchip PHY. Hence, most likely the Motorcomm PHY is the one
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* responsible for the misbehaviour, not the GMAC.
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*/
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&mdio {
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phy: ethernet-phy@0 {
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reg = <0>;
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rx-internal-delay-ps = <900>;
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};
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};
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@ -204,6 +204,37 @@
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status = "disabled";
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};
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gmac: ethernet@10020000 {
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compatible = "starfive,jh7100-dwmac", "snps,dwmac";
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reg = <0x0 0x10020000 0x0 0x10000>;
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clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>,
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<&clkgen JH7100_CLK_GMAC_AHB>,
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<&clkgen JH7100_CLK_GMAC_PTP_REF>,
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<&clkgen JH7100_CLK_GMAC_TX_INV>,
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<&clkgen JH7100_CLK_GMAC_GTX>;
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clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx";
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resets = <&rstgen JH7100_RSTN_GMAC_AHB>;
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reset-names = "ahb";
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interrupts = <6>, <7>;
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interrupt-names = "macirq", "eth_wake_irq";
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max-frame-size = <9000>;
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snps,multicast-filter-bins = <32>;
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snps,perfect-filter-entries = <128>;
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starfive,syscon = <&sysmain 0x70 0>;
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rx-fifo-depth = <32768>;
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tx-fifo-depth = <16384>;
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snps,axi-config = <&stmmac_axi_setup>;
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snps,fixed-burst;
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snps,force_thresh_dma_mode;
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status = "disabled";
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stmmac_axi_setup: stmmac-axi-config {
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snps,wr_osr_lmt = <16>;
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snps,rd_osr_lmt = <16>;
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snps,blen = <256 128 64 32 0 0 0>;
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};
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};
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clkgen: clock-controller@11800000 {
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compatible = "starfive,jh7100-clkgen";
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reg = <0x0 0x11800000 0x0 0x10000>;
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@ -218,6 +249,11 @@
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#reset-cells = <1>;
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};
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sysmain: syscon@11850000 {
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compatible = "starfive,jh7100-sysmain", "syscon";
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reg = <0x0 0x11850000 0x0 0x10000>;
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};
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i2c0: i2c@118b0000 {
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compatible = "snps,designware-i2c";
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reg = <0x0 0x118b0000 0x0 0x10000>;
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@ -320,6 +356,15 @@
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<&rstgen JH7100_RSTN_WDT>;
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};
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||||
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pwm: pwm@12490000 {
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compatible = "starfive,jh7100-pwm", "opencores,pwm-v1";
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reg = <0x0 0x12490000 0x0 0x10000>;
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clocks = <&clkgen JH7100_CLK_PWM_APB>;
|
||||
resets = <&rstgen JH7100_RSTN_PWM_APB>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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|
||||
sfctemp: temperature-sensor@124a0000 {
|
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compatible = "starfive,jh7100-temp";
|
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reg = <0x0 0x124a0000 0x0 0x10000>;
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@ -125,6 +125,55 @@
|
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clock-frequency = <49152000>;
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};
|
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&camss {
|
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assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
|
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<&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>;
|
||||
assigned-clock-rates = <49500000>, <198000000>;
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
camss_from_csi2rx: endpoint {
|
||||
remote-endpoint = <&csi2rx_to_camss>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&csi2rx {
|
||||
assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
|
||||
assigned-clock-rates = <297000000>;
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
/* remote MIPI sensor endpoint */
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
csi2rx_to_camss: endpoint {
|
||||
remote-endpoint = <&camss_from_csi2rx>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
@ -323,6 +372,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
&pwm {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
@ -513,6 +568,22 @@
|
||||
};
|
||||
};
|
||||
|
||||
pwm_pins: pwm-0 {
|
||||
pwm-pins {
|
||||
pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
|
||||
GPOEN_SYS_PWM0_CHANNEL0,
|
||||
GPI_NONE)>,
|
||||
<GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
|
||||
GPOEN_SYS_PWM0_CHANNEL1,
|
||||
GPI_NONE)>;
|
||||
bias-disable;
|
||||
drive-strength = <12>;
|
||||
input-disable;
|
||||
input-schmitt-disable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
spi0_pins: spi0-0 {
|
||||
mosi-pins {
|
||||
pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
|
||||
|
||||
@ -829,6 +829,15 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm: pwm@120d0000 {
|
||||
compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
|
||||
reg = <0x0 0x120d0000 0x0 0x10000>;
|
||||
clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
|
||||
resets = <&syscrg JH7110_SYSRST_PWM_APB>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sfctemp: temperature-sensor@120e0000 {
|
||||
compatible = "starfive,jh7110-temp";
|
||||
reg = <0x0 0x120e0000 0x0 0x10000>;
|
||||
@ -1104,6 +1113,32 @@
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
csi2rx: csi@19800000 {
|
||||
compatible = "starfive,jh7110-csi2rx", "cdns,csi2rx";
|
||||
reg = <0x0 0x19800000 0x0 0x10000>;
|
||||
clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>,
|
||||
<&ispcrg JH7110_ISPCLK_VIN_APB>,
|
||||
<&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF0>,
|
||||
<&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF1>,
|
||||
<&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF2>,
|
||||
<&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF3>;
|
||||
clock-names = "sys_clk", "p_clk",
|
||||
"pixel_if0_clk", "pixel_if1_clk",
|
||||
"pixel_if2_clk", "pixel_if3_clk";
|
||||
resets = <&ispcrg JH7110_ISPRST_VIN_SYS>,
|
||||
<&ispcrg JH7110_ISPRST_VIN_APB>,
|
||||
<&ispcrg JH7110_ISPRST_VIN_PIXEL_IF0>,
|
||||
<&ispcrg JH7110_ISPRST_VIN_PIXEL_IF1>,
|
||||
<&ispcrg JH7110_ISPRST_VIN_PIXEL_IF2>,
|
||||
<&ispcrg JH7110_ISPRST_VIN_PIXEL_IF3>;
|
||||
reset-names = "sys", "reg_bank",
|
||||
"pixel_if0", "pixel_if1",
|
||||
"pixel_if2", "pixel_if3";
|
||||
phys = <&csi_phy>;
|
||||
phy-names = "dphy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ispcrg: clock-controller@19810000 {
|
||||
compatible = "starfive,jh7110-ispcrg";
|
||||
reg = <0x0 0x19810000 0x0 0x10000>;
|
||||
@ -1121,6 +1156,47 @@
|
||||
power-domains = <&pwrc JH7110_PD_ISP>;
|
||||
};
|
||||
|
||||
csi_phy: phy@19820000 {
|
||||
compatible = "starfive,jh7110-dphy-rx";
|
||||
reg = <0x0 0x19820000 0x0 0x10000>;
|
||||
clocks = <&ispcrg JH7110_ISPCLK_M31DPHY_CFG_IN>,
|
||||
<&ispcrg JH7110_ISPCLK_M31DPHY_REF_IN>,
|
||||
<&ispcrg JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0>;
|
||||
clock-names = "cfg", "ref", "tx";
|
||||
resets = <&ispcrg JH7110_ISPRST_M31DPHY_HW>,
|
||||
<&ispcrg JH7110_ISPRST_M31DPHY_B09_AON>;
|
||||
power-domains = <&aon_syscon JH7110_AON_PD_DPHY_RX>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
camss: isp@19840000 {
|
||||
compatible = "starfive,jh7110-camss";
|
||||
reg = <0x0 0x19840000 0x0 0x10000>,
|
||||
<0x0 0x19870000 0x0 0x30000>;
|
||||
reg-names = "syscon", "isp";
|
||||
clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
|
||||
<&ispcrg JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C>,
|
||||
<&ispcrg JH7110_ISPCLK_DVP_INV>,
|
||||
<&ispcrg JH7110_ISPCLK_VIN_P_AXI_WR>,
|
||||
<&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>,
|
||||
<&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
|
||||
<&syscrg JH7110_SYSCLK_ISP_TOP_AXI>;
|
||||
clock-names = "apb_func", "wrapper_clk_c", "dvp_inv",
|
||||
"axiwr", "mipi_rx0_pxl", "ispcore_2x",
|
||||
"isp_axi";
|
||||
resets = <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_P>,
|
||||
<&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_C>,
|
||||
<&ispcrg JH7110_ISPRST_VIN_P_AXI_RD>,
|
||||
<&ispcrg JH7110_ISPRST_VIN_P_AXI_WR>,
|
||||
<&syscrg JH7110_SYSRST_ISP_TOP>,
|
||||
<&syscrg JH7110_SYSRST_ISP_TOP_AXI>;
|
||||
reset-names = "wrapper_p", "wrapper_c", "axird",
|
||||
"axiwr", "isp_top_n", "isp_top_axi";
|
||||
power-domains = <&pwrc JH7110_PD_ISP>;
|
||||
interrupts = <92>, <87>, <90>, <88>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
voutcrg: clock-controller@295c0000 {
|
||||
compatible = "starfive,jh7110-voutcrg";
|
||||
reg = <0x0 0x295c0000 0x0 0x10000>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user