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scsi: mpi3mr: Update mpi3 header files
Update the mpi3 header files. Link: https://lore.kernel.org/r/20220912135742.11764-2-sreekanth.reddy@broadcom.com Signed-off-by: Sreekanth Reddy <sreekanth.reddy@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Sreekanth Reddy
Martin K. Petersen
parent
d82e68483b
commit
ee6f2d6bb2
@ -1,7 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright 2017-2021 Broadcom Inc. All rights reserved.
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*
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* Copyright 2017-2022 Broadcom Inc. All rights reserved.
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*/
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#ifndef MPI30_CNFG_H
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#define MPI30_CNFG_H 1
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@ -100,6 +99,7 @@ struct mpi3_config_page_header {
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#define MPI3_SAS_NEG_LINK_RATE_LOGICAL_MASK (0xf0)
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#define MPI3_SAS_NEG_LINK_RATE_LOGICAL_SHIFT (4)
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#define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_MASK (0x0f)
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#define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_SHIFT (0)
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#define MPI3_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
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#define MPI3_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
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#define MPI3_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
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@ -135,6 +135,16 @@ struct mpi3_config_page_header {
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#define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_ACTIVE (0x00000000)
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#define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_PARTIAL (0x08000000)
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#define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_SLUMBER (0x10000000)
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#define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_SHIFT (0)
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#define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_MASK (0x04000000)
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#define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_SHIFT (26)
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#define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_MASK (0x02000000)
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#define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_SHIFT (25)
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#define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_MASK (0x01000000)
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#define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_SHIFT (24)
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#define MPI3_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
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#define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_WITHIN (0x00200000)
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#define MPI3_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
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#define MPI3_SAS_PHYINFO_REASON_MASK (0x000f0000)
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#define MPI3_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
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#define MPI3_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
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@ -210,7 +220,7 @@ struct mpi3_man_page0 {
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u8 board_rework_day;
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u8 board_rework_month;
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__le16 board_rework_year;
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__le64 board_revision;
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u8 board_revision[8];
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u8 e_pack_fru[16];
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u8 product_name[256];
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};
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@ -226,6 +236,15 @@ struct mpi3_man_page1 {
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};
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#define MPI3_MAN1_PAGEVERSION (0x00)
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struct mpi3_man_page2 {
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struct mpi3_config_page_header header;
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u8 flags;
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u8 reserved09[3];
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__le32 reserved0c[3];
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u8 oem_board_tracer_number[32];
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};
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#define MPI3_MAN2_PAGEVERSION (0x00)
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#define MPI3_MAN2_FLAGS_TRACER_PRESENT (0x01)
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struct mpi3_man5_phy_entry {
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__le64 ioc_wwid;
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__le64 device_name;
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@ -338,6 +357,8 @@ struct mpi3_man7_receptacle_info {
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#define MPI3_MAN7_LOCATION_INTERNAL (0x01)
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#define MPI3_MAN7_LOCATION_EXTERNAL (0x02)
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#define MPI3_MAN7_LOCATION_VIRTUAL (0x03)
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#define MPI3_MAN7_LOCATION_HOST (0x04)
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#define MPI3_MAN7_CONNECTOR_TYPE_NO_INFO (0x00)
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#define MPI3_MAN7_PEDCLK_ROUTING_MASK (0x10)
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#define MPI3_MAN7_PEDCLK_ROUTING_DIRECT (0x00)
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#define MPI3_MAN7_PEDCLK_ROUTING_CLOCK_BUFFER (0x10)
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@ -369,7 +390,8 @@ struct mpi3_man8_phy_info {
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__le32 reserved0c;
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};
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#define MPI3_MAN8_PHY_INFO_RECEPTACLE_ID_HOST_PHY (0xff)
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#define MPI3_MAN8_PHY_INFO_RECEPTACLE_ID_NOT_ASSOCIATED (0xff)
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#define MPI3_MAN8_PHY_INFO_CONNECTOR_LANE_NOT_ASSOCIATED (0xff)
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#ifndef MPI3_MAN8_PHY_INFO_MAX
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#define MPI3_MAN8_PHY_INFO_MAX (1)
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#endif
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@ -536,6 +558,10 @@ struct mpi3_man11_bkplane_spec_non_ubm_format {
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#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_MASK (0xf000)
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#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_SHIFT (12)
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#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED (0x0200)
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#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_MASK (0x00c0)
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#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_4 (0x0000)
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#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_2 (0x0040)
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#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_1 (0x0080)
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#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_MASK (0x0030)
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#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_GPIO (0x0000)
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#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_REG (0x0010)
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@ -825,19 +851,16 @@ struct mpi3_man_page21 {
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};
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#define MPI3_MAN21_PAGEVERSION (0x00)
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#define MPI3_MAN21_FLAGS_HOST_METADATA_CAPABILITY_MASK (0x80)
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#define MPI3_MAN21_FLAGS_HOST_METADATA_CAPABILITY_ENABLED (0x80)
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#define MPI3_MAN21_FLAGS_HOST_METADATA_CAPABILITY_DISABLED (0x00)
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#define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_MASK (0x60)
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#define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_BLOCK (0x00)
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#define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_ALLOW (0x20)
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#define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_WARN (0x40)
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#define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_MASK (0x08)
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#define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_ALLOW (0x00)
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#define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_PREVENT (0x08)
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#define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_MASK (0x01)
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#define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_DEFAULT (0x00)
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#define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_OEM_SPECIFIC (0x01)
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#define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_MASK (0x00000060)
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#define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_BLOCK (0x00000000)
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#define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_ALLOW (0x00000020)
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#define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_WARN (0x00000040)
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#define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_MASK (0x00000008)
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#define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_ALLOW (0x00000000)
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#define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_PREVENT (0x00000008)
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#define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_MASK (0x00000001)
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#define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_DEFAULT (0x00000000)
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#define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_OEM_SPECIFIC (0x00000001)
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#ifndef MPI3_MAN_PROD_SPECIFIC_MAX
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#define MPI3_MAN_PROD_SPECIFIC_MAX (1)
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#endif
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@ -995,7 +1018,12 @@ struct mpi3_io_unit_page5 {
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#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_MASK (0x000c)
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#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_SHIFT (2)
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#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_MASK (0x0003)
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#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAA_SSD_SHIFT (0)
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#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_SHIFT (0)
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#define MPI3_IOUNIT5_FLAGS_SATAPUIS_MASK (0x0c)
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#define MPI3_IOUNIT5_FLAGS_SATAPUIS_NOT_SUPPORTED (0x00)
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#define MPI3_IOUNIT5_FLAGS_SATAPUIS_OS_CONTROLLED (0x04)
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#define MPI3_IOUNIT5_FLAGS_SATAPUIS_APP_CONTROLLED (0x08)
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#define MPI3_IOUNIT5_FLAGS_SATAPUIS_BLOCKED (0x0c)
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#define MPI3_IOUNIT5_FLAGS_POWER_CAPABLE_SPINUP (0x02)
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#define MPI3_IOUNIT5_FLAGS_AUTO_PORT_ENABLE (0x01)
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#define MPI3_IOUNIT5_PHY_SPINUP_GROUP_MASK (0x03)
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@ -1027,7 +1055,8 @@ struct mpi3_io_unit_page8 {
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u8 slots_available;
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u8 current_key_encryption_algo;
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u8 key_digest_hash_algo;
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__le32 reserved10[2];
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union mpi3_version_union current_svn;
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__le32 reserved14;
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__le32 current_key[128];
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union mpi3_iounit8_digest digest[MPI3_IOUNIT8_DIGEST_MAX];
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};
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@ -1036,6 +1065,7 @@ struct mpi3_io_unit_page8 {
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#define MPI3_IOUNIT8_SBMODE_SECURE_DEBUG (0x04)
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#define MPI3_IOUNIT8_SBMODE_HARD_SECURE (0x02)
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#define MPI3_IOUNIT8_SBMODE_CONFIG_SECURE (0x01)
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#define MPI3_IOUNIT8_SBSTATE_SVN_UPDATE_PENDING (0x04)
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#define MPI3_IOUNIT8_SBSTATE_KEY_UPDATE_PENDING (0x02)
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#define MPI3_IOUNIT8_SBSTATE_SECURE_BOOT_ENABLED (0x01)
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struct mpi3_io_unit_page9 {
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@ -1045,9 +1075,14 @@ struct mpi3_io_unit_page9 {
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__le16 reserved0e;
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};
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#define MPI3_IOUNIT9_PAGEVERSION (0x00)
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#define MPI3_IOUNIT9_FLAGS_VDFIRST_ENABLED (0x01)
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#define MPI3_IOUNIT9_FIRSTDEVICE_UNKNOWN (0xffff)
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#define MPI3_IOUNIT9_PAGEVERSION (0x00)
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#define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_MASK (0x00000006)
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#define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_SHIFT (1)
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#define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_NONE (0x00000000)
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#define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_RECEPTACLE (0x00000002)
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#define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_BACKPLANE_TYPE (0x00000004)
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#define MPI3_IOUNIT9_FLAGS_VDFIRST_ENABLED (0x00000001)
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#define MPI3_IOUNIT9_FIRSTDEVICE_UNKNOWN (0xffff)
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struct mpi3_io_unit_page10 {
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struct mpi3_config_page_header header;
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u8 flags;
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@ -1090,6 +1125,57 @@ struct mpi3_io_unit_page11 {
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struct mpi3_iounit11_profile profile[MPI3_IOUNIT11_PROFILE_MAX];
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};
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#define MPI3_IOUNIT11_PAGEVERSION (0x00)
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#ifndef MPI3_IOUNIT12_BUCKET_MAX
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#define MPI3_IOUNIT12_BUCKET_MAX (1)
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#endif
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struct mpi3_iounit12_bucket {
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u8 coalescing_depth;
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u8 coalescing_timeout;
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__le16 io_count_low_boundary;
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__le32 reserved04;
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};
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struct mpi3_io_unit_page12 {
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struct mpi3_config_page_header header;
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__le32 flags;
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__le32 reserved0c[4];
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u8 num_buckets;
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u8 reserved1d[3];
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struct mpi3_iounit12_bucket bucket[MPI3_IOUNIT12_BUCKET_MAX];
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};
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#define MPI3_IOUNIT12_PAGEVERSION (0x00)
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#define MPI3_IOUNIT12_FLAGS_NUMPASSES_MASK (0x00000300)
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#define MPI3_IOUNIT12_FLAGS_NUMPASSES_SHIFT (8)
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#define MPI3_IOUNIT12_FLAGS_NUMPASSES_8 (0x00000000)
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#define MPI3_IOUNIT12_FLAGS_NUMPASSES_16 (0x00000100)
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#define MPI3_IOUNIT12_FLAGS_NUMPASSES_32 (0x00000200)
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#define MPI3_IOUNIT12_FLAGS_NUMPASSES_64 (0x00000300)
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#define MPI3_IOUNIT12_FLAGS_PASSPERIOD_MASK (0x00000003)
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#define MPI3_IOUNIT12_FLAGS_PASSPERIOD_DISABLED (0x00000000)
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#define MPI3_IOUNIT12_FLAGS_PASSPERIOD_500US (0x00000001)
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#define MPI3_IOUNIT12_FLAGS_PASSPERIOD_1MS (0x00000002)
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#define MPI3_IOUNIT12_FLAGS_PASSPERIOD_2MS (0x00000003)
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#ifndef MPI3_IOUNIT13_FUNC_MAX
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#define MPI3_IOUNIT13_FUNC_MAX (1)
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#endif
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struct mpi3_iounit13_allowed_function {
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__le16 sub_function;
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u8 function_code;
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u8 fuction_flags;
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};
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#define MPI3_IOUNIT13_FUNCTION_FLAGS_ADMIN_BLOCKED (0x04)
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#define MPI3_IOUNIT13_FUNCTION_FLAGS_OOB_BLOCKED (0x02)
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#define MPI3_IOUNIT13_FUNCTION_FLAGS_CHECK_SUBFUNCTION_ENABLED (0x01)
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struct mpi3_io_unit_page13 {
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struct mpi3_config_page_header header;
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__le16 flags;
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__le16 reserved0a;
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u8 num_allowed_functions;
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u8 reserved0d[3];
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struct mpi3_iounit13_allowed_function allowed_function[MPI3_IOUNIT13_FUNC_MAX];
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};
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#define MPI3_IOUNIT13_PAGEVERSION (0x00)
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#define MPI3_IOUNIT13_FLAGS_ADMIN_BLOCKED (0x0002)
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#define MPI3_IOUNIT13_FLAGS_OOB_BLOCKED (0x0001)
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struct mpi3_ioc_page0 {
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struct mpi3_config_page_header header;
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__le32 reserved08;
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@ -1182,6 +1268,7 @@ struct mpi3_driver_page0 {
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__le32 reserved18;
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};
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#define MPI3_DRIVER0_PAGEVERSION (0x00)
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#define MPI3_DRIVER0_BSDOPTS_HEADLESS_MODE_ENABLE (0x00000008)
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#define MPI3_DRIVER0_BSDOPTS_DIS_HII_CONFIG_UTIL (0x00000004)
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#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_MASK (0x00000003)
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#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_DEVS (0x00000000)
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@ -1906,19 +1993,30 @@ struct mpi3_pcie_io_unit_page1 {
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};
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#define MPI3_PCIEIOUNIT1_PAGEVERSION (0x00)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_OVERRIDE_DISABLE (0x80)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_DISABLE (0x40)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_MASK (0x30)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_MASK (0xe0000000)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_NONE (0x00000000)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_DEASSERT (0x20000000)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_ASSERT (0x40000000)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_BACKPLANE_ERROR (0x60000000)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_MASK (0x1c000000)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_NONE (0x00000000)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_DEASSERT (0x04000000)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_ASSERT (0x08000000)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_BACKPLANE_ERROR (0x0c000000)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_OVERRIDE_DISABLE (0x00000080)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_DISABLE (0x00000040)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_MASK (0x00000030)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SHIFT (4)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_SRNS_DISABLED (0x00)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_ENABLED (0x10)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRNS_ENABLED (0x20)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MASK (0x0f)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_2_5 (0x02)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_5_0 (0x03)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_8_0 (0x04)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_16_0 (0x05)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_32_0 (0x06)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_SRNS_DISABLED (0x00000000)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_ENABLED (0x00000010)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRNS_ENABLED (0x00000020)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MASK (0x0000000f)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_USE_BACKPLANE (0x00000000)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_2_5 (0x00000002)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_5_0 (0x00000003)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_8_0 (0x00000004)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_16_0 (0x00000005)
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#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_32_0 (0x00000006)
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#define MPI3_PCIEIOUNIT1_ASPM_SWITCH_MASK (0x0c)
|
||||
#define MPI3_PCIEIOUNIT1_ASPM_SWITCH_SHIFT (2)
|
||||
#define MPI3_PCIEIOUNIT1_ASPM_DIRECT_MASK (0x03)
|
||||
@ -2169,10 +2267,7 @@ struct mpi3_device0_vd_format {
|
||||
#define MPI3_DEVICE0_VD_DEVICE_INFO_SATA (0x0002)
|
||||
#define MPI3_DEVICE0_VD_DEVICE_INFO_SAS (0x0001)
|
||||
#define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_MASK (0xf000)
|
||||
#define MPI3_DEVICE0_VD_FLAGS_METADATA_MODE_MASK (0x0003)
|
||||
#define MPI3_DEVICE0_VD_FLAGS_METADATA_MODE_NONE (0x0000)
|
||||
#define MPI3_DEVICE0_VD_FLAGS_METADATA_MODE_HOST (0x0001)
|
||||
#define MPI3_DEVICE0_VD_FLAGS_METADATA_MODE_IOC (0x0002)
|
||||
#define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_SHIFT (12)
|
||||
union mpi3_device0_dev_spec_format {
|
||||
struct mpi3_device0_sas_sata_format sas_sata_format;
|
||||
struct mpi3_device0_pcie_format pcie_format;
|
||||
|
||||
@ -1,7 +1,6 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright 2018-2021 Broadcom Inc. All rights reserved.
|
||||
*
|
||||
* Copyright 2018-2022 Broadcom Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef MPI30_IMAGE_H
|
||||
#define MPI30_IMAGE_H 1
|
||||
@ -63,6 +62,9 @@ struct mpi3_component_image_header {
|
||||
#define MPI3_IMAGE_HEADER_SIGNATURE1_PBLP (0x504c4250)
|
||||
#define MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST (0x464e414d)
|
||||
#define MPI3_IMAGE_HEADER_SIGNATURE1_OEM (0x204d454f)
|
||||
#define MPI3_IMAGE_HEADER_SIGNATURE1_RMC (0x20434d52)
|
||||
#define MPI3_IMAGE_HEADER_SIGNATURE1_SMM (0x204d4d53)
|
||||
#define MPI3_IMAGE_HEADER_SIGNATURE1_PSW (0x20575350)
|
||||
#define MPI3_IMAGE_HEADER_SIGNATURE2_VALUE (0x50584546)
|
||||
#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_MASK (0x00000030)
|
||||
#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_CDI (0x00000000)
|
||||
|
||||
@ -1,13 +1,12 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright 2016-2021 Broadcom Inc. All rights reserved.
|
||||
*
|
||||
* Copyright 2016-2022 Broadcom Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef MPI30_INIT_H
|
||||
#define MPI30_INIT_H 1
|
||||
struct mpi3_scsi_io_cdb_eedp32 {
|
||||
u8 cdb[20];
|
||||
__be32 primary_reference_tag;
|
||||
__be32 primary_reference_tag;
|
||||
__le16 primary_application_tag;
|
||||
__le16 primary_application_tag_mask;
|
||||
__le32 transfer_length;
|
||||
|
||||
@ -1,7 +1,6 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright 2016-2021 Broadcom Inc. All rights reserved.
|
||||
*
|
||||
* Copyright 2016-2022 Broadcom Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef MPI30_IOC_H
|
||||
#define MPI30_IOC_H 1
|
||||
@ -158,6 +157,7 @@ struct mpi3_ioc_facts_data {
|
||||
#define MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA (0x00000000)
|
||||
#define MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR (0x00000002)
|
||||
#define MPI3_IOCFACTS_IO_THROTTLE_DATA_LENGTH_NOT_REQUIRED (0x0000)
|
||||
#define MPI3_IOCFACTS_MAX_IO_THROTTLE_GROUP_NOT_REQUIRED (0x0000)
|
||||
struct mpi3_mgmt_passthrough_request {
|
||||
__le16 host_tag;
|
||||
u8 ioc_use_only02;
|
||||
@ -637,6 +637,23 @@ struct mpi3_event_data_diag_buffer_status_change {
|
||||
#define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RELEASED (0x01)
|
||||
#define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_PAUSED (0x02)
|
||||
#define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RESUMED (0x03)
|
||||
#define MPI3_PEL_LOCALE_FLAGS_NON_BLOCKING_BOOT_EVENT (0x0200)
|
||||
#define MPI3_PEL_LOCALE_FLAGS_BLOCKING_BOOT_EVENT (0x0100)
|
||||
#define MPI3_PEL_LOCALE_FLAGS_PCIE (0x0080)
|
||||
#define MPI3_PEL_LOCALE_FLAGS_CONFIGURATION (0x0040)
|
||||
#define MPI3_PEL_LOCALE_FLAGS_CONTROLER (0x0020)
|
||||
#define MPI3_PEL_LOCALE_FLAGS_SAS (0x0010)
|
||||
#define MPI3_PEL_LOCALE_FLAGS_EPACK (0x0008)
|
||||
#define MPI3_PEL_LOCALE_FLAGS_ENCLOSURE (0x0004)
|
||||
#define MPI3_PEL_LOCALE_FLAGS_PD (0x0002)
|
||||
#define MPI3_PEL_LOCALE_FLAGS_VD (0x0001)
|
||||
#define MPI3_PEL_CLASS_DEBUG (0x00)
|
||||
#define MPI3_PEL_CLASS_PROGRESS (0x01)
|
||||
#define MPI3_PEL_CLASS_INFORMATIONAL (0x02)
|
||||
#define MPI3_PEL_CLASS_WARNING (0x03)
|
||||
#define MPI3_PEL_CLASS_CRITICAL (0x04)
|
||||
#define MPI3_PEL_CLASS_FATAL (0x05)
|
||||
#define MPI3_PEL_CLASS_FAULT (0x06)
|
||||
#define MPI3_PEL_CLEARTYPE_CLEAR (0x00)
|
||||
#define MPI3_PEL_WAITTIME_INFINITE_WAIT (0x00)
|
||||
#define MPI3_PEL_ACTION_GET_SEQNUM (0x01)
|
||||
@ -924,6 +941,7 @@ struct mpi3_ci_download_reply {
|
||||
};
|
||||
|
||||
#define MPI3_CI_DOWNLOAD_FLAGS_DOWNLOAD_IN_PROGRESS (0x80)
|
||||
#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_FAILURE (0x40)
|
||||
#define MPI3_CI_DOWNLOAD_FLAGS_OFFLINE_ACTIVATION_REQUIRED (0x20)
|
||||
#define MPI3_CI_DOWNLOAD_FLAGS_KEY_UPDATE_PENDING (0x10)
|
||||
#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_MASK (0x0e)
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright 2016-2021 Broadcom Inc. All rights reserved.
|
||||
* Copyright 2016-2022 Broadcom Inc. All rights reserved.
|
||||
*
|
||||
*/
|
||||
#ifndef MPI30_PCI_H
|
||||
|
||||
@ -1,7 +1,6 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright 2016-2021 Broadcom Inc. All rights reserved.
|
||||
*
|
||||
* Copyright 2016-2022 Broadcom Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef MPI30_SAS_H
|
||||
#define MPI30_SAS_H 1
|
||||
|
||||
@ -1,7 +1,6 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright 2016-2021 Broadcom Inc. All rights reserved.
|
||||
*
|
||||
* Copyright 2016-2022 Broadcom Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef MPI30_TRANSPORT_H
|
||||
#define MPI30_TRANSPORT_H 1
|
||||
@ -19,8 +18,8 @@ union mpi3_version_union {
|
||||
|
||||
#define MPI3_VERSION_MAJOR (3)
|
||||
#define MPI3_VERSION_MINOR (0)
|
||||
#define MPI3_VERSION_UNIT (23)
|
||||
#define MPI3_VERSION_DEV (1)
|
||||
#define MPI3_VERSION_UNIT (26)
|
||||
#define MPI3_VERSION_DEV (0)
|
||||
#define MPI3_DEVHANDLE_INVALID (0xffff)
|
||||
struct mpi3_sysif_oper_queue_indexes {
|
||||
__le16 producer_index;
|
||||
@ -212,6 +211,7 @@ struct mpi3_default_reply_descriptor {
|
||||
#define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS (0x1000)
|
||||
#define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_TARGET_COMMAND_BUFFER (0x2000)
|
||||
#define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS (0x3000)
|
||||
#define MPI3_REPLY_DESCRIPT_REQUEST_QUEUE_ID_INVALID (0xffff)
|
||||
struct mpi3_address_reply_descriptor {
|
||||
__le64 reply_frame_address;
|
||||
__le16 request_queue_ci;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user