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clk: sunxi: Add a simple gates driver
The gates were handled with a common piece of framework that was registering all gates array, that was not using the CLK_OF_DECLARE logic, and was not using clock-indices but some private masks that were pretty much equivalent. Move this code in a new driver that handles all the gates array and solves both these issues. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> [sboyd@codeaurora.org: Include clk.h for consumer API usage] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Maxime Ripard
Stephen Boyd
parent
06f282757a
commit
ee38b2698a
@ -6,6 +6,7 @@ obj-y += clk-sunxi.o clk-factors.o
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obj-y += clk-a10-hosc.o
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obj-y += clk-a20-gmac.o
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obj-y += clk-mod0.o
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obj-y += clk-simple-gates.o
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obj-y += clk-sun8i-mbus.o
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obj-y += clk-sun9i-core.o
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obj-y += clk-sun9i-mmc.o
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158
drivers/clk/sunxi/clk-simple-gates.c
Normal file
158
drivers/clk/sunxi/clk-simple-gates.c
Normal file
@ -0,0 +1,158 @@
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/*
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* Copyright 2015 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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static DEFINE_SPINLOCK(gates_lock);
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static void __init sunxi_simple_gates_setup(struct device_node *node,
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const int protected[],
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int nprotected)
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{
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struct clk_onecell_data *clk_data;
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const char *clk_parent, *clk_name;
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struct property *prop;
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struct resource res;
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void __iomem *clk_reg;
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void __iomem *reg;
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const __be32 *p;
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int number, i = 0, j;
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u8 clk_bit;
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u32 index;
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reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (IS_ERR(reg))
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return;
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clk_parent = of_clk_get_parent_name(node, 0);
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clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
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if (!clk_data)
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goto err_unmap;
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number = of_property_count_u32_elems(node, "clock-indices");
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of_property_read_u32_index(node, "clock-indices", number - 1, &number);
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clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
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if (!clk_data->clks)
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goto err_free_data;
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of_property_for_each_u32(node, "clock-indices", prop, p, index) {
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of_property_read_string_index(node, "clock-output-names",
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i, &clk_name);
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clk_reg = reg + 4 * (index / 32);
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clk_bit = index % 32;
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clk_data->clks[index] = clk_register_gate(NULL, clk_name,
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clk_parent, 0,
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clk_reg,
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clk_bit,
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0, &gates_lock);
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i++;
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if (IS_ERR(clk_data->clks[index])) {
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WARN_ON(true);
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continue;
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}
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for (j = 0; j < nprotected; j++)
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if (protected[j] == index)
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clk_prepare_enable(clk_data->clks[index]);
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}
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clk_data->clk_num = number + 1;
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of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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return;
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err_free_data:
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kfree(clk_data);
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err_unmap:
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iounmap(reg);
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of_address_to_resource(node, 0, &res);
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release_mem_region(res.start, resource_size(&res));
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}
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static void __init sunxi_simple_gates_init(struct device_node *node)
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{
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sunxi_simple_gates_setup(node, NULL, 0);
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}
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CLK_OF_DECLARE(sun4i_a10_apb0, "allwinner,sun4i-a10-apb0-gates-clk",
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sunxi_simple_gates_init);
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CLK_OF_DECLARE(sun4i_a10_apb1, "allwinner,sun4i-a10-apb1-gates-clk",
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sunxi_simple_gates_init);
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CLK_OF_DECLARE(sun4i_a10_axi, "allwinner,sun4i-a10-axi-gates-clk",
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sunxi_simple_gates_init);
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CLK_OF_DECLARE(sun5i_a10s_apb0, "allwinner,sun5i-a10s-apb0-gates-clk",
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sunxi_simple_gates_init);
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CLK_OF_DECLARE(sun5i_a10s_apb1, "allwinner,sun5i-a10s-apb1-gates-clk",
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sunxi_simple_gates_init);
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CLK_OF_DECLARE(sun5i_a13_apb0, "allwinner,sun5i-a13-apb0-gates-clk",
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sunxi_simple_gates_init);
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CLK_OF_DECLARE(sun5i_a13_apb1, "allwinner,sun5i-a13-apb1-gates-clk",
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sunxi_simple_gates_init);
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CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-gates-clk",
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sunxi_simple_gates_init);
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CLK_OF_DECLARE(sun6i_a31_apb1, "allwinner,sun6i-a31-apb1-gates-clk",
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sunxi_simple_gates_init);
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CLK_OF_DECLARE(sun6i_a31_apb2, "allwinner,sun6i-a31-apb2-gates-clk",
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sunxi_simple_gates_init);
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CLK_OF_DECLARE(sun7i_a20_apb0, "allwinner,sun7i-a20-apb0-gates-clk",
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sunxi_simple_gates_init);
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CLK_OF_DECLARE(sun7i_a20_apb1, "allwinner,sun7i-a20-apb1-gates-clk",
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sunxi_simple_gates_init);
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CLK_OF_DECLARE(sun8i_a23_ahb1, "allwinner,sun8i-a23-ahb1-gates-clk",
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sunxi_simple_gates_init);
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CLK_OF_DECLARE(sun8i_a23_apb1, "allwinner,sun8i-a23-apb1-gates-clk",
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sunxi_simple_gates_init);
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CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
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sunxi_simple_gates_init);
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CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
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sunxi_simple_gates_init);
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CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
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sunxi_simple_gates_init);
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CLK_OF_DECLARE(sun9i_a80_ahb2, "allwinner,sun9i-a80-ahb2-gates-clk",
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sunxi_simple_gates_init);
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CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-gates-clk",
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sunxi_simple_gates_init);
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CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-gates-clk",
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sunxi_simple_gates_init);
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static const int sun4i_a10_ahb_critical_clocks[] __initconst = {
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14, /* ahb_sdram */
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};
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static void __init sun4i_a10_ahb_init(struct device_node *node)
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{
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sunxi_simple_gates_setup(node, sun4i_a10_ahb_critical_clocks,
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ARRAY_SIZE(sun4i_a10_ahb_critical_clocks));
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}
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CLK_OF_DECLARE(sun4i_a10_ahb, "allwinner,sun4i-a10-ahb-gates-clk",
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sun4i_a10_ahb_init);
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CLK_OF_DECLARE(sun5i_a10s_ahb, "allwinner,sun5i-a10s-ahb-gates-clk",
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sun4i_a10_ahb_init);
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CLK_OF_DECLARE(sun5i_a13_ahb, "allwinner,sun5i-a13-ahb-gates-clk",
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sun4i_a10_ahb_init);
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CLK_OF_DECLARE(sun7i_a20_ahb, "allwinner,sun7i-a20-ahb-gates-clk",
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sun4i_a10_ahb_init);
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@ -896,150 +896,6 @@ struct gates_data {
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DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
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};
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static const struct gates_data sun4i_axi_gates_data __initconst = {
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.mask = {1},
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};
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static const struct gates_data sun4i_ahb_gates_data __initconst = {
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.mask = {0x7F77FFF, 0x14FB3F},
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};
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static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
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.mask = {0x147667e7, 0x185915},
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};
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static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
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.mask = {0x107067e7, 0x185111},
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};
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static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
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.mask = {0xEDFE7F62, 0x794F931},
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};
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static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
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.mask = { 0x12f77fff, 0x16ff3f },
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};
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static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
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.mask = {0x25386742, 0x2505111},
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};
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static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
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.mask = {0xF5F12B},
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};
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static const struct gates_data sun9i_a80_ahb1_gates_data __initconst = {
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.mask = {0x1E20003},
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};
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static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
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.mask = {0x9B7},
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};
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static const struct gates_data sun4i_apb0_gates_data __initconst = {
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.mask = {0x4EF},
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};
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static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
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.mask = {0x469},
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};
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static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
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.mask = {0x61},
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};
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static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
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.mask = { 0x4ff },
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};
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static const struct gates_data sun9i_a80_apb0_gates_data __initconst = {
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.mask = {0xEB822},
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};
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static const struct gates_data sun4i_apb1_gates_data __initconst = {
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.mask = {0xFF00F7},
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};
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static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
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.mask = {0xf0007},
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};
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static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
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.mask = {0xa0007},
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};
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static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
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.mask = {0x3031},
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};
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static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
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.mask = {0x3021},
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};
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static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
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.mask = {0x3F000F},
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};
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static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
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.mask = { 0xff80ff },
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};
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static const struct gates_data sun9i_a80_apb1_gates_data __initconst = {
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.mask = {0x3F001F},
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};
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static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
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.mask = {0x1F0007},
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};
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static void __init sunxi_gates_clk_setup(struct device_node *node,
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struct gates_data *data)
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{
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struct clk_onecell_data *clk_data;
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const char *clk_parent;
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const char *clk_name;
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void __iomem *reg;
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int qty;
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int i = 0;
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int j = 0;
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reg = of_iomap(node, 0);
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clk_parent = of_clk_get_parent_name(node, 0);
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/* Worst-case size approximation and memory allocation */
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qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
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clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
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if (!clk_data)
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return;
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clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
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if (!clk_data->clks) {
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kfree(clk_data);
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return;
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}
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for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
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of_property_read_string_index(node, "clock-output-names",
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j, &clk_name);
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clk_data->clks[i] = clk_register_gate(NULL, clk_name,
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clk_parent, 0,
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reg + 4 * (i/32), i % 32,
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0, &clk_lock);
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WARN_ON(IS_ERR(clk_data->clks[i]));
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clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
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j++;
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}
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/* Adjust to the real max */
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clk_data->clk_num = i;
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of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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}
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/**
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* sunxi_divs_clk_setup() helper data
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*/
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@ -1277,34 +1133,6 @@ static const struct of_device_id clk_mux_match[] __initconst = {
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{}
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};
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/* Matches for gate clocks */
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static const struct of_device_id clk_gates_match[] __initconst = {
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{.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
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{.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
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{.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
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{.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
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{.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
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{.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
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{.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
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{.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
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{.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
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{.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
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{.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
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{.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
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{.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
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{.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
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{.compatible = "allwinner,sun9i-a80-apb0-gates-clk", .data = &sun9i_a80_apb0_gates_data,},
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{.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
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{.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
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{.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
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{.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
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{.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
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{.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
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{.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
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{.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
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{.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
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{}
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};
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static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
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void *function)
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@ -1336,9 +1164,6 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
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/* Register mux clocks */
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of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
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/* Register gate clocks */
|
||||
of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
|
||||
|
||||
/* Protect the clocks that needs to stay on */
|
||||
for (i = 0; i < nclocks; i++) {
|
||||
struct clk *clk = clk_get(NULL, clocks[i]);
|
||||
@ -1350,7 +1175,6 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
|
||||
|
||||
static const char *sun4i_a10_critical_clocks[] __initdata = {
|
||||
"pll5_ddr",
|
||||
"ahb_sdram",
|
||||
};
|
||||
|
||||
static void __init sun4i_a10_init_clocks(struct device_node *node)
|
||||
@ -1363,7 +1187,6 @@ CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks)
|
||||
static const char *sun5i_critical_clocks[] __initdata = {
|
||||
"cpu",
|
||||
"pll5_ddr",
|
||||
"ahb_sdram",
|
||||
};
|
||||
|
||||
static void __init sun5i_init_clocks(struct device_node *node)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user