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MIPS: Add Cavium OCTEON specific register definitions to mipsregs.h

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Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney 2008-12-11 15:33:24 -08:00 committed by Ralf Baechle
parent f9bb4cf37a
commit ed918c2daf
1 changed files with 20 additions and 0 deletions
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20
arch/mips/include/asm/mipsregs.h
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@ -1000,6 +1000,26 @@ do { \
#define read_c0_ebase() __read_32bit_c0_register($15, 1)
#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
/* Cavium OCTEON (cnMIPS) */
#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
#define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
/*
* The cacheerr registers are not standardized. On OCTEON, they are
* 64 bits wide.
*/
#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
/*
* Macros to access the floating point coprocessor control registers
*/