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Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86: add X86_FEATURE_XMM4_2 definitions x86: fix cpufreq + sched_clock() regression x86: fix HPET regression in 2.6.26 versus 2.6.25, check hpet against BAR, v3 x86: do not enable TSC notifier if we don't need it x86 MCE: Fix CPU hotplug problem with multiple multicore AMD CPUs x86: fix: make PCI ECS for AMD CPUs hotplug capable x86: fix: do not run code in amd_bus.c on non-AMD CPUs
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commit
ec73adba51
@ -759,6 +759,7 @@ static struct sysdev_class mce_sysclass = {
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};
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DEFINE_PER_CPU(struct sys_device, device_mce);
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void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu) __cpuinitdata;
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/* Why are there no generic functions for this? */
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#define ACCESSOR(name, var, start) \
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@ -883,9 +884,13 @@ static int __cpuinit mce_cpu_callback(struct notifier_block *nfb,
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case CPU_ONLINE:
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case CPU_ONLINE_FROZEN:
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mce_create_device(cpu);
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if (threshold_cpu_callback)
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threshold_cpu_callback(action, cpu);
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break;
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case CPU_DEAD:
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case CPU_DEAD_FROZEN:
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if (threshold_cpu_callback)
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threshold_cpu_callback(action, cpu);
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mce_remove_device(cpu);
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break;
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}
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@ -628,6 +628,7 @@ static void threshold_remove_bank(unsigned int cpu, int bank)
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deallocate_threshold_block(cpu, bank);
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free_out:
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kobject_del(b->kobj);
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kobject_put(b->kobj);
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kfree(b);
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per_cpu(threshold_banks, cpu)[bank] = NULL;
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@ -645,14 +646,11 @@ static void threshold_remove_device(unsigned int cpu)
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}
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/* get notified when a cpu comes on/off */
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static int __cpuinit threshold_cpu_callback(struct notifier_block *nfb,
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unsigned long action, void *hcpu)
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static void __cpuinit amd_64_threshold_cpu_callback(unsigned long action,
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unsigned int cpu)
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{
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/* cpu was unsigned int to begin with */
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unsigned int cpu = (unsigned long)hcpu;
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if (cpu >= NR_CPUS)
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goto out;
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return;
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switch (action) {
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case CPU_ONLINE:
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@ -666,14 +664,8 @@ static int __cpuinit threshold_cpu_callback(struct notifier_block *nfb,
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default:
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break;
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}
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out:
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return NOTIFY_OK;
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}
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static struct notifier_block threshold_cpu_notifier __cpuinitdata = {
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.notifier_call = threshold_cpu_callback,
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};
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static __init int threshold_init_device(void)
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{
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unsigned lcpu = 0;
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@ -684,7 +676,7 @@ static __init int threshold_init_device(void)
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if (err)
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return err;
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}
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register_hotcpu_notifier(&threshold_cpu_notifier);
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threshold_cpu_callback = amd_64_threshold_cpu_callback;
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return 0;
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}
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@ -314,7 +314,7 @@ static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
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mark_tsc_unstable("cpufreq changes");
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}
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set_cyc2ns_scale(tsc_khz_ref, freq->cpu);
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set_cyc2ns_scale(tsc_khz, freq->cpu);
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return 0;
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}
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@ -325,6 +325,10 @@ static struct notifier_block time_cpufreq_notifier_block = {
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static int __init cpufreq_tsc(void)
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{
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if (!cpu_has_tsc)
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return 0;
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if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
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return 0;
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cpufreq_register_notifier(&time_cpufreq_notifier_block,
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CPUFREQ_TRANSITION_NOTIFIER);
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return 0;
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@ -1,6 +1,7 @@
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/topology.h>
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#include <linux/cpu.h>
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#include "pci.h"
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#ifdef CONFIG_X86_64
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@ -555,15 +556,17 @@ static int __init early_fill_mp_bus_info(void)
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return 0;
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}
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postcore_initcall(early_fill_mp_bus_info);
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#else /* !CONFIG_X86_64 */
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#endif
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static int __init early_fill_mp_bus_info(void) { return 0; }
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#endif /* !CONFIG_X86_64 */
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/* common 32/64 bit code */
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#define ENABLE_CF8_EXT_CFG (1ULL << 46)
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static void enable_pci_io_ecs_per_cpu(void *unused)
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static void enable_pci_io_ecs(void *unused)
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{
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u64 reg;
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rdmsrl(MSR_AMD64_NB_CFG, reg);
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@ -573,14 +576,51 @@ static void enable_pci_io_ecs_per_cpu(void *unused)
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}
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}
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static int __init enable_pci_io_ecs(void)
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static int __cpuinit amd_cpu_notify(struct notifier_block *self,
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unsigned long action, void *hcpu)
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{
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int cpu = (long)hcpu;
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switch(action) {
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case CPU_ONLINE:
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case CPU_ONLINE_FROZEN:
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smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
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break;
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default:
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block __cpuinitdata amd_cpu_notifier = {
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.notifier_call = amd_cpu_notify,
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};
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static int __init pci_io_ecs_init(void)
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{
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int cpu;
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/* assume all cpus from fam10h have IO ECS */
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if (boot_cpu_data.x86 < 0x10)
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return 0;
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on_each_cpu(enable_pci_io_ecs_per_cpu, NULL, 1);
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register_cpu_notifier(&amd_cpu_notifier);
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for_each_online_cpu(cpu)
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amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
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(void *)(long)cpu);
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pci_probe |= PCI_HAS_IO_ECS;
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return 0;
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}
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postcore_initcall(enable_pci_io_ecs);
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static int __init amd_postcore_init(void)
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{
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if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
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return 0;
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early_fill_mp_bus_info();
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pci_io_ecs_init();
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return 0;
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}
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postcore_initcall(amd_postcore_init);
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@ -31,8 +31,11 @@
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#include <linux/ioport.h>
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#include <linux/errno.h>
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#include <linux/bootmem.h>
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#include <linux/acpi.h>
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#include <asm/pat.h>
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#include <asm/hpet.h>
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#include <asm/io_apic.h>
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#include "pci.h"
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@ -77,6 +80,77 @@ pcibios_align_resource(void *data, struct resource *res,
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}
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EXPORT_SYMBOL(pcibios_align_resource);
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static int check_res_with_valid(struct pci_dev *dev, struct resource *res)
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{
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unsigned long base;
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unsigned long size;
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int i;
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base = res->start;
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size = (res->start == 0 && res->end == res->start) ? 0 :
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(res->end - res->start + 1);
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if (!base || !size)
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return 0;
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#ifdef CONFIG_HPET_TIMER
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/* for hpet */
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if (base == hpet_address && (res->flags & IORESOURCE_MEM)) {
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dev_info(&dev->dev, "BAR has HPET at %08lx-%08lx\n",
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base, base + size - 1);
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return 1;
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}
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#endif
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#ifdef CONFIG_X86_IO_APIC
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for (i = 0; i < nr_ioapics; i++) {
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unsigned long ioapic_phys = mp_ioapics[i].mp_apicaddr;
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if (base == ioapic_phys && (res->flags & IORESOURCE_MEM)) {
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dev_info(&dev->dev, "BAR has ioapic at %08lx-%08lx\n",
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base, base + size - 1);
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return 1;
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}
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}
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#endif
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#ifdef CONFIG_PCI_MMCONFIG
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for (i = 0; i < pci_mmcfg_config_num; i++) {
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unsigned long addr;
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addr = pci_mmcfg_config[i].address;
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if (base == addr && (res->flags & IORESOURCE_MEM)) {
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dev_info(&dev->dev, "BAR has MMCONFIG at %08lx-%08lx\n",
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base, base + size - 1);
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return 1;
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}
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}
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#endif
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return 0;
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}
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static int check_platform(struct pci_dev *dev, struct resource *res)
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{
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struct resource *root = NULL;
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/*
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* forcibly insert it into the
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* resource tree
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*/
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if (res->flags & IORESOURCE_MEM)
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root = &iomem_resource;
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else if (res->flags & IORESOURCE_IO)
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root = &ioport_resource;
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if (root && check_res_with_valid(dev, res)) {
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insert_resource(root, res);
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return 1;
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}
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return 0;
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}
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/*
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* Handle resources of PCI devices. If the world were perfect, we could
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* just allocate all the resource regions and do nothing more. It isn't.
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@ -128,6 +202,8 @@ static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
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pr = pci_find_parent_resource(dev, r);
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if (!r->start || !pr ||
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request_resource(pr, r) < 0) {
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if (check_platform(dev, r))
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continue;
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dev_err(&dev->dev, "BAR %d: can't "
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"allocate resource\n", idx);
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/*
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@ -171,6 +247,8 @@ static void __init pcibios_allocate_resources(int pass)
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r->flags, disabled, pass);
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pr = pci_find_parent_resource(dev, r);
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if (!pr || request_resource(pr, r) < 0) {
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if (check_platform(dev, r))
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continue;
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dev_err(&dev->dev, "BAR %d: can't "
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"allocate resource\n", idx);
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/* We'll assign a new address later */
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@ -91,6 +91,7 @@
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#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
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#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
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#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
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#define X86_FEATURE_XMM4_2 (4*32+20) /* Streaming SIMD Extensions-4.2 */
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/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
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#define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */
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@ -189,6 +190,7 @@ extern const char * const x86_power_flags[32];
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#define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES)
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#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
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#define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT)
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#define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2)
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#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
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# define cpu_has_invlpg 1
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@ -92,6 +92,7 @@ extern int mce_disabled;
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void mce_log(struct mce *m);
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DECLARE_PER_CPU(struct sys_device, device_mce);
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extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
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#ifdef CONFIG_X86_MCE_INTEL
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void mce_intel_feature_init(struct cpuinfo_x86 *c);
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