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Second Round of Renesas ARM64 Based SoC DT Updates for v5.1
* R-Car Gen3 SoC based Salvator-X, Salvator-XS and ULCB boards - Enable HS400 support for eMMC * R-Car E3 (r7a77990) SoC - Add OPPs table for cpu devices * RZ/G2E (r8a774c0) SoC - Describe TMU, CMT, SDHI devices in DT - Describe pincontrol support for SCIF2 device in DT - Add OPPs table for cpu devices * RZ/G2E (r8a774c0) based EK874 board and CAT875 sub-board, and CAT874 board - Initial support -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAlxdYfIACgkQ189kaWo3 T76PixAAnSzRxLUHssiuUZMje7PMJQiof41rO6800v3NK53z1KQe7azDuB8X2rrd uWYieSlUudRkFGVMT3hNzXHaonWucEklJAGoud2w5Ih2Vd9zOvK2Ae2dKn0Pf5aU jRKhYB2y+vUY+UT6AQO5sddHSnwb1iXY2XEqa3+obO5VxPrjCEkExiu6VYsZoIIh s5vSek/7SdifScwSAM7ZombvsFYvTZl2caCJYFeKK21sVKZfUUEq5DWfobYwiWMe P05LstjaD2FdkEgGECL4a7gWuHYF9hsSuSsJ7yy4si6BlFKASylRCQA27YvHFOle otDaStMj3vFpq5jLuGnGFIdXIDw173h5RR/g4QJbjM+eWAPn8NDelbrxq8tbMV+7 nbHjNUvc4+rcHEzlLQTfsGoYKejY+cOndefIbviflieLJKzRzRuWuqkt19NwblcR fgseBR1fTaVciLORvm17xhYWZMPDVCggaooegkKJ2+yOu626Y7bfVT+BJqds6PTo G7KwGXJb5Kj49cgeEsco/WNoOkSatYha8FwBzBZW+fWdMeBxWHMX34ycgeWyjY0c T79Ik9vIcyeRmmYFKOm/aJZZ/CRoOvLOO8u4nLtJ1bBrMnKetLVGjUIrOecFtbw0 e0oxCNiLZ7iVGsdcnMxCpmMhBV9hEVgsdhShQAfyUb6sAYdP578= =3PTZ -----END PGP SIGNATURE----- Merge tag 'renesas-arm64-dt2-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/dt Second Round of Renesas ARM64 Based SoC DT Updates for v5.1 * R-Car Gen3 SoC based Salvator-X, Salvator-XS and ULCB boards - Enable HS400 support for eMMC * R-Car E3 (r7a77990) SoC - Add OPPs table for cpu devices * RZ/G2E (r8a774c0) SoC - Describe TMU, CMT, SDHI devices in DT - Describe pincontrol support for SCIF2 device in DT - Add OPPs table for cpu devices * RZ/G2E (r8a774c0) based EK874 board and CAT875 sub-board, and CAT874 board - Initial support * tag 'renesas-arm64-dt2-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: arm64: dts: renesas: cat875: Enable PCIe support arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support arm64: dts: renesas: r8a774c0: Add TMU device nodes arm64: dts: renesas: r8a774c0: Add CMT device nodes arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices arm64: dts: renesas: r8a77990: Add OPPs table for cpu devices arm64: dts: renesas: enable HS400 on R-Car Gen3 arm64: dts: renesas: cat875: Add ethernet support arm64: dts: renesas: r8a774c0-cat874: Add uSD support arm64: dts: renesas: r8a774c0-cat874: Add pincontrol support to scif2 arm64: dts: renesas: Add Si-Linux EK874 board support arm64: dts: renesas: Add Si-Linux CAT874 board support Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
ec38fad35f
@ -1,4 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb
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dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
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dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb
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dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb
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44
arch/arm64/boot/dts/renesas/cat875.dtsi
Normal file
44
arch/arm64/boot/dts/renesas/cat875.dtsi
Normal file
@ -0,0 +1,44 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the Silicon Linux sub board for CAT874 (CAT875)
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*
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* Copyright (C) 2019 Renesas Electronics Corp.
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*/
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/ {
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model = "Silicon Linux sub board for CAT874 (CAT875)";
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aliases {
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ethernet0 = &avb;
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};
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};
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&avb {
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pinctrl-0 = <&avb_pins>;
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pinctrl-names = "default";
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renesas,no-ether-link;
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phy-handle = <&phy0>;
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phy-mode = "rgmii";
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status = "okay";
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phy0: ethernet-phy@0 {
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rxc-skew-ps = <1500>;
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reg = <0>;
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interrupt-parent = <&gpio2>;
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interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
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};
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};
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&pciec0 {
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status = "okay";
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};
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&pfc {
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avb_pins: avb {
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mux {
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groups = "avb_mii";
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function = "avb";
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};
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};
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};
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106
arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
Normal file
106
arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
Normal file
@ -0,0 +1,106 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874)
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*
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* Copyright (C) 2019 Renesas Electronics Corp.
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*/
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/dts-v1/;
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#include "r8a774c0.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Silicon Linux RZ/G2E 96board platform (CAT874)";
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compatible = "si-linux,cat874", "renesas,r8a774c0";
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aliases {
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serial0 = &scif2;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
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stdout-path = "serial0:115200n8";
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};
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0x78000000>;
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};
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vcc_sdhi0: regulator-vcc-sdhi0 {
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compatible = "regulator-fixed";
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regulator-name = "SDHI0 Vcc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-boot-on;
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};
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vccq_sdhi0: regulator-vccq-sdhi0 {
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compatible = "regulator-gpio";
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regulator-name = "SDHI0 VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
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gpios-states = <1>;
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states = <3300000 1
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1800000 0>;
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};
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};
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&extal_clk {
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clock-frequency = <48000000>;
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};
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&pcie_bus_clk {
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clock-frequency = <100000000>;
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};
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&pciec0 {
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/* Map all possible DDR as inbound ranges */
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dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
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};
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&pfc {
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scif2_pins: scif2 {
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groups = "scif2_data_a";
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function = "scif2";
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};
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sdhi0_pins: sd0 {
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groups = "sdhi0_data4", "sdhi0_ctrl";
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function = "sdhi0";
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power-source = <3300>;
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};
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sdhi0_pins_uhs: sd0_uhs {
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groups = "sdhi0_data4", "sdhi0_ctrl";
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function = "sdhi0";
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power-source = <1800>;
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};
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};
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&scif2 {
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pinctrl-0 = <&scif2_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&sdhi0 {
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pinctrl-0 = <&sdhi0_pins>;
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pinctrl-1 = <&sdhi0_pins_uhs>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <&vcc_sdhi0>;
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vqmmc-supply = <&vccq_sdhi0>;
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cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
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bus-width = <4>;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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status = "okay";
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};
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14
arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts
Normal file
14
arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts
Normal file
@ -0,0 +1,14 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the Silicon Linux RZ/G2E evaluation kit (EK874)
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*
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* Copyright (C) 2019 Renesas Electronics Corp.
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*/
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#include "r8a774c0-cat874.dts"
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#include "cat875.dtsi"
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/ {
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model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875)";
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compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0";
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};
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@ -44,6 +44,27 @@
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clock-frequency = <0>;
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};
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cluster1_opp: opp_table10 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-800000000 {
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <820000>;
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clock-latency-ns = <300000>;
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};
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <820000>;
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clock-latency-ns = <300000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <820000>;
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clock-latency-ns = <300000>;
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opp-suspend;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -55,6 +76,8 @@
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power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
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next-level-cache = <&L2_CA53>;
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enable-method = "psci";
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clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
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operating-points-v2 = <&cluster1_opp>;
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};
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a53_1: cpu@1 {
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@ -64,6 +87,8 @@
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power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
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next-level-cache = <&L2_CA53>;
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enable-method = "psci";
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clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
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operating-points-v2 = <&cluster1_opp>;
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};
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L2_CA53: cache-controller-0 {
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@ -234,6 +259,76 @@
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reg = <0 0xe6060000 0 0x508>;
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};
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cmt0: timer@e60f0000 {
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compatible = "renesas,r8a774c0-cmt0",
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"renesas,rcar-gen3-cmt0";
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reg = <0 0xe60f0000 0 0x1004>;
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 303>;
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clock-names = "fck";
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power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
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resets = <&cpg 303>;
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status = "disabled";
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};
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cmt1: timer@e6130000 {
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compatible = "renesas,r8a774c0-cmt1",
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"renesas,rcar-gen3-cmt1";
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reg = <0 0xe6130000 0 0x1004>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 302>;
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clock-names = "fck";
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power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
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resets = <&cpg 302>;
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status = "disabled";
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};
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cmt2: timer@e6140000 {
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compatible = "renesas,r8a774c0-cmt1",
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"renesas,rcar-gen3-cmt1";
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reg = <0 0xe6140000 0 0x1004>;
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interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 301>;
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clock-names = "fck";
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power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
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resets = <&cpg 301>;
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status = "disabled";
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};
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cmt3: timer@e6148000 {
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compatible = "renesas,r8a774c0-cmt1",
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"renesas,rcar-gen3-cmt1";
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reg = <0 0xe6148000 0 0x1004>;
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interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 300>;
|
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clock-names = "fck";
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power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
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resets = <&cpg 300>;
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status = "disabled";
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||||
};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a774c0-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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||||
@ -283,6 +378,71 @@
|
||||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
tmu0: timer@e61e0000 {
|
||||
compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
|
||||
reg = <0 0xe61e0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 125>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 125>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu1: timer@e6fc0000 {
|
||||
compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
|
||||
reg = <0 0xe6fc0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 124>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 124>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu2: timer@e6fd0000 {
|
||||
compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
|
||||
reg = <0 0xe6fd0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 123>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 123>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu3: timer@e6fe0000 {
|
||||
compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
|
||||
reg = <0 0xe6fe0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 122>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 122>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu4: timer@ffc00000 {
|
||||
compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
|
||||
reg = <0 0xffc00000 0 0x30>;
|
||||
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 121>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 121>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
@ -55,6 +55,27 @@
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cluster1_opp: opp_table10 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
opp-800000000 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1200000000 {
|
||||
opp-hz = /bits/ 64 <1200000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
opp-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -66,6 +87,8 @@
|
||||
power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
};
|
||||
|
||||
a53_1: cpu@1 {
|
||||
@ -75,6 +98,8 @@
|
||||
power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
};
|
||||
|
||||
L2_CA53: cache-controller-0 {
|
||||
|
||||
@ -764,6 +764,7 @@
|
||||
vqmmc-supply = <®_1p8v>;
|
||||
bus-width = <8>;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
non-removable;
|
||||
fixed-emmc-driver-type = <1>;
|
||||
status = "okay";
|
||||
|
||||
@ -463,6 +463,7 @@
|
||||
vqmmc-supply = <®_1p8v>;
|
||||
bus-width = <8>;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user