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ASoC: rockchip: i2s: add other configurable formats
simple-audio-card,bitclock-inversion = <1> : bclk falling edge taken simple-audio-card,format = "dsp_a" : pcm no delay mode simple-audio-card,format = "dsp_b" : pcm late 1 mode Signed-off-by: zhangjun <zhangjun@rock-chips.com> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -204,7 +204,21 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
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regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
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mask = I2S_TXCR_IBM_MASK;
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mask = I2S_CKR_CKP_MASK;
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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val = I2S_CKR_CKP_NEG;
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break;
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case SND_SOC_DAIFMT_IB_NF:
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val = I2S_CKR_CKP_POS;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
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mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_RIGHT_J:
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val = I2S_TXCR_IBM_RSJM;
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@ -215,13 +229,19 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
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case SND_SOC_DAIFMT_I2S:
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val = I2S_TXCR_IBM_NORMAL;
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break;
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case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */
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val = I2S_TXCR_TFS_PCM;
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break;
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case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */
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val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
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mask = I2S_RXCR_IBM_MASK;
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mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_RIGHT_J:
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val = I2S_RXCR_IBM_RSJM;
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@ -232,6 +252,12 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
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case SND_SOC_DAIFMT_I2S:
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val = I2S_RXCR_IBM_NORMAL;
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break;
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case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */
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val = I2S_RXCR_TFS_PCM;
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break;
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case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */
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val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
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break;
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default:
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return -EINVAL;
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}
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@ -41,6 +41,7 @@
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#define I2S_TXCR_TFS_SHIFT 5
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#define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT)
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#define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT)
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#define I2S_TXCR_TFS_MASK (1 << I2S_TXCR_TFS_SHIFT)
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#define I2S_TXCR_VDW_SHIFT 0
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#define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT)
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#define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT)
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@ -70,6 +71,7 @@
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#define I2S_RXCR_TFS_SHIFT 5
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#define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT)
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#define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT)
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#define I2S_RXCR_TFS_MASK (1 << I2S_RXCR_TFS_SHIFT)
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#define I2S_RXCR_VDW_SHIFT 0
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#define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT)
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#define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT)
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@ -91,6 +93,7 @@
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#define I2S_CKR_CKP_SHIFT 26
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#define I2S_CKR_CKP_NEG (0 << I2S_CKR_CKP_SHIFT)
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#define I2S_CKR_CKP_POS (1 << I2S_CKR_CKP_SHIFT)
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#define I2S_CKR_CKP_MASK (1 << I2S_CKR_CKP_SHIFT)
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#define I2S_CKR_RLP_SHIFT 25
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#define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT)
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#define I2S_CKR_RLP_OPPSITE (1 << I2S_CKR_RLP_SHIFT)
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