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phy: mvebu-cp110-comphy: Add SMC call support
Keep the exact same list of supported configurations but first try to use the firmware's implementation. If it fails, try the legacy method: Linux implementation. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> [miquel.raynal@bootlin.com: adapt the content to the mainline driver] Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Tested-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Grzegorz Jaszczyk
Kishon Vijay Abraham I
parent
d4eda9d847
commit
eb6a1fcb53
@ -57,6 +57,7 @@ config PHY_MVEBU_CP110_COMPHY
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tristate "Marvell CP110 comphy driver"
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depends on ARCH_MVEBU || COMPILE_TEST
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depends on OF
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depends on HAVE_ARM_SMCCC
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select GENERIC_PHY
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help
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This driver allows to control the comphy, an hardware block providing
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@ -5,6 +5,7 @@
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* Antoine Tenart <antoine.tenart@free-electrons.com>
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*/
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#include <linux/arm-smccc.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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@ -116,45 +117,89 @@
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#define MVEBU_COMPHY_LANES 6
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#define MVEBU_COMPHY_PORTS 3
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#define COMPHY_SIP_POWER_ON 0x82000001
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#define COMPHY_SIP_POWER_OFF 0x82000002
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#define COMPHY_FW_NOT_SUPPORTED (-1)
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/*
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* A lane is described by the following bitfields:
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* [ 1- 0]: COMPHY polarity invertion
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* [ 2- 7]: COMPHY speed
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* [ 5-11]: COMPHY port index
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* [12-16]: COMPHY mode
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* [17]: Clock source
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*/
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#define COMPHY_FW_POL_OFFSET 0
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#define COMPHY_FW_POL_MASK GENMASK(1, 0)
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#define COMPHY_FW_SPEED_OFFSET 2
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#define COMPHY_FW_SPEED_MASK GENMASK(7, 2)
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#define COMPHY_FW_SPEED_MAX COMPHY_FW_SPEED_MASK
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#define COMPHY_FW_SPEED_1250 0
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#define COMPHY_FW_SPEED_3125 2
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#define COMPHY_FW_SPEED_5000 3
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#define COMPHY_FW_SPEED_103125 6
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#define COMPHY_FW_PORT_OFFSET 8
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#define COMPHY_FW_PORT_MASK GENMASK(11, 8)
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#define COMPHY_FW_MODE_OFFSET 12
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#define COMPHY_FW_MODE_MASK GENMASK(16, 12)
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#define COMPHY_FW_PARAM_FULL(mode, port, speed, pol) \
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((((pol) << COMPHY_FW_POL_OFFSET) & COMPHY_FW_POL_MASK) | \
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(((mode) << COMPHY_FW_MODE_OFFSET) & COMPHY_FW_MODE_MASK) | \
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(((port) << COMPHY_FW_PORT_OFFSET) & COMPHY_FW_PORT_MASK) | \
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(((speed) << COMPHY_FW_SPEED_OFFSET) & COMPHY_FW_SPEED_MASK))
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#define COMPHY_FW_PARAM(mode, port) \
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COMPHY_FW_PARAM_FULL(mode, port, 0, 0)
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#define COMPHY_FW_PARAM_ETH(mode, port, speed) \
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COMPHY_FW_PARAM_FULL(mode, port, speed, 0)
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#define COMPHY_FW_MODE_SGMII 0x2 /* SGMII 1G */
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#define COMPHY_FW_MODE_HS_SGMII 0x3 /* SGMII 2.5G */
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#define COMPHY_FW_MODE_XFI 0x8 /* SFI: 0x9 (is treated like XFI) */
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struct mvebu_comphy_conf {
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enum phy_mode mode;
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int submode;
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unsigned lane;
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unsigned port;
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u32 mux;
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u32 fw_mode;
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};
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#define MVEBU_COMPHY_CONF(_lane, _port, _submode, _mux) \
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#define MVEBU_COMPHY_CONF(_lane, _port, _submode, _mux, _fw) \
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{ \
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.lane = _lane, \
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.port = _port, \
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.mode = PHY_MODE_ETHERNET, \
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.submode = _submode, \
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.mux = _mux, \
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.fw_mode = _fw, \
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}
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static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
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/* lane 0 */
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MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1),
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MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1),
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MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
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MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
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/* lane 1 */
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MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1),
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MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1),
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MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
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MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
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/* lane 2 */
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MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1),
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MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1),
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MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1),
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MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
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MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
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MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1, COMPHY_FW_MODE_XFI),
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/* lane 3 */
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MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2),
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MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2),
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MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
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MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
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/* lane 4 */
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MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2),
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MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2),
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MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2),
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MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1),
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MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
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MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
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MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2, COMPHY_FW_MODE_XFI),
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MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
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/* lane 5 */
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MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1),
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MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1),
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MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
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MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
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};
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struct mvebu_comphy_priv {
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@ -164,6 +209,7 @@ struct mvebu_comphy_priv {
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struct clk *mg_domain_clk;
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struct clk *mg_core_clk;
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struct clk *axi_clk;
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unsigned long cp_phys;
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};
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struct mvebu_comphy_lane {
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@ -174,8 +220,18 @@ struct mvebu_comphy_lane {
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int port;
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};
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static int mvebu_comphy_get_mux(int lane, int port,
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enum phy_mode mode, int submode)
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static int mvebu_comphy_smc(unsigned long function, unsigned long phys,
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unsigned long lane, unsigned long mode)
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{
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struct arm_smccc_res res;
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arm_smccc_smc(function, phys, lane, mode, 0, 0, 0, 0, &res);
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return res.a0;
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}
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static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port,
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enum phy_mode mode, int submode)
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{
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int i, n = ARRAY_SIZE(mvebu_comphy_cp110_modes);
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@ -194,7 +250,22 @@ static int mvebu_comphy_get_mux(int lane, int port,
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if (i == n)
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return -EINVAL;
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return mvebu_comphy_cp110_modes[i].mux;
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if (fw_mode)
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return mvebu_comphy_cp110_modes[i].fw_mode;
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else
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return mvebu_comphy_cp110_modes[i].mux;
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}
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static inline int mvebu_comphy_get_mux(int lane, int port,
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enum phy_mode mode, int submode)
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{
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return mvebu_comphy_get_mode(false, lane, port, mode, submode);
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}
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static inline int mvebu_comphy_get_fw_mode(int lane, int port,
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enum phy_mode mode, int submode)
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{
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return mvebu_comphy_get_mode(true, lane, port, mode, submode);
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}
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static void mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane)
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@ -480,7 +551,7 @@ static int mvebu_comphy_set_mode_10gkr(struct phy *phy)
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return mvebu_comphy_init_plls(lane);
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}
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static int mvebu_comphy_power_on(struct phy *phy)
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static int mvebu_comphy_power_on_legacy(struct phy *phy)
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{
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struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
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struct mvebu_comphy_priv *priv = lane->priv;
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@ -521,6 +592,68 @@ static int mvebu_comphy_power_on(struct phy *phy)
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return ret;
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}
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static int mvebu_comphy_power_on(struct phy *phy)
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{
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struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
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struct mvebu_comphy_priv *priv = lane->priv;
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int fw_mode, fw_speed;
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u32 fw_param = 0;
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int ret;
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fw_mode = mvebu_comphy_get_fw_mode(lane->id, lane->port,
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lane->mode, lane->submode);
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if (fw_mode < 0)
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goto try_legacy;
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/* Try SMC flow first */
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switch (lane->mode) {
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case PHY_MODE_ETHERNET:
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switch (lane->submode) {
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case PHY_INTERFACE_MODE_SGMII:
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dev_dbg(priv->dev, "set lane %d to 1000BASE-X mode\n",
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lane->id);
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fw_speed = COMPHY_FW_SPEED_1250;
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break;
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case PHY_INTERFACE_MODE_2500BASEX:
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dev_dbg(priv->dev, "set lane %d to 2500BASE-X mode\n",
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lane->id);
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fw_speed = COMPHY_FW_SPEED_3125;
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break;
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case PHY_INTERFACE_MODE_10GKR:
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dev_dbg(priv->dev, "set lane %d to 10G-KR mode\n",
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lane->id);
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fw_speed = COMPHY_FW_SPEED_103125;
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break;
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default:
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dev_err(priv->dev, "unsupported Ethernet mode (%d)\n",
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lane->submode);
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return -ENOTSUPP;
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}
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fw_param = COMPHY_FW_PARAM_ETH(fw_mode, lane->port, fw_speed);
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break;
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default:
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dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode);
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return -ENOTSUPP;
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}
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ret = mvebu_comphy_smc(COMPHY_SIP_POWER_ON, priv->cp_phys, lane->id,
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fw_param);
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if (!ret)
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return ret;
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if (ret == COMPHY_FW_NOT_SUPPORTED)
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dev_err(priv->dev,
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"unsupported SMC call, try updating your firmware\n");
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dev_warn(priv->dev,
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"Firmware could not configure PHY %d with mode %d (ret: %d), trying legacy method\n",
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lane->id, lane->mode, ret);
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try_legacy:
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/* Fallback to Linux's implementation */
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return mvebu_comphy_power_on_legacy(phy);
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}
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static int mvebu_comphy_set_mode(struct phy *phy,
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enum phy_mode mode, int submode)
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{
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@ -532,7 +665,7 @@ static int mvebu_comphy_set_mode(struct phy *phy,
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if (submode == PHY_INTERFACE_MODE_1000BASEX)
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submode = PHY_INTERFACE_MODE_SGMII;
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if (mvebu_comphy_get_mux(lane->id, lane->port, mode, submode) < 0)
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if (mvebu_comphy_get_fw_mode(lane->id, lane->port, mode, submode) < 0)
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return -EINVAL;
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lane->mode = mode;
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@ -540,7 +673,7 @@ static int mvebu_comphy_set_mode(struct phy *phy,
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return 0;
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}
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static int mvebu_comphy_power_off(struct phy *phy)
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static int mvebu_comphy_power_off_legacy(struct phy *phy)
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{
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struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
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struct mvebu_comphy_priv *priv = lane->priv;
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@ -563,6 +696,21 @@ static int mvebu_comphy_power_off(struct phy *phy)
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return 0;
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}
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static int mvebu_comphy_power_off(struct phy *phy)
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{
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struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
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struct mvebu_comphy_priv *priv = lane->priv;
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int ret;
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ret = mvebu_comphy_smc(COMPHY_SIP_POWER_OFF, priv->cp_phys,
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lane->id, 0);
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if (!ret)
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return ret;
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/* Fallback to Linux's implementation */
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return mvebu_comphy_power_off_legacy(phy);
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}
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static const struct phy_ops mvebu_comphy_ops = {
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.power_on = mvebu_comphy_power_on,
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.power_off = mvebu_comphy_power_off,
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@ -682,6 +830,12 @@ static int mvebu_comphy_probe(struct platform_device *pdev)
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dev_warn(&pdev->dev, "cannot initialize clocks\n");
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}
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/*
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* Hack to retrieve a physical offset relative to this CP that will be
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* given to the firmware
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*/
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priv->cp_phys = res->start;
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for_each_available_child_of_node(pdev->dev.of_node, child) {
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struct mvebu_comphy_lane *lane;
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struct phy *phy;
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