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arm64: dts: qcom: x1e80100: Describe the PCIe 6a resources

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On both the CRD and QCP, on PCIe 6a sits the NVMe. Add the 3.3V
gpio-controlled regulator and the clkreq, perst and wake gpios as
resources for the PCIe 6a.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240530-x1e80100-dts-pcie6a-v1-3-ee17a9939ba5@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Abel Vesa 2024-05-30 18:43:41 +03:00 committed by Bjorn Andersson
parent 87042003f6
commit eb57cbe730
2 changed files with 104 additions and 0 deletions
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52
arch/arm64/boot/dts/qcom/x1e80100-crd.dts
View File

@ -164,6 +164,20 @@
regulator-always-on;
regulator-boot-on;
};
vreg_nvme: regulator-nvme {
compatible = "regulator-fixed";
regulator-name = "VREG_NVME_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&nvme_reg_en>;
};
};
&apps_rsc {
@ -646,6 +660,14 @@
};
&pcie6a {
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-names = "default";
pinctrl-0 = <&pcie6a_default>;
status = "okay";
};
@ -795,6 +817,36 @@
bias-disable;
};
nvme_reg_en: nvme-reg-en-state {
pins = "gpio18";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
pcie6a_default: pcie2a-default-state {
clkreq-n-pins {
pins = "gpio153";
function = "pcie6a_clk";
drive-strength = <2>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio152";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
wake-n-pins {
pins = "gpio154";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
tpad_default: tpad-default-state {
pins = "gpio3";
function = "gpio";

52
arch/arm64/boot/dts/qcom/x1e80100-qcp.dts
View File

@ -50,6 +50,20 @@
regulator-always-on;
regulator-boot-on;
};
vreg_nvme: regulator-nvme {
compatible = "regulator-fixed";
regulator-name = "VREG_NVME_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&nvme_reg_en>;
};
};
&apps_rsc {
@ -457,6 +471,14 @@
};
&pcie6a {
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-names = "default";
pinctrl-0 = <&pcie6a_default>;
status = "okay";
};
@ -519,6 +541,36 @@
drive-strength = <16>;
bias-disable;
};
nvme_reg_en: nvme-reg-en-state {
pins = "gpio18";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
pcie6a_default: pcie2a-default-state {
clkreq-n-pins {
pins = "gpio153";
function = "pcie6a_clk";
drive-strength = <2>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio152";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
wake-n-pins {
pins = "gpio154";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
};
&uart21 {