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MIPS: Add some missing guest CP0 accessors & defs
Add some missing guest accessors and register field definitions for KVM for MIPS VZ to make use of. Guest CP0_LLAddr register accessors and definitions for the LLB field allow KVM to clear the guest LLB to cancel in-progress LL/SC atomics on restore, and to emulate accesses by the guest to the CP0_LLAddr register. Bitwise modifiers and definitions for the guest CP0_Wired and CP0_Config1 registers allow KVM to modify fields within the CP0_Wired and CP0_Config1 registers. Finally a definition for the CP0_Config5.SBRI bit allows KVM to initialise and allow modification of the guest version of the SBRI bit. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org
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@ -219,8 +219,10 @@
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/*
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* Wired register bits
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*/
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#define MIPSR6_WIRED_LIMIT (_ULCAST_(0xffff) << 16)
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#define MIPSR6_WIRED_WIRED (_ULCAST_(0xffff) << 0)
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#define MIPSR6_WIRED_LIMIT_SHIFT 16
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#define MIPSR6_WIRED_LIMIT (_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
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#define MIPSR6_WIRED_WIRED_SHIFT 0
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#define MIPSR6_WIRED_WIRED (_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
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/*
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* Values used for computation of new tlb entries
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@ -647,6 +649,7 @@
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#define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
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#define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
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#define MIPS_CONF5_VP (_ULCAST_(1) << 7)
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#define MIPS_CONF5_SBRI (_ULCAST_(1) << 6)
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#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
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#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
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#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
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@ -742,6 +745,10 @@
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#define MIPS_CMGCRB_BASE 11
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#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
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/* LLAddr bit definitions */
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#define MIPS_LLADDR_LLB_SHIFT 0
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#define MIPS_LLADDR_LLB (_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
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/*
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* Bits in the MIPS32 Memory Segmentation registers.
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*/
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@ -2018,6 +2025,9 @@ do { \
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#define write_gc0_config6(val) __write_32bit_gc0_register(16, 6, val)
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#define write_gc0_config7(val) __write_32bit_gc0_register(16, 7, val)
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#define read_gc0_lladdr() __read_ulong_gc0_register(17, 0)
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#define write_gc0_lladdr(val) __write_ulong_gc0_register(17, 0, val)
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#define read_gc0_watchlo0() __read_ulong_gc0_register(18, 0)
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#define read_gc0_watchlo1() __read_ulong_gc0_register(18, 1)
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#define read_gc0_watchlo2() __read_ulong_gc0_register(18, 2)
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@ -2702,9 +2712,11 @@ __BUILD_SET_C0(brcm_mode)
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*/
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#define __BUILD_SET_GC0(name) __BUILD_SET_COMMON(gc0_##name)
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__BUILD_SET_GC0(wired)
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__BUILD_SET_GC0(status)
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__BUILD_SET_GC0(cause)
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__BUILD_SET_GC0(ebase)
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__BUILD_SET_GC0(config1)
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/*
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* Return low 10 bits of ebase.
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