Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-12-13 14:43:03 +00:00
Code Issues Packages Projects Releases Wiki Activity

ARM: dts: exynos: Add missing CPU frequencies for Exynos5422/5800

Browse Source 
Add missing 2.0GHz, 1.9GHz & 1.8GHz OPPs (for A15 cores) and 1.4GHz
OPP (for A7 cores).  Also update common Odroid-XU3 Lite/XU3/XU4
thermal cooling maps to account for new OPPs.

Since some new OPPs are not available on all Exynos5422/5800 boards
modify dts files for Odroid XU3 Lite (limited to 1.8 GHz / 1.3 GHz) &
Peach Pi (limited to 2.0 GHz / 1.3 GHz) accordingly.

This patch uses maximum voltages for new OPPs. This is a temporary
solution till proper Exynos ASV support is added.

Also while at it fix the number of cooling down steps for big cores
(should be 11 instead of 12 on Odroid XU3 Lite and 14 on XU3/XU4).

Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
[mszyprow: rebased onto v5.5-rc1 and adapted to recent dts changes,
 fixed removal of the 1.4GHz OPP for A7s on Peach-Pi]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Bartlomiej Zolnierkiewicz 2019-12-10 12:40:27 +01:00 committed by Krzysztof Kozlowski
parent 6c43b5d396
commit eaffc4de16
5 changed files with 158 additions and 71 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

64
arch/arm/boot/dts/exynos5422-odroidhc1.dts
View File

@ -72,14 +72,14 @@
*/
map1 {
trip = <&cpu0_alert1>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};
@ -116,14 +116,14 @@
};
map1 {
trip = <&cpu1_alert1>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};
@ -160,14 +160,14 @@
};
map1 {
trip = <&cpu2_alert1>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};
@ -204,14 +204,14 @@
};
map1 {
trip = <&cpu3_alert1>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};

78
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
View File

@ -107,7 +107,7 @@
/*
* When reaching cpu0_alert3, reduce CPU
* by 2 steps. On Exynos5422/5800 that would
* be: 1600 MHz and 1100 MHz.
* (usually) be: 1800 MHz and 1200 MHz.
*/
map3 {
trip = <&cpu0_alert3>;
@ -122,19 +122,19 @@
};
/*
* When reaching cpu0_alert4, reduce CPU
* further, down to 600 MHz (12 steps for big,
* 7 steps for LITTLE).
* further, down to 600 MHz (14 steps for big,
* 8 steps for LITTLE).
*/
map4 {
cpu0_cooling_map4: map4 {
trip = <&cpu0_alert4>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};
@ -198,16 +198,16 @@
<&cpu6 0 2>,
<&cpu7 0 2>;
};
map4 {
cpu1_cooling_map4: map4 {
trip = <&cpu1_alert4>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};
@ -271,16 +271,16 @@
<&cpu6 0 2>,
<&cpu7 0 2>;
};
map4 {
cpu2_cooling_map4: map4 {
trip = <&cpu2_alert4>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};
@ -344,16 +344,16 @@
<&cpu6 0 2>,
<&cpu7 0 2>;
};
map4 {
cpu3_cooling_map4: map4 {
trip = <&cpu3_alert4>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};

58
arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
View File

@ -30,6 +30,64 @@
samsung,asv-bin = <2>;
};
/*
* Odroid XU3-Lite board uses SoC revision with lower maximum frequencies
* than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores.
* Therefore we need to update OPPs tables and thermal maps accordingly.
*/
&cluster_a15_opp_table {
/delete-node/opp-2000000000;
/delete-node/opp-1900000000;
};
&cluster_a7_opp_table {
/delete-node/opp-1400000000;
};
&cpu0_cooling_map4 {
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
};
&cpu1_cooling_map4 {
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
};
&cpu2_cooling_map4 {
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
};
&cpu3_cooling_map4 {
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
};
&pwm {
/*
* PWM 0 -- fan

9
arch/arm/boot/dts/exynos5800-peach-pi.dts
View File

@ -156,6 +156,15 @@
assigned-clock-parents = <&clock CLK_MAU_EPLL>;
};
/*
* Peach Pi board uses SoC revision with lower maximum frequency for A7 cores
* (1.3 GHz instead of 1.4 GHz) than Odroid XU3/XU4 boards. Thus we need to
* update A7 OPPs table accordingly.
*/
&cluster_a7_opp_table {
/delete-node/opp-1400000000;
};
&cpu0 {
cpu-supply = <&buck2_reg>;
};

20
arch/arm/boot/dts/exynos5800.dtsi
View File

@ -21,6 +21,21 @@
};
&cluster_a15_opp_table {
opp-2000000000 {
opp-hz = /bits/ 64 <2000000000>;
opp-microvolt = <1312500>;
clock-latency-ns = <140000>;
};
opp-1900000000 {
opp-hz = /bits/ 64 <1900000000>;
opp-microvolt = <1262500>;
clock-latency-ns = <140000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1237500>;
clock-latency-ns = <140000>;
};
opp-1700000000 {
opp-microvolt = <1250000 1250000 1500000>;
};
@ -82,6 +97,11 @@
};
&cluster_a7_opp_table {
opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-microvolt = <1275000>;
clock-latency-ns = <140000>;
};
opp-1300000000 {
opp-microvolt = <1250000>;
};