Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-11-25 13:41:51 +00:00
Code Issues Packages Projects Releases Wiki Activity

clk: qcom: mmcc-msm8996: Migrate gfx3d clock to clk_rcg2_gfx3d

Browse Source 
In the previous commit ("clk: qcom: rcg2: Stop hardcoding gfx3d pingpong
parent numbers") the gfx3d ping-pong ops (clk_gfx3d_ops) were
generalized in order to be able to reuse the same ops for more than just
one clock for one SoC: follow the change here in the MSM8996 MMCC.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210113183817.447866-7-angelogioacchino.delregno@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
AngeloGioacchino Del Regno 2021-01-13 19:38:14 +01:00 committed by Stephen Boyd
parent 7cbb78a99d
commit eaf87e5661
1 changed files with 18 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
drivers/clk/qcom/mmcc-msm8996.c
View File

@ -528,16 +528,23 @@ static struct clk_rcg2 maxi_clk_src = {
},
};
static struct clk_rcg2 gfx3d_clk_src = {
.cmd_rcgr = 0x4000,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src",
.parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0,
.num_parents = 6,
.ops = &clk_gfx3d_ops,
.flags = CLK_SET_RATE_PARENT,
static struct clk_rcg2_gfx3d gfx3d_clk_src = {
.rcg = {
.cmd_rcgr = 0x4000,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src",
.parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0,
.num_parents = 6,
.ops = &clk_gfx3d_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
.hws = (struct clk_hw*[]) {
&mmpll9.clkr.hw,
&mmpll2.clkr.hw,
&mmpll8.clkr.hw
},
};
@ -3089,7 +3096,7 @@ static struct clk_regmap *mmcc_msm8996_clocks[] = {
[AHB_CLK_SRC] = &ahb_clk_src.clkr,
[AXI_CLK_SRC] = &axi_clk_src.clkr,
[MAXI_CLK_SRC] = &maxi_clk_src.clkr,
[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
[GFX3D_CLK_SRC] = &gfx3d_clk_src.rcg.clkr,
[RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
[ISENSE_CLK_SRC] = &isense_clk_src.clkr,
[RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,