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Merge branches 'clk-ingenic-fixes', 'clk-max9485', 'clk-pxa-32k-pll', 'clk-aspeed' and 'clk-imx6sll-gpio' into clk-next
* clk-ingenic-fixes: : - Ingenic i2s bit update and allow UDC clk to gate clk: ingenic: Add missing flag for UDC clock clk: ingenic: Fix incorrect data for the i2s clock * clk-max9485: : - Maxim 9485 Programmable Clock Generator clk: Add driver for MAX9485 dts: clk: add devicetree bindings for MAX9485 * clk-pxa-32k-pll: : - Expose 32 kHz PLL on PXA SoCs clk: pxa: export 32kHz PLL * clk-aspeed: : - Fix name of aspeed SDC clk define to have only one 'CLK' clk: aspeed: Fix SDCLK name * clk-imx6sll-gpio: : - imx6sll GPIO clk gate support clk: imx6sll: add GPIO LPCGs
This commit is contained in:
Stephen Boyd
commit
ea4f7872c7
59
Documentation/devicetree/bindings/clock/maxim,max9485.txt
Normal file
59
Documentation/devicetree/bindings/clock/maxim,max9485.txt
Normal file
@ -0,0 +1,59 @@
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Devicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator
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This device exposes 4 clocks in total:
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- MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
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- MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete
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frequencies
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- MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
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MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set
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requests.
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Required properties:
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- compatible: "maxim,max9485"
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- clocks: Input clock, must provice 27.000 MHz
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- clock-names: Must be set to "xclk"
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- #clock-cells: From common clock binding; shall be set to 1
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Optional properties:
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- reset-gpios: GPIO descriptor connected to the #RESET input pin
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- vdd-supply: A regulator node for Vdd
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- clock-output-names: Name of output clocks, as defined in common clock
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bindings
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If not explicitly set, the output names are "mclkout", "clkout", "clkout1"
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and "clkout2".
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Clocks are defined as preprocessor macros in the dt-binding header.
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Example:
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#include <dt-bindings/clock/maxim,max9485.h>
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xo-27mhz: xo-27mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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};
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&i2c0 {
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max9485: audio-clock@63 {
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reg = <0x63>;
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compatible = "maxim,max9485";
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clock-names = "xclk";
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clocks = <&xo-27mhz>;
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reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
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vdd-supply = <&3v3-reg>;
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#clock-cells = <1>;
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};
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};
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// Clock consumer node
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foo@0 {
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compatible = "bar,foo";
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/* ... */
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clock-names = "foo-input-clk";
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clocks = <&max9485 MAX9485_CLKOUT1>;
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};
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@ -45,6 +45,12 @@ config COMMON_CLK_MAX77686
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This driver supports Maxim 77620/77686/77802 crystal oscillator
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clock.
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config COMMON_CLK_MAX9485
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tristate "Maxim 9485 Programmable Clock Generator"
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depends on I2C
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help
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This driver supports Maxim 9485 Programmable Audio Clock Generator
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config COMMON_CLK_RK808
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tristate "Clock driver for RK805/RK808/RK818"
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depends on MFD_RK808
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@ -31,6 +31,7 @@ obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o
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obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
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obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
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obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
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obj-$(CONFIG_COMMON_CLK_MAX9485) += clk-max9485.o
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obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
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obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
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obj-$(CONFIG_ARCH_NPCM7XX) += clk-npcm7xx.o
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@ -109,7 +109,7 @@ static const struct aspeed_gate_data aspeed_gates[] = {
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[ASPEED_CLK_GATE_RSACLK] = { 24, -1, "rsaclk-gate", NULL, 0 }, /* RSA */
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[ASPEED_CLK_GATE_UART3CLK] = { 25, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
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[ASPEED_CLK_GATE_UART4CLK] = { 26, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
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[ASPEED_CLK_GATE_SDCLKCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
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[ASPEED_CLK_GATE_SDCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
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[ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
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};
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387
drivers/clk/clk-max9485.c
Normal file
387
drivers/clk/clk-max9485.c
Normal file
@ -0,0 +1,387 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/gpio/consumer.h>
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#include <linux/i2c.h>
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#include <linux/regulator/consumer.h>
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#include <dt-bindings/clock/maxim,max9485.h>
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#define MAX9485_NUM_CLKS 4
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/* This chip has only one register of 8 bit width. */
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#define MAX9485_FS_12KHZ (0 << 0)
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#define MAX9485_FS_32KHZ (1 << 0)
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#define MAX9485_FS_44_1KHZ (2 << 0)
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#define MAX9485_FS_48KHZ (3 << 0)
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#define MAX9485_SCALE_256 (0 << 2)
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#define MAX9485_SCALE_384 (1 << 2)
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#define MAX9485_SCALE_768 (2 << 2)
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#define MAX9485_DOUBLE BIT(4)
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#define MAX9485_CLKOUT1_ENABLE BIT(5)
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#define MAX9485_CLKOUT2_ENABLE BIT(6)
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#define MAX9485_MCLK_ENABLE BIT(7)
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#define MAX9485_FREQ_MASK 0x1f
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struct max9485_rate {
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unsigned long out;
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u8 reg_value;
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};
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/*
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* Ordered by frequency. For frequency the hardware can generate with
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* multiple settings, the one with lowest jitter is listed first.
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*/
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static const struct max9485_rate max9485_rates[] = {
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{ 3072000, MAX9485_FS_12KHZ | MAX9485_SCALE_256 },
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{ 4608000, MAX9485_FS_12KHZ | MAX9485_SCALE_384 },
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{ 8192000, MAX9485_FS_32KHZ | MAX9485_SCALE_256 },
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{ 9126000, MAX9485_FS_12KHZ | MAX9485_SCALE_768 },
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{ 11289600, MAX9485_FS_44_1KHZ | MAX9485_SCALE_256 },
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{ 12288000, MAX9485_FS_48KHZ | MAX9485_SCALE_256 },
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{ 12288000, MAX9485_FS_32KHZ | MAX9485_SCALE_384 },
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{ 16384000, MAX9485_FS_32KHZ | MAX9485_SCALE_256 | MAX9485_DOUBLE },
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{ 16934400, MAX9485_FS_44_1KHZ | MAX9485_SCALE_384 },
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{ 18384000, MAX9485_FS_48KHZ | MAX9485_SCALE_384 },
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{ 22579200, MAX9485_FS_44_1KHZ | MAX9485_SCALE_256 | MAX9485_DOUBLE },
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{ 24576000, MAX9485_FS_48KHZ | MAX9485_SCALE_256 | MAX9485_DOUBLE },
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{ 24576000, MAX9485_FS_32KHZ | MAX9485_SCALE_384 | MAX9485_DOUBLE },
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{ 24576000, MAX9485_FS_32KHZ | MAX9485_SCALE_768 },
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{ 33868800, MAX9485_FS_44_1KHZ | MAX9485_SCALE_384 | MAX9485_DOUBLE },
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{ 33868800, MAX9485_FS_44_1KHZ | MAX9485_SCALE_768 },
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{ 36864000, MAX9485_FS_48KHZ | MAX9485_SCALE_384 | MAX9485_DOUBLE },
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{ 36864000, MAX9485_FS_48KHZ | MAX9485_SCALE_768 },
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{ 49152000, MAX9485_FS_32KHZ | MAX9485_SCALE_768 | MAX9485_DOUBLE },
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{ 67737600, MAX9485_FS_44_1KHZ | MAX9485_SCALE_768 | MAX9485_DOUBLE },
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{ 73728000, MAX9485_FS_48KHZ | MAX9485_SCALE_768 | MAX9485_DOUBLE },
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{ } /* sentinel */
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};
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struct max9485_driver_data;
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struct max9485_clk_hw {
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struct clk_hw hw;
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struct clk_init_data init;
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u8 enable_bit;
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struct max9485_driver_data *drvdata;
|
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};
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struct max9485_driver_data {
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struct clk *xclk;
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struct i2c_client *client;
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u8 reg_value;
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struct regulator *supply;
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struct gpio_desc *reset_gpio;
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struct max9485_clk_hw hw[MAX9485_NUM_CLKS];
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};
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static inline struct max9485_clk_hw *to_max9485_clk(struct clk_hw *hw)
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{
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return container_of(hw, struct max9485_clk_hw, hw);
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}
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static int max9485_update_bits(struct max9485_driver_data *drvdata,
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u8 mask, u8 value)
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{
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int ret;
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||||
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drvdata->reg_value &= ~mask;
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drvdata->reg_value |= value;
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dev_dbg(&drvdata->client->dev,
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"updating mask 0x%02x value 0x%02x -> 0x%02x\n",
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mask, value, drvdata->reg_value);
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ret = i2c_master_send(drvdata->client,
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&drvdata->reg_value,
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sizeof(drvdata->reg_value));
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return ret < 0 ? ret : 0;
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}
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static int max9485_clk_prepare(struct clk_hw *hw)
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{
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struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
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return max9485_update_bits(clk_hw->drvdata,
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clk_hw->enable_bit,
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clk_hw->enable_bit);
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}
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static void max9485_clk_unprepare(struct clk_hw *hw)
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{
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struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
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max9485_update_bits(clk_hw->drvdata, clk_hw->enable_bit, 0);
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}
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/*
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* CLKOUT - configurable clock output
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*/
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static int max9485_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
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const struct max9485_rate *entry;
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for (entry = max9485_rates; entry->out != 0; entry++)
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if (entry->out == rate)
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break;
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if (entry->out == 0)
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return -EINVAL;
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return max9485_update_bits(clk_hw->drvdata,
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MAX9485_FREQ_MASK,
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entry->reg_value);
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}
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static unsigned long max9485_clkout_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
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struct max9485_driver_data *drvdata = clk_hw->drvdata;
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u8 val = drvdata->reg_value & MAX9485_FREQ_MASK;
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const struct max9485_rate *entry;
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for (entry = max9485_rates; entry->out != 0; entry++)
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if (val == entry->reg_value)
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return entry->out;
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return 0;
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}
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static long max9485_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
|
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unsigned long *parent_rate)
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{
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const struct max9485_rate *curr, *prev = NULL;
|
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|
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for (curr = max9485_rates; curr->out != 0; curr++) {
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/* Exact matches */
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if (curr->out == rate)
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return rate;
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||||
|
||||
/*
|
||||
* Find the first entry that has a frequency higher than the
|
||||
* requested one.
|
||||
*/
|
||||
if (curr->out > rate) {
|
||||
unsigned int mid;
|
||||
|
||||
/*
|
||||
* If this is the first entry, clamp the value to the
|
||||
* lowest possible frequency.
|
||||
*/
|
||||
if (!prev)
|
||||
return curr->out;
|
||||
|
||||
/*
|
||||
* Otherwise, determine whether the previous entry or
|
||||
* current one is closer.
|
||||
*/
|
||||
mid = prev->out + ((curr->out - prev->out) / 2);
|
||||
|
||||
return (mid > rate) ? prev->out : curr->out;
|
||||
}
|
||||
|
||||
prev = curr;
|
||||
}
|
||||
|
||||
/* If the last entry was still too high, clamp the value */
|
||||
return prev->out;
|
||||
}
|
||||
|
||||
struct max9485_clk {
|
||||
const char *name;
|
||||
int parent_index;
|
||||
const struct clk_ops ops;
|
||||
u8 enable_bit;
|
||||
};
|
||||
|
||||
static const struct max9485_clk max9485_clks[MAX9485_NUM_CLKS] = {
|
||||
[MAX9485_MCLKOUT] = {
|
||||
.name = "mclkout",
|
||||
.parent_index = -1,
|
||||
.enable_bit = MAX9485_MCLK_ENABLE,
|
||||
.ops = {
|
||||
.prepare = max9485_clk_prepare,
|
||||
.unprepare = max9485_clk_unprepare,
|
||||
},
|
||||
},
|
||||
[MAX9485_CLKOUT] = {
|
||||
.name = "clkout",
|
||||
.parent_index = -1,
|
||||
.ops = {
|
||||
.set_rate = max9485_clkout_set_rate,
|
||||
.round_rate = max9485_clkout_round_rate,
|
||||
.recalc_rate = max9485_clkout_recalc_rate,
|
||||
},
|
||||
},
|
||||
[MAX9485_CLKOUT1] = {
|
||||
.name = "clkout1",
|
||||
.parent_index = MAX9485_CLKOUT,
|
||||
.enable_bit = MAX9485_CLKOUT1_ENABLE,
|
||||
.ops = {
|
||||
.prepare = max9485_clk_prepare,
|
||||
.unprepare = max9485_clk_unprepare,
|
||||
},
|
||||
},
|
||||
[MAX9485_CLKOUT2] = {
|
||||
.name = "clkout2",
|
||||
.parent_index = MAX9485_CLKOUT,
|
||||
.enable_bit = MAX9485_CLKOUT2_ENABLE,
|
||||
.ops = {
|
||||
.prepare = max9485_clk_prepare,
|
||||
.unprepare = max9485_clk_unprepare,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_hw *
|
||||
max9485_of_clk_get(struct of_phandle_args *clkspec, void *data)
|
||||
{
|
||||
struct max9485_driver_data *drvdata = data;
|
||||
unsigned int idx = clkspec->args[0];
|
||||
|
||||
return &drvdata->hw[idx].hw;
|
||||
}
|
||||
|
||||
static int max9485_i2c_probe(struct i2c_client *client,
|
||||
const struct i2c_device_id *id)
|
||||
{
|
||||
struct max9485_driver_data *drvdata;
|
||||
struct device *dev = &client->dev;
|
||||
const char *xclk_name;
|
||||
int i, ret;
|
||||
|
||||
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
|
||||
if (!drvdata)
|
||||
return -ENOMEM;
|
||||
|
||||
drvdata->xclk = devm_clk_get(dev, "xclk");
|
||||
if (IS_ERR(drvdata->xclk))
|
||||
return PTR_ERR(drvdata->xclk);
|
||||
|
||||
xclk_name = __clk_get_name(drvdata->xclk);
|
||||
|
||||
drvdata->supply = devm_regulator_get(dev, "vdd");
|
||||
if (IS_ERR(drvdata->supply))
|
||||
return PTR_ERR(drvdata->supply);
|
||||
|
||||
ret = regulator_enable(drvdata->supply);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
drvdata->reset_gpio =
|
||||
devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
|
||||
if (IS_ERR(drvdata->reset_gpio))
|
||||
return PTR_ERR(drvdata->reset_gpio);
|
||||
|
||||
i2c_set_clientdata(client, drvdata);
|
||||
drvdata->client = client;
|
||||
|
||||
ret = i2c_master_recv(drvdata->client, &drvdata->reg_value,
|
||||
sizeof(drvdata->reg_value));
|
||||
if (ret < 0) {
|
||||
dev_warn(dev, "Unable to read device register: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
for (i = 0; i < MAX9485_NUM_CLKS; i++) {
|
||||
int parent_index = max9485_clks[i].parent_index;
|
||||
const char *name;
|
||||
|
||||
if (of_property_read_string_index(dev->of_node,
|
||||
"clock-output-names",
|
||||
i, &name) == 0) {
|
||||
drvdata->hw[i].init.name = name;
|
||||
} else {
|
||||
drvdata->hw[i].init.name = max9485_clks[i].name;
|
||||
}
|
||||
|
||||
drvdata->hw[i].init.ops = &max9485_clks[i].ops;
|
||||
drvdata->hw[i].init.num_parents = 1;
|
||||
drvdata->hw[i].init.flags = 0;
|
||||
|
||||
if (parent_index > 0) {
|
||||
drvdata->hw[i].init.parent_names =
|
||||
&drvdata->hw[parent_index].init.name;
|
||||
drvdata->hw[i].init.flags |= CLK_SET_RATE_PARENT;
|
||||
} else {
|
||||
drvdata->hw[i].init.parent_names = &xclk_name;
|
||||
}
|
||||
|
||||
drvdata->hw[i].enable_bit = max9485_clks[i].enable_bit;
|
||||
drvdata->hw[i].hw.init = &drvdata->hw[i].init;
|
||||
drvdata->hw[i].drvdata = drvdata;
|
||||
|
||||
ret = devm_clk_hw_register(dev, &drvdata->hw[i].hw);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return devm_of_clk_add_hw_provider(dev, max9485_of_clk_get, drvdata);
|
||||
}
|
||||
|
||||
static int __maybe_unused max9485_suspend(struct device *dev)
|
||||
{
|
||||
struct i2c_client *client = to_i2c_client(dev);
|
||||
struct max9485_driver_data *drvdata = i2c_get_clientdata(client);
|
||||
|
||||
gpiod_set_value_cansleep(drvdata->reset_gpio, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused max9485_resume(struct device *dev)
|
||||
{
|
||||
struct i2c_client *client = to_i2c_client(dev);
|
||||
struct max9485_driver_data *drvdata = i2c_get_clientdata(client);
|
||||
int ret;
|
||||
|
||||
gpiod_set_value_cansleep(drvdata->reset_gpio, 1);
|
||||
|
||||
ret = i2c_master_send(client, &drvdata->reg_value,
|
||||
sizeof(drvdata->reg_value));
|
||||
|
||||
return ret < 0 ? ret : 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops max9485_pm_ops = {
|
||||
SET_SYSTEM_SLEEP_PM_OPS(max9485_suspend, max9485_resume)
|
||||
};
|
||||
|
||||
static const struct of_device_id max9485_dt_ids[] = {
|
||||
{ .compatible = "maxim,max9485", },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, max9485_dt_ids);
|
||||
|
||||
static const struct i2c_device_id max9485_i2c_ids[] = {
|
||||
{ .name = "max9485", },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, max9485_i2c_ids);
|
||||
|
||||
static struct i2c_driver max9485_driver = {
|
||||
.driver = {
|
||||
.name = "max9485",
|
||||
.pm = &max9485_pm_ops,
|
||||
.of_match_table = max9485_dt_ids,
|
||||
},
|
||||
.probe = max9485_i2c_probe,
|
||||
.id_table = max9485_i2c_ids,
|
||||
};
|
||||
module_i2c_driver(max9485_driver);
|
||||
|
||||
MODULE_AUTHOR("Daniel Mack <daniel@zonque.org>");
|
||||
MODULE_DESCRIPTION("MAX9485 Programmable Audio Clock Generator");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@ -253,6 +253,7 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node)
|
||||
clks[IMX6SLL_CLK_DCP] = imx_clk_gate2("dcp", "ahb", base + 0x68, 10);
|
||||
clks[IMX6SLL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28);
|
||||
clks[IMX6SLL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28);
|
||||
clks[IMX6SLL_CLK_GPIO2] = imx_clk_gate2("gpio2", "ipg", base + 0x68, 30);
|
||||
|
||||
/* CCGR1 */
|
||||
clks[IMX6SLL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0);
|
||||
@ -267,13 +268,17 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node)
|
||||
clks[IMX6SLL_CLK_GPT_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22);
|
||||
clks[IMX6SLL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24);
|
||||
clks[IMX6SLL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serail", "uart_podf", base + 0x6c, 24);
|
||||
clks[IMX6SLL_CLK_GPIO1] = imx_clk_gate2("gpio1", "ipg", base + 0x6c, 26);
|
||||
clks[IMX6SLL_CLK_GPIO5] = imx_clk_gate2("gpio5", "ipg", base + 0x6c, 30);
|
||||
|
||||
/* CCGR2 */
|
||||
clks[IMX6SLL_CLK_GPIO6] = imx_clk_gate2("gpio6", "ipg", base + 0x70, 0);
|
||||
clks[IMX6SLL_CLK_CSI] = imx_clk_gate2("csi", "axi", base + 0x70, 2);
|
||||
clks[IMX6SLL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6);
|
||||
clks[IMX6SLL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8);
|
||||
clks[IMX6SLL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10);
|
||||
clks[IMX6SLL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12);
|
||||
clks[IMX6SLL_CLK_GPIO3] = imx_clk_gate2("gpio3", "ipg", base + 0x70, 26);
|
||||
clks[IMX6SLL_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "axi", base + 0x70, 28);
|
||||
clks[IMX6SLL_CLK_PXP] = imx_clk_gate2("pxp", "axi", base + 0x70, 30);
|
||||
|
||||
@ -283,6 +288,7 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node)
|
||||
clks[IMX6SLL_CLK_EPDC_AXI] = imx_clk_gate2("epdc_aclk", "axi", base + 0x74, 4);
|
||||
clks[IMX6SLL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_podf", base + 0x74, 4);
|
||||
clks[IMX6SLL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10);
|
||||
clks[IMX6SLL_CLK_GPIO4] = imx_clk_gate2("gpio4", "ipg", base + 0x74, 12);
|
||||
clks[IMX6SLL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16);
|
||||
clks[IMX6SLL_CLK_MMDC_P0_FAST] = imx_clk_gate_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL);
|
||||
clks[IMX6SLL_CLK_MMDC_P0_IPG] = imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL);
|
||||
|
||||
@ -134,7 +134,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
|
||||
"i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
|
||||
.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
|
||||
.mux = { CGU_REG_CPCCR, 31, 1 },
|
||||
.div = { CGU_REG_I2SCDR, 0, 1, 8, -1, -1, -1 },
|
||||
.div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR, 6 },
|
||||
},
|
||||
|
||||
@ -161,7 +161,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
|
||||
},
|
||||
|
||||
[JZ4740_CLK_UDC] = {
|
||||
"udc", CGU_CLK_MUX | CGU_CLK_DIV,
|
||||
"udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
|
||||
.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
|
||||
.mux = { CGU_REG_CPCCR, 29, 1 },
|
||||
.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
|
||||
|
||||
@ -292,8 +292,10 @@ static void __init pxa25x_register_plls(void)
|
||||
{
|
||||
clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL,
|
||||
CLK_GET_RATE_NOCACHE, 3686400);
|
||||
clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
|
||||
CLK_GET_RATE_NOCACHE, 32768);
|
||||
clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
|
||||
clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
|
||||
CLK_GET_RATE_NOCACHE,
|
||||
32768));
|
||||
clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
|
||||
clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz",
|
||||
0, 26, 1);
|
||||
|
||||
@ -314,9 +314,10 @@ static void __init pxa27x_register_plls(void)
|
||||
clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
|
||||
CLK_GET_RATE_NOCACHE,
|
||||
13 * MHz);
|
||||
clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
|
||||
CLK_GET_RATE_NOCACHE,
|
||||
32768 * KHz);
|
||||
clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
|
||||
clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
|
||||
CLK_GET_RATE_NOCACHE,
|
||||
32768 * KHz));
|
||||
clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
|
||||
clk_register_fixed_factor(NULL, "ppll_312mhz", "osc_13mhz", 0, 24, 1);
|
||||
}
|
||||
|
||||
@ -286,9 +286,10 @@ static void __init pxa3xx_register_plls(void)
|
||||
clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
|
||||
CLK_GET_RATE_NOCACHE,
|
||||
13 * MHz);
|
||||
clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
|
||||
CLK_GET_RATE_NOCACHE,
|
||||
32768);
|
||||
clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
|
||||
clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
|
||||
CLK_GET_RATE_NOCACHE,
|
||||
32768));
|
||||
clk_register_fixed_rate(NULL, "ring_osc_120mhz", NULL,
|
||||
CLK_GET_RATE_NOCACHE,
|
||||
120 * MHz);
|
||||
|
||||
@ -25,7 +25,7 @@
|
||||
#define ASPEED_CLK_GATE_RSACLK 19
|
||||
#define ASPEED_CLK_GATE_UART3CLK 20
|
||||
#define ASPEED_CLK_GATE_UART4CLK 21
|
||||
#define ASPEED_CLK_GATE_SDCLKCLK 22
|
||||
#define ASPEED_CLK_GATE_SDCLK 22
|
||||
#define ASPEED_CLK_GATE_LHCCLK 23
|
||||
#define ASPEED_CLK_HPLL 24
|
||||
#define ASPEED_CLK_AHB 25
|
||||
|
||||
@ -197,6 +197,13 @@
|
||||
#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171
|
||||
#define IMX6SLL_CLK_EXTERN_AUDIO 172
|
||||
|
||||
#define IMX6SLL_CLK_END 173
|
||||
#define IMX6SLL_CLK_GPIO1 173
|
||||
#define IMX6SLL_CLK_GPIO2 174
|
||||
#define IMX6SLL_CLK_GPIO3 175
|
||||
#define IMX6SLL_CLK_GPIO4 176
|
||||
#define IMX6SLL_CLK_GPIO5 177
|
||||
#define IMX6SLL_CLK_GPIO6 178
|
||||
|
||||
#define IMX6SLL_CLK_END 179
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */
|
||||
|
||||
18
include/dt-bindings/clock/maxim,max9485.h
Normal file
18
include/dt-bindings/clock/maxim,max9485.h
Normal file
@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Daniel Mack
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_MAX9485_CLK_H
|
||||
#define __DT_BINDINGS_MAX9485_CLK_H
|
||||
|
||||
#define MAX9485_MCLKOUT 0
|
||||
#define MAX9485_CLKOUT 1
|
||||
#define MAX9485_CLKOUT1 2
|
||||
#define MAX9485_CLKOUT2 3
|
||||
|
||||
#endif /* __DT_BINDINGS_MAX9485_CLK_H */
|
||||
@ -72,6 +72,7 @@
|
||||
#define CLK_USIM 58
|
||||
#define CLK_USIM1 59
|
||||
#define CLK_USMI0 60
|
||||
#define CLK_MAX 61
|
||||
#define CLK_OSC32k768 61
|
||||
#define CLK_MAX 62
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user