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arm64: dts: add description for solidrun cn9132 cex7 module and clearfog board
Add description for the SolidRun CN9132 COM-Express Type 7 module, and the Clearfog evaluation board. The COM-Express module includes: - CN9130 SoC - 2x 88F8215 Southbridges - eMMC - SPI Flash - DDR-4 SODIMM connector - 1GBase-T Ethernet PHY The Clearfog Evaluation board provides: - 1x 10Gbps SFP+ - 2x 5GBase-T RJ45 - 4x 1GBase-T RJ45 on DSA switch with 2.5Gbps cpu link - 1x full-size PCI-E x4 - 2x M.2 with PCI-E x1 - 1x M.2 with PCI-E x2 - 2x M.2 with PCI-E x1 and USB-2.0 - 1x M.2 with USB-2.0, USB-3.0 and 2x SIM slots - 1x mini-PCI-E x1 - 2x SATA (Laptop-Style connector with data and power) - 3x USB-3.0 Type-A - microSD slot Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This commit is contained in:
Josua Mayer
Gregory CLEMENT
parent
1280840d20
commit
e9ff907f40
@ -31,3 +31,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-base.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-pro.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += cn9131-cf-solidwan.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += cn9132-clearfog.dtb
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673
arch/arm64/boot/dts/marvell/cn9132-clearfog.dts
Normal file
673
arch/arm64/boot/dts/marvell/cn9132-clearfog.dts
Normal file
@ -0,0 +1,673 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
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*
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* DTS for SolidRun CN9132 Clearfog.
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*
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include "cn9130.dtsi"
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#include "cn9132-sr-cex7.dtsi"
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/ {
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model = "SolidRun CN9132 Clearfog";
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compatible = "solidrun,cn9132-clearfog",
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"solidrun,cn9132-sr-cex7", "marvell,cn9130";
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aliases {
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ethernet1 = &cp0_eth2;
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ethernet2 = &cp0_eth0;
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ethernet3 = &cp2_eth0;
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ethernet4 = &cp1_eth0;
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i2c7 = &carrier_mpcie_i2c;
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i2c8 = &carrier_ptp_i2c;
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mmc1 = &cp0_sdhci0;
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_wake0_pins>;
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button-0 {
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label = "SW2";
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gpios = <&cp1_gpio2 8 GPIO_ACTIVE_LOW>;
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linux,can-disable;
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linux,code = <BTN_2>;
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_batlow_pins &cp2_rsvd4_pins>;
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/* LED11 */
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led-io-0 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_DISK;
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function-enumerator = <0>;
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default-state = "off";
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gpios = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
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};
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/* LED12 */
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led-io-1 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_DISK;
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function-enumerator = <1>;
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default-state = "off";
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gpios = <&cp2_gpio1 4 GPIO_ACTIVE_HIGH>;
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};
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};
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/* CON4 W_DISABLE1/W_DISABLE2 */
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rfkill-m2-wlan {
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compatible = "rfkill-gpio";
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label = "m.2 wlan (CON4)";
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radio-type = "wlan";
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_10g_phy_rst_01_pins>;
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/* rfkill-gpio inverts internally */
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shutdown-gpios = <&cp1_gpio2 11 GPIO_ACTIVE_HIGH>;
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};
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/* CON5 W_DISABLE1/W_DISABLE2 */
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rfkill-m2-wlan {
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compatible = "rfkill-gpio";
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label = "m.2 wlan (CON5)";
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radio-type = "wlan";
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_10g_phy_rst_23_pins>;
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/* rfkill-gpio inverts internally */
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shutdown-gpios = <&cp1_gpio2 10 GPIO_ACTIVE_HIGH>;
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};
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/* J21 W_DISABLE1 */
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rfkill-m2-wwan {
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compatible = "rfkill-gpio";
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label = "m.2 wwan (J21)";
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radio-type = "wwan";
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pinctrl-names = "default";
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pinctrl-0 = <&cp2_rsvd3_pins>;
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/* rfkill-gpio inverts internally */
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shutdown-gpios = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
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};
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/* J21 W_DISABLE1 */
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rfkill-m2-gnss {
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compatible = "rfkill-gpio";
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label = "m.2 gnss (J21)";
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radio-type = "gps";
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pinctrl-names = "default";
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pinctrl-0 = <&cp2_rsvd8_pins>;
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/* rfkill-gpio inverts internally */
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shutdown-gpios = <&cp2_gpio1 8 GPIO_ACTIVE_HIGH>;
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};
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/* J14 W_DISABLE */
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rfkill-mpcie-wlan {
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compatible = "rfkill-gpio";
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label = "mpcie wlan (J14)";
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radio-type = "wlan";
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pinctrl-names = "default";
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pinctrl-0 = <&cp2_rsvd2_pins>;
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/* rfkill-gpio inverts internally */
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shutdown-gpios = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
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};
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sfp: sfp {
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compatible = "sff,sfp";
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i2c-bus = <&com_10g_sfp_i2c0>;
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pinctrl-names = "default";
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pinctrl-0 = <&com_10g_int0_pins>;
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mod-def0-gpios = <&cp0_gpio1 24 GPIO_ACTIVE_LOW>;
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maximum-power-milliwatt = <2000>;
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};
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};
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&com_smbus {
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/* This bus is also routed to STM32 BMC Microcontroller (U2) */
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power-sensor@40 {
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compatible = "ti,ina220";
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reg = <0x40>;
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#io-channel-cells = <1>;
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label = "vdd_12v0";
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shunt-resistor = <2000>;
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};
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adc@48 {
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compatible = "ti,tla2021";
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reg = <0x48>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* supplied by chaoskey hardware noise generator circuit */
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channel@0 {
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reg = <0>;
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};
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};
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};
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&cp0_eth_phy0 {
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/*
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* Configure LEDs default behaviour:
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* - LED[0]: link is 1000Mbps: On (yellow): 0111
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* - LED[1]: link/activity: On/Blink (green): 0001
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* - LED[2]: Off (green): 1000
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*/
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marvell,reg-init = <3 16 0xf000 0x0817>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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/* link */
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reg = <0>;
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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led@1 {
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/* act */
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reg = <1>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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led@2 {
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/* 1000 */
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reg = <2>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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};
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};
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/* SRDS #4 - 10GE */
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&cp0_eth0 {
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phys = <&cp0_comphy4 0>;
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phy-mode = "10gbase-r";
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managed = "in-band-status";
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sfp = <&sfp>;
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status = "okay";
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};
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&cp0_eth2 {
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phy-mode = "2500base-x";
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phys = <&cp0_comphy5 2>;
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status = "okay";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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&cp0_i2c1 {
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/*
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* Both COM and Carrier Board have a PCA9547 i2c mux at 0x77.
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* Describe them as a single device merging each child bus.
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*/
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i2c-mux@77 {
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i2c@0 {
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/* Routed to Full PCIe (J4) */
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};
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i2c@1 {
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/* Routed to USB Hub (U29) */
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};
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i2c@2 {
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/* Routed to M.2 (CON4) */
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};
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i2c@3 {
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/* Routed to M.2 (CON5) */
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};
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i2c@4 {
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/* Routed to M.2 (J21) */
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};
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carrier_mpcie_i2c: i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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/* Routed to mini-PCIe (J14) */
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};
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carrier_ptp_i2c: i2c@6 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <6>;
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/* Routed to various optional PTP related components */
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};
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};
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};
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&cp0_mdio {
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ethernet-switch@4 {
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compatible = "marvell,mv88e6085";
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reg = <4>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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sw_phy1: ethernet-phy@1 {
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reg = <0x11>;
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};
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sw_phy2: ethernet-phy@2 {
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reg = <0x12>;
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};
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sw_phy3: ethernet-phy@3 {
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reg = <0x13>;
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};
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sw_phy4: ethernet-phy@4 {
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reg = <0x14>;
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};
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};
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-port@1 {
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reg = <1>;
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label = "lan1";
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phy-handle = <&sw_phy1>;
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phy-mode = "internal";
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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};
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};
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ethernet-port@2 {
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reg = <2>;
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label = "lan2";
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phy-handle = <&sw_phy2>;
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phy-mode = "internal";
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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};
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};
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ethernet-port@3 {
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reg = <3>;
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label = "lan3";
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phy-handle = <&sw_phy3>;
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phy-mode = "internal";
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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};
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};
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ethernet-port@4 {
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reg = <4>;
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label = "lan4";
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phy-handle = <&sw_phy4>;
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phy-mode = "internal";
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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};
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};
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ethernet-port@5 {
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reg = <5>;
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label = "cpu";
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ethernet = <&cp0_eth2>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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};
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};
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};
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/* SRDS #0,#1,#2,#3 - PCIe */
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&cp0_pcie0 {
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num-lanes = <4>;
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phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
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status = "okay";
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};
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&cp0_pinctrl {
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/*
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* configure unused gpios exposed via pin headers:
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* - J7-10: PWRBTN
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*/
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_pwrbtn_pins>;
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};
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/* microSD */
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&cp0_sdhci0 {
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pinctrl-0 = <&cp0_mmc0_pins>, <&cp0_mmc0_cd_pins>;
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pinctrl-names = "default";
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bus-width = <4>;
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no-1-8-v;
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status = "okay";
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};
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&cp0_spi1 {
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/* add CS1 */
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pinctrl-0 = <&cp0_spi1_pins>, <&cp0_spi1_cs1_pins>;
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flash@1 {
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compatible = "jedec,spi-nor";
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reg = <1>;
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/* read command supports max. 50MHz */
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spi-max-frequency = <50000000>;
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};
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};
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/* J38 */
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&cp0_uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_uart2_pins>;
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status = "okay";
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};
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&cp0_utmi {
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/* M.2 "CON5" swaps D+/D- */
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||||
swap-dx-lanes = <1>;
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};
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||||
&cp1_ethernet {
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status = "okay";
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||||
};
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||||
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||||
/* SRDS #2 - 5GE */
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||||
&cp1_eth0 {
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phys = <&cp1_comphy2 0>;
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||||
phy-mode = "5gbase-r";
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||||
phy = <&cp1_eth_phy0>;
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managed = "in-band-status";
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status = "okay";
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||||
};
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||||
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||||
/* SRDS #0,#1 - PCIe */
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&cp1_pcie0 {
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num-lanes = <2>;
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phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
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status = "okay";
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||||
};
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||||
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/* SRDS #4 - PCIe */
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&cp1_pcie1 {
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num-lanes = <1>;
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||||
phys = <&cp1_comphy4 1>;
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||||
status = "okay";
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||||
};
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||||
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||||
/* SRDS #5 - PCIe */
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&cp1_pcie2 {
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num-lanes = <1>;
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||||
phys = <&cp1_comphy5 2>;
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status = "okay";
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||||
};
|
||||
|
||||
&cp1_pinctrl {
|
||||
/*
|
||||
* configure unused gpios exposed via pin headers:
|
||||
* - J7-8: RSVD16
|
||||
* - J7-10: THRM
|
||||
* - J10-1: WAKE1
|
||||
* - J10-2: SATA_ACT
|
||||
* - J10-8: THERMTRIP
|
||||
*/
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_rsvd16_pins &cp1_sata_act_pins &cp1_thrm_irq_pins>,
|
||||
<&cp1_thrm_trip_pins &cp1_wake1_pins>;
|
||||
};
|
||||
|
||||
/* SRDS #3 - SATA */
|
||||
&cp1_sata0 {
|
||||
status = "okay";
|
||||
|
||||
/* only port 1 is available */
|
||||
/delete-node/ sata-port@0;
|
||||
|
||||
sata-port@1 {
|
||||
phys = <&cp1_comphy3 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp1_utmi {
|
||||
/* M.2 "CON4" swaps D+/D- */
|
||||
swap-dx-lanes = <0>;
|
||||
};
|
||||
|
||||
&cp1_xmdio {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_xmdio_pins>;
|
||||
status = "okay";
|
||||
|
||||
cp1_eth_phy0: ethernet-phy@8 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <8>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&com_10g_int1_pins>;
|
||||
interrupt-parent = <&cp1_gpio2>;
|
||||
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_YELLOW>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
led@2 {
|
||||
reg = <2>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp2_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SRDS #2 - 5GE */
|
||||
&cp2_eth0 {
|
||||
phys = <&cp2_comphy2 0>;
|
||||
phy-mode = "5gbase-r";
|
||||
phy = <&cp2_eth_phy0>;
|
||||
managed = "in-band-status";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_gpio1 {
|
||||
pinctrl-names= "default";
|
||||
pinctrl-0 = <&cp2_rsvd9_pins>;
|
||||
|
||||
/* J21 */
|
||||
m2-wwan-reset-hog {
|
||||
gpio-hog;
|
||||
gpios = <9 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
|
||||
output-low;
|
||||
line-name = "m2-wwan-reset";
|
||||
};
|
||||
};
|
||||
|
||||
/* SRDS #0 - PCIe */
|
||||
&cp2_pcie0 {
|
||||
num-lanes = <1>;
|
||||
phys = <&cp2_comphy0 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SRDS #4 - PCIe */
|
||||
&cp2_pcie1 {
|
||||
num-lanes = <1>;
|
||||
phys = <&cp2_comphy4 1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SRDS #5 - PCIe */
|
||||
&cp2_pcie2 {
|
||||
num-lanes = <1>;
|
||||
phys = <&cp2_comphy5 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_pinctrl {
|
||||
/*
|
||||
* configure unused gpios exposed via pin headers:
|
||||
* - J7-1: RSVD10
|
||||
* - J7-3: RSVD11
|
||||
* - J7-5: RSVD56
|
||||
* - J7-6: RSVD7
|
||||
* - J7-7: RSVD27
|
||||
* - J10-3: RSVD31
|
||||
* - J10-5: RSVD5
|
||||
* - J10-6: RSVD32
|
||||
* - J10-7: RSVD0
|
||||
* - J10-9: RSVD1
|
||||
*/
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp2_rsvd0_pins &cp2_rsvd1_pins &cp2_rsvd5_pins>,
|
||||
<&cp2_rsvd7_pins &cp2_rsvd10_pins &cp2_rsvd11_pins>,
|
||||
<&cp2_rsvd27_pins &cp2_rsvd31_pins &cp2_rsvd32_pins>,
|
||||
<&cp2_rsvd56_pins>;
|
||||
};
|
||||
|
||||
/* SRDS #3 - SATA */
|
||||
&cp2_sata0 {
|
||||
status = "okay";
|
||||
|
||||
/* only port 1 is available */
|
||||
/delete-node/ sata-port@0;
|
||||
|
||||
sata-port@1 {
|
||||
phys = <&cp2_comphy3 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp2_xmdio {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp2_xmdio_pins>;
|
||||
status = "okay";
|
||||
|
||||
cp2_eth_phy0: ethernet-phy@8 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <8>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&com_10g_int2_pins>;
|
||||
interrupt-parent = <&cp2_gpio2>;
|
||||
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_YELLOW>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
led@2 {
|
||||
reg = <2>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
712
arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi
Normal file
712
arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi
Normal file
@ -0,0 +1,712 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/*
|
||||
* Instantiate the first external CP115
|
||||
*/
|
||||
|
||||
#define CP11X_NAME cp1
|
||||
#define CP11X_BASE f4000000
|
||||
#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
|
||||
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
|
||||
#define CP11X_PCIE0_BASE f4600000
|
||||
#define CP11X_PCIE1_BASE f4620000
|
||||
#define CP11X_PCIE2_BASE f4640000
|
||||
|
||||
#include "armada-cp115.dtsi"
|
||||
|
||||
#undef CP11X_NAME
|
||||
#undef CP11X_BASE
|
||||
#undef CP11X_PCIEx_MEM_BASE
|
||||
#undef CP11X_PCIEx_MEM_SIZE
|
||||
#undef CP11X_PCIE0_BASE
|
||||
#undef CP11X_PCIE1_BASE
|
||||
#undef CP11X_PCIE2_BASE
|
||||
|
||||
/*
|
||||
* Instantiate the second external CP115
|
||||
*/
|
||||
|
||||
#define CP11X_NAME cp2
|
||||
#define CP11X_BASE f6000000
|
||||
#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
|
||||
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
|
||||
#define CP11X_PCIE0_BASE f6600000
|
||||
#define CP11X_PCIE1_BASE f6620000
|
||||
#define CP11X_PCIE2_BASE f6640000
|
||||
|
||||
#include "armada-cp115.dtsi"
|
||||
|
||||
#undef CP11X_NAME
|
||||
#undef CP11X_BASE
|
||||
#undef CP11X_PCIEx_MEM_BASE
|
||||
#undef CP11X_PCIEx_MEM_SIZE
|
||||
#undef CP11X_PCIE0_BASE
|
||||
#undef CP11X_PCIE1_BASE
|
||||
#undef CP11X_PCIE2_BASE
|
||||
|
||||
/ {
|
||||
model = "SolidRun CN9132 COM Express Type 7 Module";
|
||||
compatible = "solidrun,cn9132-sr-cex7", "marvell,cn9130";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &cp0_eth1;
|
||||
gpio3 = &cp1_gpio1;
|
||||
gpio4 = &cp1_gpio2;
|
||||
gpio5 = &cp2_gpio1;
|
||||
gpio6 = &cp2_gpio2;
|
||||
i2c0 = &cp0_i2c0;
|
||||
i2c1 = &cp0_i2c1;
|
||||
i2c2 = &com_clkgen_i2c;
|
||||
i2c3 = &com_10g_led_i2c;
|
||||
i2c4 = &com_10g_sfp_i2c0;
|
||||
i2c5 = &com_smbus;
|
||||
i2c6 = &com_fanctrl_i2c;
|
||||
mmc0 = &ap_sdhci0;
|
||||
rtc0 = &cp0_rtc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
fan: pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
cooling-levels = <0 51 102 153 204 255>;
|
||||
#cooling-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_fan_pwm_pins &cp0_fan_tacho_pins>;
|
||||
pwms = <&cp0_gpio2 7 40000>;
|
||||
interrupt-parent = <&cp0_gpio1>;
|
||||
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
|
||||
v_1_8: regulator-1-8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
ap_vhv: regulator-ap-vhv-1-8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "ap-vhv-1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
pinctrl-0 = <&cp0_reg_ap_vhv_pins>;
|
||||
pinctrl-names = "default";
|
||||
gpios = <&cp0_gpio2 21 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
cp_vhv: regulator-cp-vhv-1-8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "cp-vhv-1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
pinctrl-0 = <&cp0_reg_cp_vhv_pins>;
|
||||
pinctrl-names = "default";
|
||||
gpios = <&cp0_gpio2 17 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&ap_pinctrl {
|
||||
ap_mmc0_pins: ap-mmc0-pins {
|
||||
marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", "mpp4", "mpp5",
|
||||
"mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp12";
|
||||
marvell,function = "sdio";
|
||||
/*
|
||||
* mpp12 is emmc reset, function should be sdio (hw_rst),
|
||||
* but pinctrl-mvebu does not support this.
|
||||
*
|
||||
* From pinctrl-mvebu.h:
|
||||
* "The name will be used to switch to this setting in DT description, e.g.
|
||||
* marvell,function = "uart2". subname is only for debugging purposes."
|
||||
*/
|
||||
};
|
||||
};
|
||||
|
||||
&ap_sdhci0 {
|
||||
bus-width = <8>;
|
||||
pinctrl-0 = <&ap_mmc0_pins>;
|
||||
pinctrl-names = "default";
|
||||
vqmmc-supply = <&v_1_8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ap_thermal_ic {
|
||||
polling-delay = <1000>;
|
||||
|
||||
trips {
|
||||
ap_active: trip-active {
|
||||
temperature = <40000>;
|
||||
hysteresis = <4000>;
|
||||
type = "active";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&ap_active>;
|
||||
cooling-device = <&fan THERMAL_NO_LIMIT 4>;
|
||||
};
|
||||
|
||||
map1 {
|
||||
trip = <&ap_crit>;
|
||||
cooling-device = <&fan 4 5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_eth1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_eth1_pins>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy = <&cp0_eth_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_gpio1 {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* Tacho signal used as interrupt source by pwm-fan driver.
|
||||
* Hog IO as input to ensure mvebu-gpio irq driver`s
|
||||
* irq_set_type can succeed.
|
||||
*/
|
||||
pwm-tacho-irq-hog {
|
||||
gpio-hog;
|
||||
gpios = <26 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
|
||||
input;
|
||||
line-name = "fan-tacho";
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_i2c0_pins>;
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
|
||||
com_eeprom: eeprom@50 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
pagesize = <8>;
|
||||
};
|
||||
|
||||
eeprom@53 {
|
||||
compatible = "atmel,spd";
|
||||
reg = <0x53>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_i2c1_pins>;
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
|
||||
i2c-mux@77 {
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x77>;
|
||||
i2c-mux-idle-disconnect;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
com_clkgen_i2c: i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
/* clock-controller@6b */
|
||||
};
|
||||
|
||||
com_10g_led_i2c: i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
/* Routed to B2B Connector as I2C_10G_LED_SCL/SDA */
|
||||
};
|
||||
|
||||
com_10g_sfp_i2c0: i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
|
||||
/* Routed to B2B Connector as I2C_SFP0_CP0_SCL/SDA */
|
||||
};
|
||||
|
||||
com_smbus: i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
|
||||
/* Routed to B2B Connector as SBM_CLK/DAT */
|
||||
};
|
||||
|
||||
com_fanctrl_i2c: i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
|
||||
/* fan-controller@2f (assembly option) */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_mdio {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_mdio_pins>;
|
||||
status = "okay";
|
||||
|
||||
cp0_eth_phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_spi1_pins>;
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
/* read command supports max. 50MHz */
|
||||
spi-max-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_syscon0 {
|
||||
cp0_pinctrl: pinctrl {
|
||||
compatible = "marvell,cp115-standalone-pinctrl";
|
||||
|
||||
com_10g_int0_pins: cp0-10g-int-pins {
|
||||
marvell,pins = "mpp24";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp0_eth1_pins: cp0-eth1-pins {
|
||||
marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
|
||||
"mpp4", "mpp5", "mpp6", "mpp7",
|
||||
"mpp8", "mpp9", "mpp10", "mpp11";
|
||||
/* docs call it "ge1", but cp110-pinctrl "ge0" */
|
||||
marvell,function = "ge0";
|
||||
};
|
||||
|
||||
cp0_fan_pwm_pins: cp0-fan-pwm-pins {
|
||||
marvell,pins = "mpp39";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp0_fan_tacho_pins: cp0-fan-tacho-pins {
|
||||
marvell,pins = "mpp26";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp0_i2c0_pins: cp0-i2c0-pins {
|
||||
marvell,pins = "mpp37", "mpp38";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
|
||||
cp0_i2c1_pins: cp0-i2c1-pins {
|
||||
marvell,pins = "mpp35", "mpp36";
|
||||
marvell,function = "i2c1";
|
||||
};
|
||||
|
||||
cp0_mdio_pins: cp0-mdio-pins {
|
||||
marvell,pins = "mpp40", "mpp41";
|
||||
marvell,function = "ge";
|
||||
};
|
||||
|
||||
cp0_mmc0_pins: cp0-mmc0-pins {
|
||||
marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59",
|
||||
"mpp60", "mpp61";
|
||||
marvell,function = "sdio";
|
||||
};
|
||||
|
||||
cp0_mmc0_cd_pins: cp0-mmc0-cd-pins {
|
||||
marvell,pins = "mpp55";
|
||||
marvell,function = "sdio_cd";
|
||||
};
|
||||
|
||||
cp0_pwrbtn_pins: cp0-pwrbtn-pins {
|
||||
marvell,pins = "mpp31";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp0_reg_ap_vhv_pins: cp0-reg-ap-vhv-pins {
|
||||
marvell,pins = "mpp53";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp0_reg_cp_vhv_pins: cp0-reg-cp-vhv-pins {
|
||||
marvell,pins = "mpp49";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp0_spi1_pins: cp0-spi1-pins {
|
||||
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
|
||||
cp0_spi1_cs1_pins: cp0-spi1-cs1-pins {
|
||||
marvell,pins = "mpp12";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
|
||||
cp0_uart2_pins: cp0-uart2-pins {
|
||||
marvell,pins = "mpp50", "mpp51";
|
||||
marvell,function = "uart2";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_thermal_ic {
|
||||
polling-delay = <1000>;
|
||||
|
||||
trips {
|
||||
cp0_active: trip-active {
|
||||
temperature = <40000>;
|
||||
hysteresis = <4000>;
|
||||
type = "active";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cp0_active>;
|
||||
cooling-device = <&fan THERMAL_NO_LIMIT 4>;
|
||||
};
|
||||
|
||||
map1 {
|
||||
trip = <&cp0_crit>;
|
||||
cooling-device = <&fan 4 5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* USB-2.0 Host */
|
||||
&cp0_usb3_0 {
|
||||
phys = <&cp0_utmi0>;
|
||||
phy-names = "utmi";
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* USB-2.0 Host */
|
||||
&cp0_usb3_1 {
|
||||
phys = <&cp0_utmi1>;
|
||||
phy-names = "utmi";
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_utmi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_rtc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp1_spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_spi1_pins>;
|
||||
status = "okay";
|
||||
|
||||
tpm@0 {
|
||||
reg = <0>;
|
||||
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
|
||||
spi-max-frequency = <10000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_tpm_irq_pins>;
|
||||
interrupt-parent = <&cp1_gpio1>;
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp1_syscon0 {
|
||||
cp1_pinctrl: pinctrl {
|
||||
compatible = "marvell,cp115-standalone-pinctrl";
|
||||
|
||||
com_10g_int1_pins: cp1-10g-int-pins {
|
||||
marvell,pins = "mpp50";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_10g_phy_rst_01_pins: cp1-10g-phy-rst-01-pins {
|
||||
marvell,pins = "mpp43";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_10g_phy_rst_23_pins: cp1-10g-phy-rst-23-pins {
|
||||
marvell,pins = "mpp42";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_batlow_pins: cp1-batlow-pins {
|
||||
marvell,pins = "mpp11";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_rsvd16_pins: cp1-rsvd16-pins {
|
||||
marvell,pins = "mpp29";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_sata_act_pins: cp1-sata-act-pins {
|
||||
marvell,pins = "mpp39";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_spi1_pins: cp1-spi1-pins {
|
||||
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
|
||||
cp1_thrm_irq_pins: cp1-thrm-irq-pins {
|
||||
marvell,pins = "mpp34";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_thrm_trip_pins: cp1-thrm-trip-pins {
|
||||
marvell,pins = "mpp33";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_tpm_irq_pins: cp1-tpm-irq-pins {
|
||||
marvell,pins = "mpp17";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_wake0_pins: cp1-wake0-pins {
|
||||
marvell,pins = "mpp40";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_wake1_pins: cp1-wake1-pins {
|
||||
marvell,pins = "mpp51";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_xmdio_pins: cp1-xmdio-pins {
|
||||
marvell,pins = "mpp37", "mpp38";
|
||||
marvell,function = "xg";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp1_thermal_ic {
|
||||
polling-delay = <1000>;
|
||||
|
||||
trips {
|
||||
cp1_active: trip-active {
|
||||
temperature = <40000>;
|
||||
hysteresis = <4000>;
|
||||
type = "active";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cp1_active>;
|
||||
cooling-device = <&fan THERMAL_NO_LIMIT 4>;
|
||||
};
|
||||
|
||||
map1 {
|
||||
trip = <&cp1_crit>;
|
||||
cooling-device = <&fan 4 5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* USB-2.0 Host */
|
||||
&cp1_usb3_0 {
|
||||
phys = <&cp1_utmi0>;
|
||||
phy-names = "utmi";
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_utmi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_rtc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp2_syscon0 {
|
||||
cp2_pinctrl: pinctrl {
|
||||
compatible = "marvell,cp115-standalone-pinctrl";
|
||||
|
||||
com_10g_int2_pins: cp2-10g-int-pins {
|
||||
marvell,pins = "mpp50";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd0_pins: cp2-rsvd0-pins {
|
||||
marvell,pins = "mpp0";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd1_pins: cp2-rsvd1-pins {
|
||||
marvell,pins = "mpp1";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd2_pins: cp2-rsvd2-pins {
|
||||
marvell,pins = "mpp2";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd3_pins: cp2-rsvd3-pins {
|
||||
marvell,pins = "mpp3";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd4_pins: cp2-rsvd4-pins {
|
||||
marvell,pins = "mpp4";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd5_pins: cp2-rsvd5-pins {
|
||||
marvell,pins = "mpp54";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd7_pins: cp2-rsvd7-pins {
|
||||
marvell,pins = "mpp7";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd8_pins: cp2-rsvd8-pins {
|
||||
marvell,pins = "mpp8";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd9_pins: cp2-rsvd9-pins {
|
||||
marvell,pins = "mpp9";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd10_pins: cp2-rsvd10-pins {
|
||||
marvell,pins = "mpp10";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd11_pins: cp2-rsvd11-pins {
|
||||
marvell,pins = "mpp11";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd27_pins: cp2-rsvd27-pins {
|
||||
marvell,pins = "mpp11";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd31_pins: cp2-rsvd31-pins {
|
||||
marvell,pins = "mpp31";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd32_pins: cp2-rsvd32-pins {
|
||||
marvell,pins = "mpp32";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd55_pins: cp2-rsvd55-pins {
|
||||
marvell,pins = "mpp55";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd56_pins: cp2-rsvd56-pins {
|
||||
marvell,pins = "mpp56";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_xmdio_pins: cp2-xmdio-pins {
|
||||
marvell,pins = "mpp37", "mpp38";
|
||||
marvell,function = "xg";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp2_thermal_ic {
|
||||
polling-delay = <1000>;
|
||||
|
||||
trips {
|
||||
cp2_active: trip-active {
|
||||
temperature = <40000>;
|
||||
hysteresis = <4000>;
|
||||
type = "active";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cp2_active>;
|
||||
cooling-device = <&fan THERMAL_NO_LIMIT 4>;
|
||||
};
|
||||
|
||||
map1 {
|
||||
trip = <&cp2_crit>;
|
||||
cooling-device = <&fan 4 5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* USB-2.0/3.0 Host */
|
||||
&cp2_usb3_0 {
|
||||
phys = <&cp2_utmi0>, <&cp2_comphy1 0>;
|
||||
phy-names = "utmi", "comphy";
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_utmi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* AP default console */
|
||||
&uart0 {
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user