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ASoC: tas2770: Set correct FSYNC polarity
Fix setting of FSYNC polarity for DAI formats other than I2S. Also
add support for polarity inversion.
Fixes: 1a476abc72
("tas2770: add tas2770 smart PA kernel driver")
Signed-off-by: Martin Povišer <povik+lin@cutebit.org>
Link: https://lore.kernel.org/r/20220808141246.5749-2-povik+lin@cutebit.org
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
parent
d5beb74f17
commit
e9ac31f0a5
@ -337,7 +337,7 @@ static int tas2770_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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struct snd_soc_component *component = dai->component;
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struct tas2770_priv *tas2770 =
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snd_soc_component_get_drvdata(component);
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u8 tdm_rx_start_slot = 0, asi_cfg_1 = 0;
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u8 tdm_rx_start_slot = 0, invert_fpol = 0, fpol_preinv = 0, asi_cfg_1 = 0;
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int ret;
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switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
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@ -349,9 +349,15 @@ static int tas2770_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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}
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_IF:
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invert_fpol = 1;
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fallthrough;
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case SND_SOC_DAIFMT_NB_NF:
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asi_cfg_1 |= TAS2770_TDM_CFG_REG1_RX_RSING;
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break;
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case SND_SOC_DAIFMT_IB_IF:
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invert_fpol = 1;
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fallthrough;
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case SND_SOC_DAIFMT_IB_NF:
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asi_cfg_1 |= TAS2770_TDM_CFG_REG1_RX_FALING;
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break;
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@ -369,15 +375,19 @@ static int tas2770_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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tdm_rx_start_slot = 1;
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fpol_preinv = 0;
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break;
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case SND_SOC_DAIFMT_DSP_A:
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tdm_rx_start_slot = 0;
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fpol_preinv = 1;
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break;
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case SND_SOC_DAIFMT_DSP_B:
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tdm_rx_start_slot = 1;
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fpol_preinv = 1;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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tdm_rx_start_slot = 0;
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fpol_preinv = 1;
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break;
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default:
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dev_err(tas2770->dev,
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@ -391,6 +401,14 @@ static int tas2770_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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if (ret < 0)
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return ret;
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ret = snd_soc_component_update_bits(component, TAS2770_TDM_CFG_REG0,
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TAS2770_TDM_CFG_REG0_FPOL_MASK,
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(fpol_preinv ^ invert_fpol)
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? TAS2770_TDM_CFG_REG0_FPOL_RSING
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: TAS2770_TDM_CFG_REG0_FPOL_FALING);
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if (ret < 0)
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return ret;
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return 0;
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}
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@ -41,6 +41,9 @@
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#define TAS2770_TDM_CFG_REG0_31_44_1_48KHZ 0x6
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#define TAS2770_TDM_CFG_REG0_31_88_2_96KHZ 0x8
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#define TAS2770_TDM_CFG_REG0_31_176_4_192KHZ 0xa
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#define TAS2770_TDM_CFG_REG0_FPOL_MASK BIT(0)
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#define TAS2770_TDM_CFG_REG0_FPOL_RSING 0
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#define TAS2770_TDM_CFG_REG0_FPOL_FALING 1
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/* TDM Configuration Reg1 */
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#define TAS2770_TDM_CFG_REG1 TAS2770_REG(0X0, 0x0B)
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#define TAS2770_TDM_CFG_REG1_MASK GENMASK(5, 1)
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